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e) or extra holes (p-type)
ting, insulating and tran-
hnologies.
s.
ciples of VLSI Design CMOS BasicsS: Metal Oxide Semiconductor
Transistors are built on a Silicon (semiconductor) substrate.
Pure silicon has no free carriers and conducts poorly.
Dopants are added to increase conductivity: extra electrons (n-typ
MOS structure created by superimposing several layers of conducsistor-forming materials.
Metal gate has been replaced by polysilicon or poly in modern tec
There are two types of MOS transistors:
nMOS : Negatively doped silicon, rich in electron
pMOS : Positively doped silicon, rich in holes.
CMOS: Both type of transistors are used to construct any gate.
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nM.
n+
Drain
bulk Si
SiO2
Polysilicon
ciples of VLSI Design CMOS BasicsOS and pMOS
Four terminal devices: Source, Gate, Drain, body (substrate, bulk)
p
GateSource
n+
Source Gate Drain
n+n+ p substrate
ThinOxide
nMOSL
W
pMOSSiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
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CM
VDD
sistor
substrate contact (cc)
on contact (cc)urce)
layer #1
layer #2layer #3
n+
n-well (nwell)
nd)
ciples of VLSI Design CMOS BasicsOS Inverter Cross-Section
n+n+p+
glass(insulator)
metal2 metal1m1-m2 contact (via)p-substrate contact (cc)
n-diffusion contact (cc)
polysilicon gate (poly )n-transistor p-tran
GND
n-
p-diffusi
(source)
(so
(Out)
p+p+(drains)
Cadence Layer's for AMI 0.6mm technology
p substrate (black backgrou
(nactive)
(pactive)
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CM
ciples of VLSI Design CMOS BasicsOS Cadence Layout
Cadence Layout for the inverter on previous slide
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rce (S), gate (G) (con-
day, .....)
g = 1
s
d
s
d
ON
OFF
ciples of VLSI Design CMOS BasicsS Transistor Switches
We can treat MOS transistors as simple on-off switches with a soutrols the state of the switch) and drain (D).
1 represents high voltage, VDD (5V, 3.3V, 1.8V, 1.2V, <=1.0V to
0 represent low voltage - GND or VSS. (0V for digital circuits)
gs
d
g = 0
s
d
gs
d
s
d
nMOS
pMOS
OFF
ON
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Sig
source current
have no effect.ifference of at least Vt
tors produce signals with
GND + Vt).
*** Strong 1***
0
1
pMOS
ciples of VLSI Design CMOS Basicsnal Strengths
Signals such as 1 and 0 have strengths, measures ability to sink or VDD and GND Rails are the strongest 1 and 0
Under the switch abstraction, G has complete control and S and DIn reality, the gate can turn the switch on only if a potential d
exists between the G and S.We will look at Vt in detail later on in the course.
Thus signal strengths are related to Vt and therefore p and n transisdifferent strengths
Strong 1: VDD, Strong 0: GND, Weak 1 :(~VDD -Vt) and Weak 0 :(~
0
1
1
1
*** Strong 0*** Weak 1
0
0
Weak 0
nMOSS D S D
G G
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CM
TH D IDEA. WHY?
O
ciples of VLSI Design CMOS BasicsOS Inverter
E CONFIGURATION BELOW FOR A BUFFER IS NOT A GOO
Vdd
CMOS Inverter
P1
N1
A OutA O
0 1
1 0
A
Vdd
N1
A
Out
BAD IDEAP1
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NA
A B C
0 0 1
0 1 1
1 0 1
1 1 0
A B C
0 0 1
0 1 0
1 0 0
1 1 0
ciples of VLSI Design CMOS BasicsND and NOR CMOS Gates
AB C
AB C
Vdd
BOut
A P1
P2
N1 N2
Vdd
A B
OutP1 P2
N2
N1
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Pa
at the drain.sed as switches.
ded outputs, if only one
strong 0Output
degraded 1
degraded 0Output
strong 1
= 1
= 1
= 0
= 0
ciples of VLSI Design CMOS Basicsss Transistor
The off-state of a transistor creates a high impedance condition Z No current flows from source to drain. So transistors can be u
However, as we previously discussed this will produce degratransistor is used as a switch.
g
s d
g = 0s d
g = 1s d
0Input
1
g
s d
g = 0s d
g = 1s d
0Input
g
g
g
g
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Tr
nected to VDD or GND.
of a signal on In to Out.
buffers.
strong 0
Output
strong 1
gb = 0
gb = 0
ciples of VLSI Design CMOS Basicsansmission Gates
P1N1
In Out
A
A
One pMOS and one nMOS in parallel.Note that neither transistor is con
A and A control the transmission
Transmission gates act as tristate
g = 0, gb = 1a b
g = 1, gb = 0a b
0
Input
1
g
gb
a b
a bg
gb
a bg
gb
a bg
gb
g = 1,
g = 1,
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Tr
gates?
Out
ciples of VLSI Design CMOS Basicsansmission Gate Application: Select Mux
How many transistors are required to implement this using CMOS
Select
In Out
Select
VDD
Select
Select
A
B
Transmission Gate 2-to-1 MUX
Select Out
0
1
B
A
Truth Table for 2-to-1 MUX
Out = A.S + B.S
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D
Q
Q
ciples of VLSI Design CMOS BasicsLatch
CLK
D Q
Latc
h D
CLK
Q
Positivelevel-sensitive
latch
1
0
D
CLK
QCLK
CLKCLK
CLK
DQ
If CLK is unavailable one extra inverter needed to generate it using CLK
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D
ed
CLK
CLK
Q
using CLK
Slave
ciples of VLSI Design CMOS BasicsFlip-Flop
Positivege-triggered
flip-flop
Flop
CLK
D Q
D
CLK
Q
master-slaveflip-flop
a.k.a
QMCLK
CLKCLK
CLK
CLK
CLK
D
Latc
h
Latc
h
D QQM
CLK
CLK
If CLK is unavailable one extra inverter needed to generate it
Master
Master Slave
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D
Q
Q
Q
Q
ciples of VLSI Design CMOS BasicsFlip-Flop Operation
CLK = 1
D
CLK = 0
D
QM
QM
D
CLK
Q
M follows D, Q is latched
M transferred to Q, QM latched
Positiveedge-triggered
flip-flop
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Mo
Vdd
Out
ciples of VLSI Design CMOS Basicsre CMOS Gates
Vdd
P1
P2N2
N1
B
A
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An
ciples of VLSI Design CMOS Basicsd More CMOS Gates
B
A
B
Out
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An
OAI
ciples of VLSI Design CMOS Basicsd More CMOS Gates
Vdd
A
BC
D
N2
N3 N4
N1
P1P2
P4
P3