Page 1 of 12
Benha University Faculty of Engineering‐ Shoubra Electrical Engineering Department First Year Communications.
Exam Model Answer
2st Semester Exam25 ‐ May 2013
ECE 121: Electronics (I)
Duration : 3 hours
Answer all the following questions Illustrate your answers with sketches when necessary. The exam consists of three pages.
No. of questions: 5 Total Mark: 100 Marks Examiners: Dr. Ehsan Abaas – Dr. Abdallah Hammad
Question 1 (15 marks) Answer this question in the form of table. Choose the correct answer (only one answer is accepted).
1‐ The collector‐ emitter voltage is usually
(a) Less than the collector supply voltage (b) Equal to the collector supply voltage (c) More than the collector voltage (d) Cannot answer
2‐ A small collector current with zero base current is caused by the leakage current of the
(a) Emitter diode (b) Collector diode (c) Base diode (d) transistor
3‐ For the base biased circuit, if the transistor operates at the middle of the load line, a decrease of the base resistance will move the Q point
(a) Down (b) Up(c) Nowhere (d) Off the load line
4‐ When the Q point moves along the load line, VCE decreases when the collector current (a) Decreases (b) Stay the same(c) Increases (d) Non of the above
5‐ For the emitter biased circuit, when the current gain increases from 50 to 300, the collector current (a) Decreases by factor of 6 (b) Increases by a factor of 6 (c) Remains almost the same (d) Is zero
6‐ For the emitter biased circuit, if the emitter resistance increases, the collector voltage VC (a) Decreases (b) Stay the same (c) increases (d) Break down the transistor
7‐ The collector voltage of the voltage divider bias circuit is not sensitive to the change of (a) Emitter resistance (b) Supply voltage(c) Collector resistance (d) Current gain
8‐ If the emitter resistance doubles with the TSEB the collector current will (a) Stay the same (b) Increases (c) Doubles (d) Drop in half
9‐ A coupling capacitor is (a) An dc open and ac short (b) An dc short (c) A dc short and an ac open (d) An ac open
10‐ The output voltage of CE amplifier is (a) Amplified (b) Inverted (c) 180o out of phase with the input (d) All of the above
11‐ When the emitter resistance RE doubles the ac emitter resistance re’ (a) Remains the same (b) Decrease(c) Cannot be determined (d) Increases
12‐ The input impedance of the base decreases when (a) β decreases (b) β increases (c) Supply voltage increases (d) Into the base supply
13‐ If the load resistance increases in a zener regulator, the zener current (a) Decreases (b) Stays the same (c) Increases (d) = the source voltage/series resistance
14‐ The diode with a forward voltage drop of approximately 0.25 V is the (a) Step Recovery diode (b) Light emitting diode (c) Schottky diode (d) Photo diode
15‐ For the varactor diode, when the reverse voltage decreases, the capacitance (a) Stays the same (b) Decreases (c) Has more band with (d) Increases
Page 2 of 12
Question 2 (20 marks)
a‐ (6 marks) Explain, how could you implement AND and OR gates using diodes.
2 inputs AND gate:
Truth Table
Assume a diode barrier voltage of VD = 0.7 V.
There are four possible states, depending on the combination of input voltages. If at
least one input is at zero volts, then at least one diode is conducting and VO = 0.7 V. If
both V1 = V2 = 5 V
2 inputs OR gates
Truth table
The four conditions of operation of this circuit depend on various combinations of
input voltages. If V1 = V2 = 0, there is no excitation to the circuit so both diodes are off
and VO = 0. If at least one input goes to 5 V, for example, at least one diode turns on
and VO = 4.3 V, assuming VD = 0.7 V.
(The students may assume that the diode voltage drop = 0 V (ideal diode))
Page 3 of 12
b‐ (7 marks) A certain voltage doubler has 20 V rms on its input. What is the output voltage? Draw
the circuit, indicating the output terminals and PIV rating for the diode.
20
20 2 28.28
2 56.56
rms
m
out m
V V
V V
V V V
Full wave voltage doubler
PIV = 2Vm
Half Wave voltage doubler PIV = 2 Vm
(7 marks) Design a clamper to perform the function indicated in figure (1).
The design should be the following circuit: with arbitrary values of the R and C values
Page 4 of 12
Question 3 (20 marks)
a‐ (6 marks) For the zener circuit shown in figure (2). Given that , VZ1 = VZ2 = 5 V
(assume that both zener diodes have a voltage drop of 0.7 V when they are forward bias.
Explain the operation of the circuit, and then draw the o/p voltage waveform .
Two back-to-back Zeners can also be used as an ac regulator.
For the positive half cycle 2( )i Z Dv V V
Z2 will be in the reverse bias region (open circuit) so Z1 open as well
o iv v
2( )i Z Dv V V Z2 will operate in the reverse break down region (battery model VZ2 = 5), and Z1 is forward bias (0.7) Then
2( 0.7) 5.7o Zv V
For the negative half 1( )i Z Dv V V 1( )i Z Dv V V
Z1 will be in the reverse bias region (open circuit) so Z2 open as well
o iv v
1( )i Z Dv V V Z1 will operate in the reverse break down region (battery model VZ2 = 5), and Z1 is forward bias (0.7) Then
1( 0.7) 5.7o Zv V
Page 5 of 12
b‐ (6marks) Drive an expression for the ac resistance of the diode
c
● LED
mater
● LED
● Whelethe
● Themater● TheforwaLED vo
Applicswitchsystem
It (uor
Apswvo
c‐ (8 marks)
more than
character
D is a PN junc
rials such as G
D is connecte
hen the diodeectrons and he form of lighe photon enerial that fabrie output lightard current oltage drop is
cations: Indiching applicatim, Remote co
is formed byusually N typer Gold)
The Schottcapacitancfrequencie
The reducemuch high
pplication: Rewitching devicoltage power
For each of t
n 4 lines], ho
ristics LED, p
LED
tion fabricate
GaAs and GaP
d in forward
e is connectedholes recombiht (Photons) ergy depends cate the LED t from LED is
s in the range
cating ON/OFions, 7 Segmeontrol
Schottky dio
y joining a dope) with a meta
tky diode hasce and it can oes of 20 GHz o
ed junction caer switching
ectify high frece in digital csupplies (VD
the following
w could you
photo diode,
ed from sem
P
bias to emit l
d in forward bine and relea
on the energ
directly prop
e 1.5 → 2.5
F conditions,ents, Burglar a
ode
ped semicondal such as (Sil
a very little joperate at mor more
apacitance altime
equency signaomputers, an= 0.25 V)
g special purp
bias them, s
, varactor an
iconductor
ight
bias , se energy in
gy gap of the
ortional to th
Optical alarm
ductor regionver , Platinum
unction uch higher
so results in a
als, nd low
pose diodes,
state some ap
nd Schottky
he
● The phreverse b● The ph
allow ● Norma
, but ppropo
Appappl
n m
a
A vajunc
The met
Explain the p
pplications , a
diode
hotodiode is abias hotodiode hathe light to sal diode has aphotodiode hortional to the
lications: Phoications and
ractor diode tion
capacitance phod of doping
Doping
Distance from junct
Abruptdoping profile
Tunning range 4:
li i
physical cons
and finally dr
Photodiode
a PN junction
s a small transtrike the PN ja constant revhas a reverse e light intensi
oto detectionBurglar alarm
Varctor
is basically a
parameters ag Level
tion
1
di d i
struction [not
raw the IV
n that operate
nsparent windjunction verse saturatcurrent that iity
, Optical swim system
reverse biase
are controlled
Dop
Distance from j
Hyper abrudoping pro
Tunning range
d i
t
es in
dow that
ion current is directly
tching
ed pn
d by the
ping Level
junction
uptofilee 10:1
i i i
Page 7 of 12
Question 4 (20 marks)
a‐ (10 marks) For the circuit shown in figure (3)
Determine: (1) RC (2) RE (3) RB (4) VB
7.6 2.4 5.2
0.2CE C E
CE
V V V
V
The transistor operates in the active region.
0.7
0.7 2.4 0.7 3.1BE B E
B E
V V V
V V V
12 7.62.2
2
CC C C C
CC CC
C
V V I R
V VR k
I mA
800.987
1 81
22.025
0.987
2.41.185
2.025
CE
E E E
EE
E
II mA
V I R
VR k
I mA
225
80
12 3.1356
25
cB
CC B B B
CC BB
B
II A
V V I R
V VR k
I A
Page 8 of 12
b‐ (10 marks) The signal source switch of figure (4) is closed, and the transistor base current becomes
The collector characteristic of the transistor is displayed in figure
(5). If VCC = 14 V and RDC = 1 kΩ.
Graphically Determine: (1) ICQ and VCEQ (2) ic and vce (3) hFE at the Q point
Page 9 of 12
Question 5 (25 marks) a‐ (15 marks) Drive the expression for Av, rin , rin stage , ro and ro stage for
(1) Common emitter amplifier
(2) Common collector amplifier
1‐ Common emitter:
Finding the input resistance
∥ ∥
Finding the voltage gain
∥
∥
Finding the output resistance
∞
(The student may also use the T model – It will give the same results)
2
2‐ Common
The stu
collector
udents may a
∥
∥
also add the e
∥
effect of Rs in
∥
∥
∥
∥
≅ 1
n calculation
of ro and ro staage. (It will be
∥
e ok as well)
b
Stage
Stage
b‐ (10 marks
Calculate
(1) Th
(2) Th
e 2
Solvin
1
e 1
Solv
1
s) Based on t
the numeric
he overall vo
he input imp
g using ap
7
4.5
4
5.6
ving using app
.
0
.
he derivation
al values for:
oltage gain
edance of th
proximatio
25 2.
6.2
7.58 V
7.58 0.7
1.5
8 mA
26 mV
4.58 mA
668
proximation
25 5
56
.
12.5 0.7
12
26 mV
0.983 mA
ns in part (a),
:
is multistage
DC A
on
.7
2.7
7
6
56
7
, For the mult
e amplifier.
Analysis
ti stage amplifier circuit sh
hown in fig (6
6),
Page 12 of 12
AC Analysis
Second Stage
680
5.668 Ω120 or 119.9
Stage 2 ∥ ∥
Stage 2 6.2 ∥ 2.7 ∥ 0.566
Stage 2
First Stage
Stage 2 453 Ω
∥
∥
12000 ∥ 453
26.4 12000 ∥ 453
436.52
26.4 436.52
.
Total gain
≅ .
Input Impedance
Tr 1 ∥
Tr 1 100 26.44 12000 ∥ 453
Tr 1 46.296 K
Stage 1 ∥ ∥ Tr 1
Stage 1 56 ∥ 56 ∥ 46.296
Stage 1 15.366 K