8/9/2019 Semiconductor Test
1/30
IEE 572
Project Report
Electronic Copy
Submitted by :
Brian Benard
Navin Jeyacandran
!ari Ja"annatan Bala#ubramanian
8/9/2019 Semiconductor Test
2/30
Reco"nition and #tatement o$ te Problem:
The system under consideration is shown above. In a semiconductor-manufacturing
environment, wafers have to be tested with the intention of getting repeated
measurements as a baseline of system performance, accuracy, and measurement
variability.
A series of device test structures is available for testing circuits built on wafers using 0.8-
micron technology. There are 3 sites measured on each wafer as shown in the figure, with
the sites in the lower left, right, lower right, center, and top sections of the wafer, with the
reference as the flat section of the wafer at the bottom. At each site specific electrical
parameters are measured and recorded. The recorded data is automatically uploaded to a
central factory server for storage after the whole wafer is tested. The normal routine is,
after a wafer is robotically loaded onto a vacuum chuc, for the operator to locate the
probe needles e!actly over the first set of test structures on the first site probed. At each
8/9/2019 Semiconductor Test
3/30
site, "# sets of test structures are available. A program automatically moves the wafers
se$uentially through each of these sets, at which a pre-programmed number of electrical
tests are done and results, are measured. Then, the program automatically moves the
wafer to the second site, with no operator intervention, and the measurements are taen
on the same set of test structures. This repeats until the last site is tested, after which the
wafer is robotically removed and another wafer can be robotically loaded.
Two testers are available for this purpose. An operator is also present to conduct the tests.
%lectrical parameters measured give information about the design performance,
robustness, fabrication accuracyand variability. A set of response variables, which are
called &eithley electrical parameters, is chosen that best reflect the above-enumerated
issues 'in Italics(. )or deciding the response variables 'as there are many to choose from(
people from the design department, $uality assurance and the manufacturing department
are consulted.
The problem is to understand whether te#ter#, the operator#, and %a$er# produce
variability in results. *uccinctly stated, we need to find finite source of variation in
Keithley electrical parameters. +nce the e!periment is conducted and analyed, an e!act
test procedure can be suggested.
Coice o$ $actor#& level#& and ran"e#:
. 'e#ter# ( urrently there are two &eithley *ystems used for testing / this factor,
therefore, has two fi!ed levels and is a categorical factor. The variation would be due
to differences in calibration of current sources, voltmeters, and resistor networs to
traceable standards and noise factors such as 1probe-up capacitance1. )or e!ample,
the programmed value for this is treated as a system constant, at a value of 0.3# p)
'pico)arads(, but could affect parameters that rely on a measurement of capacitance,
such as film thicness 'one of the responses chosen(. Another effect due to tester, or
perhaps operator, is the incidence of 1bad 1 data points meaning points where the
probe needles did not mae low-resistance contact with the test structures. Three of the
8/9/2019 Semiconductor Test
4/30
responses 'in varying degrees with the leaage parameter being the most sensitive(
could be potentially affected due to this source of variation. The number of these bad
data points may be added as a response variable as these points are typically passed to
the database as an obvious outlier value e.g. 2%2 value for data that normally falls
between 0 and 2 olts.
2. )perator# ( The intention is to perform the e!periment using two different operators
and see whether variability in the results can be caused if different operators perform
the test. This is a fi!ed factor due to small sample of trained operators for the testers.
3. *a$er#- 4afers of the same type and the same technology are used for testing. These
wafers can be used as blocs while the other factors are tested randomly within this
bloc. The original design was intending to select a set of wafers '5golden6 wafers( as
a fi!ed factor to be used in all the e!perimental cells, and run a typical gauge study. At
the time of this report, due to production constraints out of the control of the
e!perimenters, only half of the originally planned e!periment had been run, and the
data was unavailable. Instead, randomly selected wafers were used to generate the
e!perimental data. The wafers were of the same device type and technology, run at the
same time period through the factory, and were from the same batch of starting
material. Therefore we assume they are from the same normally distributed
population of samples, even though selected from different fabrication lots.
7. +ocation o$ te#t ( 3 points on the wafer are tested. The observations obtained at these
points are duplicates and the mean of the observations is taen as the response
variable. This factor could have been used as a nested factor within wafer 'the data is
automatically provided in this manner(, but was not. andomiing testing at all three
locations is a tedious tas posing a practical difficulty. The dispersion of the data
'variance of the wafer average response( can be analyed.
8/9/2019 Semiconductor Test
5/30
#. The variation due to a different probe card on the same tester was considered. This
might have variation independent of the tester itself, and could be confounded with a
tester effect. 9owever, it was difficult to add as a factor for both testers, unless done
as a before:after change. The difficulty arises in the e!ecution of the e!periment,
where e!cessive setup time would be needed in a random order that varies the probe
card. Therefore this factor was notincluded.
Re#pon#e ,ariable#;
These responses were chosen as a cross-section of the different types of measurements
done in normal production testing, and of the different measurement sub-systems in the
tester The following is a list of responses that are most significant;
. *heet esistance of . It is sub?ect to all of the temperature variations in the
process.
2. *heet esistance of first layer of metal or width 3@, ohms ; The typical variation as a
percentage of the mean is 2>3. eaage urrent of capacitor with electrodes composed of the first and second metal
layers, amperes ; The typical variation as a percentage of the mean is 0 to 20>. The
leaage current can be sensitive to needle contact, therefore to system or operator.
The actual measurement is in the nA 'nanoampere( range, so coding or transformation
of the response may be appropriate.
7. Threshold voltage of large 4: n-channel transistor, volts ; The typical variation as a
percentage of the mean is to 2>.
#. +!ide thicness of dielectric between first and second metal layers, Angstroms; The
typical variation as a percentage of the mean is 3>. This response could be sensitive
to the 1probe-up capacitance6. It is a well-controlled process in the factory.
8/9/2019 Semiconductor Test
6/30
Coice o$ -e#i"n;
There were practical difficulties associated with this e!periment, and the choice of design
was dictated more by the practical issues than anything else. If wafer were considered as
a factor, it would imply randomiing wafer order during the time e!periment was run,
leading to e!cessive handling that was deemed too risy to successful completion of the
e!periment. This, in terms of the e!periment, would have meant re-running all
combinations again, and also financial losses. 9ence, the wafer was to be considered as a
bloc and the treatment combinations were supposed to be run in a randomied fashion
on a wafer.
Another possible factor that was considered was the site-location / i.e. the point where
the wafer is tested. onsidering it as a factor would have meant randomiing the order of
points at which the wafer is tested. This implied changing the stepper program and having
different run orders for different wafers. *uch a modification, though possible, was hardly
feasible practically. A natural simplification would be considering only three points, and
maing the tas of randomiing easier. This aspect of the e!periment was considered but
after considering the set-up of the e!periment, it was decided that the observations were
actually duplicate observations. 9ence the mean of the observations at these points was to
be considered as the response. The analysis of the variability of the locations, or the
variance of the response by wafer 'dispersion effects( could be gained from this data.
The design suggested therefore seems tentative. %ach wafer was to be a bloc and
combinations of tester and operator are tested on each wafer. This meant four
combinations on each wafer, and the value of a particular response variable is the mean of
the observations at the three different sites.
Hence, the experiment under consideration for this project was a general factorial
design, with two factors - operator and tester at two levels. Blocing was to be done by
the third factor wafer, and there were supposed to be five blocs.
Number o$ Replicate#:
8/9/2019 Semiconductor Test
7/30
The number of replicates was decided using a trial an error method on Besign %!pert.
There are fifteen replicates, which means there are three replicates per bloc. This gave
us a power of C".D> with at a significance level of #>.
Run )rder:
Std Run Block Tester Operator Std Run Block Tester Opera
47 1 wafer 1 t2 s2 52 31 wafer 3 t2 s2
48 2 wafer 1 t2 s2 7 32 wafer 3 t1 s1
16 3 wafer 1 t2 s1 54 33 wafer 3 t2 s2
18 4 wafer 1 t2 s1 37 34 wafer 3 t1 s2
46 5 wafer 1 t2 s2 9 35 wafer 3 t1 s1
33 6 wafer 1 t1 s2 8 36 wafer 3 t1 s1
31 7 wafer 1 t1 s2 57 37 wafer 4 t2 s2
1 8 wafer 1 t1 s1 40 38 wafer 4 t1 s2
2 9 wafer 1 t1 s1 42 39 wafer 4 t1 s2
32 10 wafer 1 t1 s2 27 40 wafer 4 t2 s1
3 11 wafer 1 t1 s1 55 41 wafer 4 t2 s2
17 12 wafer 1 t2 s1 11 42 wafer 4 t1 s1
50 13 wafer 2 t2 s2 10 43 wafer 4 t1 s1
34 14 wafer 2 t1 s2 25 44 wafer 4 t2 s1
19 15 wafer 2 t2 s1 41 45 wafer 4 t1 s2
49 16 wafer 2 t2 s2 12 46 wafer 4 t1 s1
4 17 wafer 2 t1 s1 56 47 wafer 4 t2 s2
35 18 wafer 2 t1 s2 26 48 wafer 4 t2 s1
6 19 wafer 2 t1 s1 15 49 wafer 5 t1 s1
21 20 wafer 2 t2 s1 43 50 wafer 5 t1 s2
51 21 wafer 2 t2 s2 45 51 wafer 5 t1 s2
5 22 wafer 2 t1 s1 30 52 wafer 5 t2 s1
20 23 wafer 2 t2 s1 14 53 wafer 5 t1 s1
36 24 wafer 2 t1 s2 59 54 wafer 5 t2 s2
53 25 wafer 3 t2 s2 28 55 wafer 5 t2 s1
23 26 wafer 3 t2 s1 60 56 wafer 5 t2 s2
22 27 wafer 3 t2 s1 29 57 wafer 5 t2 s1
39 28 wafer 3 t1 s2 58 58 wafer 5 t2 s2
38 29 wafer 3 t1 s2 44 59 wafer 5 t1 s2
24 30 wafer 3 t2 s1 13 60 wafer 5 t1 s1
Per$ormin" te e.periment:
8/9/2019 Semiconductor Test
8/30
The design that was suggested in previous pro?ect proposals was eeping wafers,
operators and testers as fi!ed factors. 9owever, the e!periment was run in a different
manner. This was because of various factors that affect e!periments in industrial settings
lie availability of time and resources, and understanding of the personnel in-charge of
the e!periment. onse$uently, the e!perimental design had to be changed in accordance
with the way the e!periment was run. 4afers were made a random factor nested within
operators. The responses considered were the same. The ob?ective was still to find the
source of variation in the electrical parameters measured. 9owever, the e!periment would
now also tell us if any variability e!isted in the wafer population.
The revised design is shown below;
+perator +perator 24 42 43 47 4# 4" 4D 48 4 42 43 47 4# 4" 4D 48
Tester
Tester 2
!ight wafer levels representing the wafer population nested within operators were tested
with the two tester levels/ "ne replication was done with these eight levels. This
e!perimental design does not e!actly conform to the design initially considered and
planned, but it might still be a reasonable model to use in maing conclusions. The
wafers were selected randomly from the population for each cell of this revised design.
9owever, the conclusions cannot be taen for granted. )ollow up e!periments need to
be conducted to ensure that the results are the same as those predicted by this e!periment
e.g. the originally designed gauge study.
Stati#tical 0naly#i# o$ -ata:
The following represents
8/9/2019 Semiconductor Test
9/30
n - *heet esistance of
8/9/2019 Semiconductor Test
10/30
8/9/2019 Semiconductor Test
11/30
eaage urrent of capacitor with electrodes composed of the first and second
metal layers, amperes
Results for: Worksheet 2
ANOVA: leakage versus tester, operator, wafereaage urrent of capacitor with electrodes composed of the first and second
metal layers, amperes
Factor Type Levels Values
wafer(operator) random 8 1 2 3 4 5 6
8
tester f!"ed 2 1 2
operator f!"ed 2 1 2
#nalys!s of Var!ance for lea
$ource %F $$ &$ F '
wafer(operator) 14 181 13 316
tester*operator 1 141536 141536 238
tester 1 1446+4 1446+4 2442
operator 1 +1+ +
,rror 14 831 5+3
Total 31 31238+
$ource Var!ance ,rror ,"pected &ean $-uare for ,ac. Term
component term (us!n/ restr!cted model)
1 wafer(operator) 8+ 5 (5) 2(1)
2 tester*operator 5 (5) 82
3 tester 5 (5) 163
4 operator 1 (5) 2(1) 164
5 ,rror 5+3 (5)
A lo" tran#$ormationwas done on the original readings to mae the data conform to the
assumptions. The A
8/9/2019 Semiconductor Test
12/30
Results for: Worksheet 2
ANOVA: 2sn versus tester, operator, wafer
Factor Type Levels Values
wafer(operator) random 8 1 2 3 4 5 6
8
tester f!"ed 2 1 2
operator f!"ed 2 1 2
#nalys!s of Var!ance for m2sn
$ource %F $$ &$ F '
wafer(operator) 14 51456 365 235 6
tester 1 21 21 13 25
operator 1 1484 1484 3832
tester*operator 1 3285 3285 211
,rror 14 2186 1561Total 31 24162
$ource Var!ance ,rror ,"pected &ean $-uare for ,ac. Term
component term (us!n/ restr!cted model)
1 wafer(operator) 15 5 (5) 2(1)
2 tester 5 (5) 162
3 operator 1 (5) 2(1) 163
4 tester*operator 5 (5) 84
5 ,rror 1561 (5)
The A
8/9/2019 Semiconductor Test
13/30
Re#po#n#e 5 teo#: +!ide thicness of dielectric between first and second metal
layers, Angstroms
Results for: Worksheet 2
ANOVA: teos versus tester, operator, wafer
Factor Type Levels Values
wafer(operator) random 8 1 2 3 4 5 6
8
tester f!"ed 2 1 2
operator f!"ed 2 1 2
#nalys!s of Var!ance for teos
$ource %F $$ &$ F '
wafer(operator) 14 5224 332 84 63tester 1 32 32 +3
operator 1 5645 5645 22
tester*operator 1 1562 1562 331
,rror 14 62564 446+
Total 31 16+6848
$ource Var!ance ,rror ,"pected &ean $-uare for ,ac. Term
component term (us!n/ restr!cted model)
1 wafer(operator) 03685 5 (5) 2(1)
2 tester 5 (5) 162
3 operator 1 (5) 2(1) 163
4 tester*operator 5 (5) 84
5 ,rror 4468+ (5)
The operator and testFoperator interaction are shown as significant.
8/9/2019 Semiconductor Test
14/30
The
8/9/2019 Semiconductor Test
15/30
Appendi!
Re#idual "rap# $or Rn Seet Re#i#tance o$ N6 active area& om##8uare9
30252015105
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
Observation Order
Residual
Residuals Versus te Order of te !ata
"res#onse is rn$
4.03.93.83.73.6
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
%itted Value
Residual
Residuals Versus te %itted Values
"res#onse is rn$
8/9/2019 Semiconductor Test
16/30
0.150.100.050.00-0.05-0.10-0.15
2
1
0
-1
-2
&or'al()ore
Residual
&or'al *robabilit+ *lot of te Residuals
"res#onse is rn$
2.01.51.0
4.1
4.0
3.9
3.8
3.7
3.6
o#erator
rn
8/9/2019 Semiconductor Test
17/30
2.01.51.0
4.1
4.0
3.9
3.8
3.7
3.6
tester
rn
87654321
4.1
4.0
3.9
3.8
3.7
3.6
wafer
rn
8/9/2019 Semiconductor Test
18/30
Re#idual "rap# $or ,tn 're#old volta"e o$ lar"e *+ n(cannel tran#i#tor& volt# 9
30252015105
0.003
0.002
0.001
0.000
-0.001
-0.002
-0.003
Observation Order
Residual
Residuals Versus te Order of te !ata
"res#onse is vtn$
0.910.900.890.880.870.86
0.003
0.002
0.001
0.000
-0.001
-0.002
-0.003
%itted Value
Residual
Residuals Versus te %itted Values
"res#onse is vtn$
8/9/2019 Semiconductor Test
19/30
0.0030.0020.0010.000-0.001-0.002-0.003
2
1
0
-1
-2
&or'al()ore
Residual
&or'al *robabilit+ *lot of te Residuals
"res#onse is vtn$
2.01.51.0
0.91
0.90
0.89
0.88
0.87
0.86
0.85
o#erator
vtn
8/9/2019 Semiconductor Test
20/30
2.01.51.0
0.91
0.90
0.89
0.88
0.87
0.86
0.85
tester
vtn
87654321
0.91
0.90
0.89
0.88
0.87
0.86
0.85
wafer
vtn
8/9/2019 Semiconductor Test
21/30
Re#idual "rap# $or +ea3a"e +ea3a"e Current o$ capacitor %it electrode#
compo#ed o$ te $ir#t and #econd metal layer#& ampere#9
30252015105
0.1
0.0
-0.1
Observation Order
Residual
Residuals Versus te Order of te !ata
"res#onse is lea,$
-8.5-8.6-8.7-8.8-8.9-9.0-9.1-9.2-9.3-9.4-9.5
0.1
0.0
-0.1
%itted Value
Residual
Residuals Versus te %itted Values
"res#onse is lea,$
8/9/2019 Semiconductor Test
22/30
0.10.0-0.1
2
1
0
-1
-2
&or'al()ore
Residual
&or'al *robabilit+ *lot of te Residuals
"res#onse is lea,$
2.01.51.0
-8.5
-8.6
-8.7-8.8
-8.9
-9.0
-9.1
-9.2
-9.3
-9.4
-9.5
o#erator
lea,
8/9/2019 Semiconductor Test
23/30
2.01.51.0
-8.5
-8.6
-8.7
-8.8
-8.9
-9.0
-9.1
-9.2
-9.3
-9.4
-9.5
tester
lea,
87654321
-8.5
-8.6
-8.7
-8.8
-8.9
-9.0
-9.1
-9.2
-9.3
-9.4
-9.5
wafer
lea,
8/9/2019 Semiconductor Test
24/30
Re#idual rap# $or ;2Sna3 Seet Re#i#tance o$ $ir#t layer o$ metal or %idt
8/9/2019 Semiconductor Test
25/30
210-1-2
2
1
0
-1
-2
&or'al()ore
Residual
&or'al *robabilit+ *lot of te Residuals
"res#onse is '2sn$
2.01.51.0
136
131
126
o#erator
'2sn
8/9/2019 Semiconductor Test
26/30
2.01.51.0
136
131
126
tester
'2sn
87654321
136
131
126
wafer
'2sn
8/9/2019 Semiconductor Test
27/30
Re#idual rap# $or 'eo# ).ide tic3ne## o$ dielectric bet%een $ir#t and #econd metal
layer#& 0n"#trom#9
5 10 15 20 25 30
-30
-20
-10
0
10
20
30
Observation Order
Residual
Residuals Versus te Order of te !ata
"res#onse is teos$
10100 10200 10300
-30
-20
-10
0
10
20
30
%itted Value
Residual
Residuals Versus te %itted Values
"res#onse is teos$
8/9/2019 Semiconductor Test
28/30
-30 -20 -10 0 10 20 30
-2
-1
0
1
2
&or'al()ore
Residual
&or'al *robabilit+ *lot of te Residuals
"res#onse is teos$
2.01.51.0
10350
10250
10150
o#erator
teos
8/9/2019 Semiconductor Test
29/30
2.01.51.0
10350
10250
10150
tester
teos
87654321
10350
10250
10150
wafer
teos
8/9/2019 Semiconductor Test
30/30