1
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY (A Constituent College of Sri Siddhartha Academy of Higher Education)
Master of Technology in VLSI & EMBEDDED SYSTEMS
2020-21
I Semester
Subject
Code
Subject
L – T – P – C Marks for
CIE SEE Total
VES101 Physics of VLSI devices
and Technology 4 - 0 - 0 - 4 50 100 150
VES102
CMOS VLSI Design 4 - 0 - 0 - 4 50 100 150
VES103
Advanced Embedded
Systems
4 - 0 - 0 - 4
50
100
150
VES104 SoC Design 4 - 0 - 0 - 4 50 100 150
VES15Y Elective-I 4 - 0 - 0 - 4 50 100 150
VES106 Technical Seminar -I 0 - 0 - 0 - 2 50 -- 50
VES107 Embedded Systems Lab
0 - 0 - 3 - 1 50 -- 50
Total Credits 20 -0 – 3 - 23 350 500 850
Elective -I
VES151 Advanced Computer Architectures
VES152 VLSI Digital Signal Processing System
VES153 CAD forVLSI
*Y stands for numerals 1,2,3..
2
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY (A Constituent College of Sri Siddhartha Academy of Higher Education)
Master of Technology in VLSI & EMBEDDED SYSTEMS
2020-21
II Semester
Subject
Code
Subject
L – T – P – C
Marks for
CIE SEE Total
VES201 Analog CMOS VLSI
Design 4 - 0 - 0 - 4 50 100 150
VES202 Low Power VLSI
Design 4 - 0 - 0 - 4 50 100 150
VES203 Advances in VLSI
Design 4 - 0 - 0 - 4 50 100 150
VES204 Real Time Embedded
System 4 - 0 - 0 - 4 50 100 150
VES25Y Elective-II 4 - 0 - 0 - 4 50 100 150
VES206 Technical Seminar -II 0 - 0 - 0 - 2 50 -- 50
VES207 VLSI Lab 0 - 0 - 3 - 1 50 -- 50
Total Credits 20 -0 – 3 - 23 350 500 850
Elective-II
VES251 Digital System Design using Verilog.
VES252 Solar Cells and Thin Film Technologies.
VES253 RF VLSI Design
*Y stands for numerals 1,2,3..
3
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY (A Constituent College of Sri Siddhartha Academy of Higher Education)
Master of Technology in VLSI & EMBEDDED SYSTEMS
2020-21
III Semester
Subject
Code
Subject
L – T – P – C
Marks for
CIE SEE Total
VES301 Internship 0 - 0 - 0 - 10 100 --- 100
VES302 Project Work Phase-I 0 - 0 - 0 - 9 50 -- 50
Total Credits 0 -0 – 0 - 19 150 --- 150
Note:
VES301: Internship: Report evaluation on Internship (50 Marks)
Viva – Voce and Evaluation of Internship (50 Marks)
VES302: Project Work Phase-I: Literature Survey to finalize the topic of the
project and presentation of the same (50 Marks)
4
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY (A Constituent College of Sri Siddhartha Academy of Higher Education)
Master of Technology in VLSI & EMBEDDED SYSTEMS
2020-21
IV Semester
Subject
Code
Subject
L – T – P –
C
Marks for
CIE SEE Total
VES41Y Elective-III 4 - 0 - 0 - 4 50 100 150
VES42Y
Elective –IV 4 - 0 - 0 - 4 50 100 150
VES403 Project Work Phase-II 0 - 0 - 0 - 15 100 200 300
Total Credits 8 -0 – 0 – 23 200 400 600
Elective-III Elective–IV
VES411 ReliabilityEngineering VES421 Internet ofThings.
VES412 High SpeedVLSIDesign VES422 CMOS Mixed Signal Circuit Design
VES413 VLSI Testingandverification VES423 SystemVerilog
*Y stands for numerals 1,2,3..
Note:
Project WorkPhase-II:
1. Project work Seminar – I: Presentation of the project work carried outfor
the first six weeks (50Marks)
2. Project work Seminar – II: Presentation of the project work carried out for
the next eight weeks (50Marks)
3. Project work evaluation taken up at the end of the IVsemester.
Report Evaluation: Average of the marks evaluated by internaland external examiners (125Marks)
Viva- Voce: Conducted and evaluated jointly by internal and external
examiners (75Marks)
Total Credits (I to IV Semester)
88
Total Marks (I to IV Semester)
2450
5
Program Objectives:
P01 An ability to independently carry out research /investigation and development
work to solve practicalproblems.
PO2 An ability to write and present a substantial technical report/document.
PO3 Students should be able to demonstrate a degree of mastery over the area as per the
specialization of the program. The mastery should be at a level higher than the
requirements in the appropriate bachelor program.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded Systems
Syllabus for the Academic Year –2020 - 2021
Semester: I
Subject Name: Physics of VLSI devices and Technology
SubjectCode:VES101 L – T – P – C:4-0-0-4
Course Objectives:
Sl.No
Course Objectives
1
To understand the impact of the physical and chemical processes of integrated circuit
fabrication technology on the design of integrated circuits.
2
To understand physics of the Crystal growth, wafer fabrication and basic properties of
silicon wafers.
3 To learn the various lithography techniques and concepts of wafer exposure system.
4 To understand Concepts of thermal oxidation and Si/SiO2 interface.
5
To learn concepts of dopant solid solubility, diffusion macroscopic point, different
solutions to diffusion equation. Design and evaluation of diffused layers andits
measurement methods.
6
To learn concepts of ion implantation, role of the crystals structures, high-energy implants,
ultralow energy implants and ion beam heating methods.
Course Outcomes:
Course
outcome
Descriptions
CO1 Appreciate the various techniques involved in the VLSI fabrication process. (L3)
CO2 Understand the different lithography methods and etching process.(L2)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
CO3 Study the Epitaxy, Oxidation, depositions and diffusion mechanisms.(L1)
CO4
Understand the nuances of assembly and packaging of VLSI devices.(L2)
UNIT Description Hours
I
CRYSTAL GROWTH, WAFER PREPARATION, EPITAXY AND OXIDATION:
Electronic Grade Silicon, Czochralski crystal growing, Silicon Shaping,
processing consideration, Vapour Phase Epitaxy, Molecular Beam Epitaxy,
Silicon on Insulators, Epitaxial Evaluation, Growth Mechanism and kinetics,
Thin Oxides, Oxidation Techniques and Systems, Oxide properties,
Redistribution of Dopant at interface, Oxidation of Poly Silicon, Oxidation
inductedDefects.
12
II
LITHOGRAPHY AND RELATIVE PLASMA ETCHING:
Optical Lithography, Electron Lithography, X-Ray Lithography, Ion
Lithography, Plasma properties, Feature Size control and Anisotropic Etch
mechanism, relative Plasma Etchingtechniques.
10
III
DEPOSITION, DIFFUSION, ION IMPLEMENTATION AND METALLIZATION:
Deposition process, Polysilicon, plasma assisted Deposition, Models of Diffusion
in Solids, Flick’s one Dimensional Diffusion Equation – Atomic Diffusion
Mechanism – Measurement techniques – Range Theory- Implant equipment.
Annealing Shallow junction – High energy implantation – Physical vapors
Deposition – Patterning.
10
IV
PROCESS SIMULATION AND VLSI PROCESS INTEGRATION:
Ion implantation – Diffusion and oxidation – Epitaxy – Lithography – Etching
and Deposition- NMOS IC Technology – CMOS IC Technology – MOS
Memory IC technology - Bipolar IC Technology – ICFabrication.
10
V
ANALYTICAL, ASSEMBLY TECHNIQUES AND PACKAGING OF VLSI
DEVICES:
Analytical Beams – Beams Specimen interactions - Chemical methods – Package
types – banking design consideration – VLSI assembly technology – Package
fabrication technology.
10
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Text Books:
Sl
No
Text Book title
Author
Volume and Year of
Edition
1 VLSI Technology S.M.Sze
McGraw Hill, 2nd
Edition. 2008.
2 ULSI Technology C.Y. Chang &
S.M.Sze
McGraw Hill,1996.
3 VLSI Fabrication Principles S.K. Gandhi John Wiley Inc.,
New York, 1994(2nd
Edition)
4 Silicon VLSI Technology: fundamentals
practice and Modeling
James D Plummer,
Michael D. Deal,
Peter B.Griffin
Prentice Hall India,
2009.
Reference Books:
Sl
No
Text Book title
Author Volume and Year
of Edition
1 Fundamentals of Modern VLSI Devices Yuan Taur, Tak. H.
Ning
Cambridge
University Press,
2003.
2 The Science and Engineering of
Microelectronic Fabrication
Stephena, Campbell 2nd edition, oxford
university press,
2005.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: I
Subject Name: CMOS VLSI Design
SubjectCode: VES102 L – T – P –C:4-0-0-4
Course Objectives:
Sl.No
Course Objectives
1
To make the students learn the principles, operations and applications of
MOSFET’s.
2
To introduce the students to modelling and design of digital VLSI circuits
using different CMOS design styles and CMOS sub system.
3
To make the students learn stick diagrams and layouts using Lambda based
design rules for a given schematic and to categorize the different MOS
Technologies
Course Outcomes:
Course
outcome
Descriptions
CO1
Identify the different design techniques used in modeling the digital VLSI
Circuits. (L1)
CO2
Calculate the design parameters for the CMOS circuits and can estimate
the parasitic values for different mask layers. (L2)
CO3 Outline the MOS process technology and CMOS sub system design. (L4)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Unit 1:MOS Transistor Theory:
n MOS / p MOS transistor, threshold voltage equation, body effect, MOS
device design equation, sub threshold region, Channel length modulation.
mobility variation, Tunneling, punch through, hot electron effect MOS
models,smallsignalACCharacteristics,CMOSinverter,βn/βpratio,noise
margin, static load MOS inverters, differential inverter, transmission gate,
tristate inverter, BiCMOS inverter. (Text1)
12
II
Unit 2:CMOS Process Technology Silicon Semiconductor technology: An
overview, basic CMOS technology. A basic n-well CMOS process, The p-well
process, twin tub process, silicon on insulator. (Text1)
CMOS process enhancements: Interconnect, circuit elements; Resistors,
Capacitors, bipolar transistors, Thin film transistors,3DCMOS (Text1)
MOS Design Processes: MOS layers, stick diagrams, design rules and layout,
symbolic diagrams. (Text3)
10
III
Unit 3: Basic circuit concepts: Sheet resistance, standard unit of capacitance
concepts, delay unit time inverter delays, driving capacitive loads, propagation
delays, scaling of MOS circuits (Text3)
Basics of Digital CMOS Design: Combinational MOS Logic circuits- Introduction, MOS logic circuits with depletion NMOS load. (Text2)
10
IV
Unit 4:Basics of Digital CMOS Design: Contd..CMOS logic circuits,
complex logic circuits, CMOS Transmission Gate. (Text2)
Sequential MOS logic Circuits :Introduction, Behavior of bi stable elements,
SR latch Circuit, (Text2).
10
V
Unit 5:Sequential MOS logic Circuits :Contd..
Clocked latch and Flip Flop Circuits, CMOS D- latch and triggered Flip Flop (Text2).
Dynamic CMOS and clocking: Introduction, advantages of CMOS over
NMOS, CMOS\SOS technology’ CMOS\bulk technology, latch up in bulk
CMOS, static CMOS design, Domino CMOS structure and design, Charge
sharing, Clocking- clock generation, clock distribution, clocked storage
elements. (Text4)
10
Text Books:
Sl
No
Title
Authors
Volume and Year of
Edition
1 Principles of CMOS VLSI
Design: A System Perspective
Neil Weste and K.
Eshragian,
2nd edition, Pearson
Education (Asia) Pte. Ltd., 2000.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
2
CMOS Digital Integrated
Circuits: Analysis and Design
Sung Mo Kang
&YosufLederabic Law,
3 rd edition, Tata
McGraw-Hill Publishing
Company Ltd., New
Delhi, 2007.
3 Basic VLSI Design Douglas A. Pucknell&
Kamran Eshraghian
PHI 3rd Edition (original
edition 1994), 2005.
4 Introduction to VLSI Design Eugene D Fabricius Mc Graw Hill,
International Edition (Original Edition 1990).
Reference Books:
Sl
No
Title
Authors
Volume and Year of
Edition
1 CMOS VLSI Design: A Circuits
and System perspective,
Neil H E Weste, David
Haris,Ayan,
3 rd edition, Pearson
Education (Asia) Pvt.
Ltd., 2000.
2 Introduction to VLSI circuits and
systems
John P Uyemura Wiley Indian
Edition,2002
3 Modern VLSI design: System on
Silicon
Wayne, Wolf, Pearson Education,
Second Edition.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: I
Subject Name: Advanced Embedded Systems
Subject Code:VES103 L – T – P – C:4-0-0-4
Course Objectives :
Sl.No
Course Objectives
1
Understand the basics of designing embedded hardware and
software systems.
2 Outline various development tools.
3
Describe the hardware software co-design and firmware design
approaches
4
RTOS design in embedded system.
Course Outcomes :
Course
outcome
Descriptions
CO1 Understand the general structure of an Embedded System. (L2)
CO2
Apply various real time algorithms in building embedded
systems.(L3)
CO3 Identify IDE and new trends in embedded industry.(L1)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Typical Embedded System: Core of the Embedded System, Memory,
Sensors and Actuators, Communication Interface, Embedded Firmware, Other
System Components. Characteristics and Quality Attributes of Embedded
Systems
10
II
Hardware Software Co-Design and Program Modelling: Fundamental
Issues in Hardware Software Co-Design, Computational Models in Embedded
Design, Introduction to Unified Modelling Language, Hardware Software
Trade-offs.
10
III
Embedded Firmware Design and Development: Embedded Firmware
Design Approaches, Embedded Firmware Development Languages.
8
IV
Real-Time Operating System (RTOS) based Embedded System Design:
Operating System Basics, Types of OS, Tasks, Process and Threads,
Multiprocessing and Multitasking, Task Scheduling, Threads, Processes and
Scheduling: Putting them altogether, Task Communication, Task
Synchronization, Device Drivers, How to Choose an RTOS.
12
V
The Embedded System Development Environment: The Integrated
Development Environment (IDE), Types of Files Generated on Cross-
compilation, Disassembler / Decompiler, Simulators, Emulators and
Debugging, Target Hardware Debugging, Boundary Scan. Trends in the
Embedded Industry, Processor Trends in Embedded System, Embedded OS
Trends, Development Language Trends, Open Standards, Frameworks and Alliances, Bottlenecks.
12
Text Book:
Sl
No
Text Book title
Author
Volume and Year of
Edition
1 Introduction to Embedded Systems Shibu K V Tata McGraw Hill
Education Private
Limited,2009
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
2
Embedded Systems: Architecture,
Programming and Design
Rajkamal
Tata McGraw Hill,
New Delhi.
Reference Book:
Sl
No
Text Book title
Author
Volume and Year
of Edition
1 Embedded Systems – A contemporary
Design Tool
James K
Peckol, John Weily
2008.
2 Embedded Real Time Systems:
Concepts Design and Programming Dr. K.V.K K Prasad, Dreamtech Press
New Delhi.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: I
Subject Name: SoC Design
Subject Code:VES104 L – T – P – C:4-0-0-4
Course Objectives :
Sl. No
Course Objectives
1
Understand the various benefits involved in SoC design and typical
design goals related to SoC design.
2
Apply the concepts of embedded memories with interconnect
architectures for SoC design.
3
Understand the concepts related to SoC design flow, co-design
and various power management issues.
Course Outcomes:
Course
outcome
Descriptions
CO1
Interpret the different challenges involved in design of SoC and
compare different design configurations such as System-on-Board
and System-in-Package.(L2).
CO2
Explain various embedded processors, memory architectures and
hardware accelerators related to SoC design.(L2).
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
CO3
Analyse the performance of various NoC architectures and mixed
signal RF components with reference to different design parameters.
(L4).
CO4
Explain the design concepts of SoC design with reference to
hardware software co-design and packaging related problems.(L2).
UNIT Description Hours
I
Unit 1:Motivation for SoC Design
Review of Moore’s law and CMOS scaling, benefits of System-on-Chip
integration in terms of cost, power, and performance, comparison of System-
on-Board, System-on-Chip and System-in-Package, typical goals in SoC
design – cost reduction, power reduction, design effort reduction, performance
maximization, productivity gap issues and the ways to improve the gap – IP
based design and design reuse.
Case study: Any typical System-in-Package.
7
II
Unit 2:Embedded Processors
Microprocessors, Microcontrollers, DSP and their selection criteria, review of
RISC and CISC instruction sets, Von-Neumann and Harward architectures and
interrupt architectures.
Case study: Interrupt controller architecture for multiprocessors based on
FPGA.
7
III
Unit 3: Embedded Memories
Scratchpad memories, Cache memories, Flash memories, Embedded DRAM,
topics related to cache memories, Cache coherence, MESI protocol.
8
IV
Unit 4:Hardware Accelerators in an SOC
Comparison on hardware accelerators and General-purpose CPU, accelerators
for graphics and image processing, typical peripherals in an SoC – DMA
controller, USB controller.
7
V
Unit 5: Interconnect architectures for SoC
Bus architecture and its limitations, Network on Chip (NoC) topologies, packet
switching and circuit switching, routing algorithms, static and dynamic
routing, distributed and source routing, minimal and non-minimal routing,
flow control, quality of service and NoC architectures.
9
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
VI
Unit 6:Mixed Signal and RF components in an SoC
Sensors, Amplifiers, Data Converters, Power management circuits, RF
transmitter and receiver circuits, heterodyne and homodyne receivers, image-
reject receivers, Hartley architecture and Weaver architecture, digital IF
receivers, subsampling receivers, direct conversion and two-step
transmitters.
9
VII
Unit 7:SoC Design Flow
IP design, verification and integration, hardware software co-design, power
management problems and packaging related problems.
5
Text Books:
Sl
No
Text Book title
Authors
Volume and Year of
Edition
1
On-Chip Communication Architectures:
System on Chip Interconnect
Sudeep Pasricha and
Nikil Dutt
Morgan Kaufmann
Publishers © 2008
2
Networks on Chips: Technology and
Tools
Luca Benini and
Giovanni De Micheli
Morgan Kaufmann
Publishers © 2006
3
Embedded Systems: A Contemporary Design Tool
James K. Peckol
Wiley Student Edition, 2007.
Reference Books:
Sl
No
Text Book title
Authors
Volume and Year of
Edition
1 Introduction to system on package sop-
Miniaturization of the entire System
Rao R. Tummala,
MadhavanSwaminathan
McGraw-Hill-2008
2
Transaction Level Modeling with
SystemC: TLM Concepts and Applications for Embedded Systems
Frank Ghenassia
Springer © 2005
3 Surviving the SOC revolution: a guide
to platform-based design
Henry Chang Kluwer (Springer),
1999
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: I
Subject Name: Advanced Computer Architecture
Subject Code:VES151 L – T – P –C:4-0-0-4
Course Objectives:
Sl.No
Course Objectives
1 To make students know about the Parallelism concepts in Programming
2 To give the students an elaborate idea about the different memory systems and buses.
3 To introduce the advanced processor architectures to the students.
4 To make the students know about the importance of multiprocessor and multicomputer.
5
To study about data flow computer architectures
Course Outcomes:
Course
outcome
Descriptions
CO1 Demonstrate concepts of parallelism in hardware/software.(L2)
CO2 Discuss memory organization and mapping techniques.(L1)
CO3 Describe architectural features of advanced processors.(L2)
CO4 Interpret performance of different pipelined processors(L3)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Parallel Computer Models:
The State of Computing, Computer Development Milestones, Elements of
Modern Computers, Evolution of Computer Architecture, System Attributes to
Performance, Multiprocessors and Multicomputer Shared –Memory
Multiprocessors, Distributed Memory Multiprocessors, A Taxonomy of MIMD
Computers, Multi vector and SIMD computers, Vector Supercomputers, SIMD
Supercomputers.
6
II
Parallel Program and network properties:
Conditions for parallelism ,data resource dependencies, Hardware & software
parallelism, The role of compilers, Program partitioning and scheduling, grain
size &latency, Grain packaging and scheduling, Problems on grain packaging,
Program mechanisms, control flow &dataflow, demand driven mechanisms,
Comparison of flow mechanisms, network properties and routing, Static
connection networks, dynamic connection networks.
10
III
Advanced Processors: Advanced Processor technology, Instruction set architecture, CISC scalar
processors, RISC scalar processors, and Superscalar Processors, VLIW
Architectures Vector and Symbolic processors.
8
IV
Scalable multiprocessors:
Scalability,: bandwidth scaling, latency scaling, cost scaling, physical scaling,
realizing programming models, primitive network transactions, shared address
space, message pasiing, common challenges, Physical DMA;
8
V
Pipeling and superscalar techniques: Linear pipeline processors synchronous & asynchronous Processors, Cocking &
timing control, speedup, efficiency, throughput, Reservation &latency analysis,
Collision free scheduling, Instruction execution phases, mechanisms for IP,
Dynamic instruction scheduling, Compiler arithmetic principles, Multifunctional
arithmetic pipeline, static arithmetic pipeline.
12
VI
Memory Hierarchy design:
Review: Introduction; Cache performance; Cache Optimizations. Memory
Hierarchy design: Introduction; Advanced optimizations of Cache performance;
Memory technology and optimizations.
8
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Text Books:
Sl
No
Text Book title
Author
Volume and Year of
Edition
1 Computer Architecture A Quantitative
Approach.
Hennessey and
Patterson
4th Edition,
Elsevier, 2007
2 Advanced Computer Architecture
Parallelism, Scalability,
Programmability.
Kai Hwang Tata McGraw-Hill,
2003.
3 Parallel computer architecture David culler,
J.P.singh,
Anoopgupta,
Margon
Kauffman1999
Reference Books:
Sl
No
Text Book title
Author
Volume and Year of
Edition
1 Computer architecture & organization John P Hayes 1998
2 Parallel computers V Rajaramanna , C
S R Murthy,;
phi 2000
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: I
Subject Name: VLSI Digital Signal Processing System
SubjectCode:VES152 L – T – P – C :4-0-0-4
Course Objectives :
Sl. No
Course Objectives
1
To understand the basics and representation of DSP
algorithms
2 To have an insight of Data flow graphs and pipelining
3
To understand Fast FIR filters and Rank order Filters
4
To have an insight of Look ahead schemes and round off
noise computation
Course Outcomes :
Course
outcome
Descriptions
CO1
To have a knowledge of DSP Basics and algorithms(L1)
CO2 Identify various pipelining and parallel processing techniques(L3)
CO3 Analyze various Fast FIR filters and Rank order Filters(L4)
CO4 Analyze various Look ahead schemes and round off noise computation(L4)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Introduction to Digital Signal Processing : Linear System Theory-
Convolution- Correlation - DFT- FFT- Basic concepts in FIR Filters and IIR
Filters - Filter Realizations. Representation of DSP Algorithms - Block
diagram-SFG-DFG.
12
II
Iteration Bound, Pipelining and Parallel Processing of FIR Filter: Iteration
Bound: Data-Flow Graph Representations- Loop Bound and Iteration Bound-
Algorithms for Computing Iteration Bound-LPM Algorithm. Pipelining and
Parallel Processing: Pipelining of FIR Digital Filters- Parallel Processing-
Pipelining and Parallel Processing for Low Power. Retiming: Definitions,
Properties and problems- Solving Systems of Inequalities.
10
III
Fast Convolution and Arithmetic Strength Reduction in Filters : Fast
Convolution: Cook-Toom Algorithm, Modified Cook-Toom Algorithm.
Design of Fast Convolution Algorithm by Inspection. Parallel FIR filters, Fast
FIR algorithms, Two parallel and three parallel. Parallel architectures for Rank
Order filters, Odd Even Merge sort architecture, Rank Order filterarchitecture,
Parallel Rank Order filters, Running Order Merge Order Sorter, Low power
Rank Order filter.
10
IV
Pipelined and Parallel Recursive Filters: Pipeline Interleaving in Digital
Filters, Pipelining in 1st Order IIR Digital Filters, Pipelining in Higher, Order
IIR Filters, Clustered Look ahead and Stable Clustered Look ahead, Parallel
Processing for IIR Filters and Problems.
10
V
Scaling and Round off Noise: Scaling and Round off Noise, State Variable
Description of Digital Filters, Scaling and Round off Noise Computation,
Round Off Noise Computation Using State Variable Description, Slow-Down
Retiming and Pipelining.
10
Text Books:
Sl
No
Text Book title
Author Volume and Year
of Edition
1 VLSI Digital Signal processing, John-
Wiley K.K Parhi 1999
Reference Book:
Sl
No
Text Book title
Author Volume and Year
of Edition
1
Digital Signal Processing, Prentice
Hall of India
John G.Proakis,
Dimitris
G.Manolakis
1995.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: I
Subject Name: CAD for VLSI
Subject Code:VES153 L – T – P – C:4-0-0-4
Course Objectives:
Sl. No
Course Objectives
1 To make the students learn the different phases of CAD for digital design.
2
To learn the fundamental concepts of CAD and to establish capability for CAD
tool.
3
To identify and develop an appropriate algorithms for different VLSI system
issues.
Course Outcomes:
Course
Outcome
Descriptions
CO1
Identify the phases of CAD for digital electronic systems, from digital logic
simulation to physical design, including testing and verification.(L3)
CO2
Demonstrate the knowledge and understanding of fundamental concepts in
CAD and to establish capability for CAD tool development and
enhancement.(L2)
CO3 Apply the appropriate algorithms and Cad tools for different VLSI problems.(L3)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I Introduction To VLSI Methodologies: VLSI Physical Design Automation -
Design and Fabrication of VLSI Devices - Fabrication process and its impact
on Physical Design.
12
II A Quick Tour Of VLSI Design Automation Tools: Data structures and Basic
Algorithms, Algorithmic Graph theory and computational complexity.
10
III General Purpose Methods For Combinational Optimization: partitioning, floor
planning and pin assignment, placement, routing.
10
IV Simulation-Logic Synthesis: Verification-High level synthesis - Compaction.
Physical Design Automation of FPGAs, MCMS.
10
V Chip Input and Output Circuits: ESD Protection, Input Circuits, Output
Circuits and noise, On-chip clock Generation and Distribution, Latch-up and
its prevention.
10
Text Books:
Sl.
No
Text Book title
Author
Volume and Year of
Edition
1 Algorithms for VLSI Physical Design
Automation
Naveed
Shervani
3rdEdition, 2005, Springer
International Edition.
2 Algorithms for VLSI Design
Automation
S. H. Gerez 1999, Wiley student
Edition, John Wiley and
Sons (Asia) Pvt.Ltd.
Reference Books:
Sl. No
Text Book title
Author
Volume and Year of
Edition
1
VLSI Physical Design Automation-
Theory and Practice
Sadiq M Sait, Habib
Youssef
I.E.E.E.Press, 1995
2
VLSI Physical Design Automation Sung Kyu Lim Springer
International Edition.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded Systems
Syllabus for the Academic Year –2020 - 2021
Semester: I
Subject Name: Embedded Systems Lab
SubjectCode:VES107 L – T – P –C:0-0-3-1
Course Objectives:
Sl.No
Course Objectives
1 Identify problems and design challenges involved in an
Embedded System and program using Embedded C.
2 Write programs for a specific Application.
3 Learn the concept of memory map and memory interface.
4 Know the characteristics of Real Time Systems.
Course Outcomes:
Course
outcome
Descriptions
CO1
Apply the knowledge of Programming for different applications.(L3)
CO2 Outline the performance of real time systems.(L2)
CO3 Develop the Building Blocks of Embedded Systems. (L3)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Description
I
Create n number of child threads. Each thread prints the message “I am in
thread number …” and sleeps for 50 ms/2 sec and then quits. The main thread
waits for complete execution of all the child threads and then quits. Compile
and execute in Linux.
II
Implement the multithread application satisfying the following:
i. Two child threads are created with normal priority.
ii. Thread 1 receives and prints its priority and sleeps for 50ms and then quits.
iii. Thread 2 prints the priority of the thread 1 and rises its priority to above
normal and retrieves the new priority of thread 1, prints it and then quits.
iv. The main thread waits for the child thread to complete its job and quits.
III Implement the usage of anonymous pipe with 512 bytes for data sharing
between parent and child processes using handle inheritance mechanism.
IV
Test the program application for creating an anonymous pipe with 512 bytes of
size and pass the “Read Handle” of the pipe to a second process using memory
mapped object. The first process writes a message “Hi from Pipe Server”. The
2nd process reads the data written by the pipe server to the pipe and displays it
on the console. Use event object for indicating the availability of data on the
pipe and mutex objects for synchronizing the access in the pipe.
V
Create a POSIX based message queue for communicating between two tasks
as per the requirements given below:-
i. Use a named message queue with name “My Queue‟. ii. Create two tasks(Task1&Task2) with stack size 4000 & priorities 99 & 100
respectively.
iii. Task 1 creates the specified message queue as Read Write and reads the message present, if any, from the message queue and prints it on the console.
iv. Task2 open the message queue and posts the message Hi fromTask2.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: II
Subject Name: Analog CMOS VLSI Design
Subject Code:VES201 L – T – P – C :4-0-0-4
Course Objectives :
Sl.No
Course Objectives
1 To understand the concept of current mirrors and its types
2
To understand the different CMOS amplifier
configurations
3
To have an insight on differential amplifiers and
operational amplifiers.
4
To have an insight of different oscillators and noise
characteristics
Course Outcomes :
Course
outcomes
Descriptions
CO1 To have a knowledge of current mirrors and its types. (L1)
CO2 To analyze different CMOS amplifier configurations. (L4)
CO3
To have a knowledge of on differential amplifiers and operational
amplifiers.(L2)
CO4 To have a knowledge of different oscillators and noise characteristics.(L2)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
CMOS Single Stage Amplifiers: Common-Source stage (with resistive load,
diode connected load, current-source load, Triode load, Source degeneration),
source follower, common-gate stage, cascode stage, folded cascode stage,
Frequency responses of CS stage and cascade stage.
12
II
Differential Amplifier & Operational Amplifiers: Single-ended and
differential operation, basic differential pair – qualitative and quantitative
analyses, common-mode response, differential pair with MOS loads,
Performance parameters of op-amp, one stage op-amp, two-stage CMOS op-
amp, Gain boosting, slew rate, power supply rejection.
10
III
Analog CMOS sub-circuits: Introduction to analog design, Passive and active
current mirrors, Switched Capacitor circuits - basic principles, sampling
switches, switched capacitor integrator, switched capacitor amplifier,.
11
IV
Oscillators: General considerations, Ring oscillators, LC oscillators – cross-
coupled oscillators, Colpitts oscillator, One-port oscillator, and voltage
controlled oscillators.
10
V
Noise Characteristics: Statistical characteristics of noise, Types of noise -
thermal noise, flicker noise, Representation of noise in circuits, noise in single-
stage amplifiers (CS stage), noise bandwidth.
9
Text Book:
Sl
No
Text Book title
Author
Volume and Year
of Edition
1
Design of analog CMOS integrated
circuits
Razavi McGraw Hill,
Edition 2002
Reference Books:
Sl
No
Text Book title
Author
Volume and Year of
Edition
1
Analysis and design of Analog
Integrated Circuits.
Gray, Meyer, Lewis,
Hurst
Willey International, 4th
Edition, 2002.
2
CMOS analog circuit design. Allen, Holberg Oxford University Press, 2nd Edition, 2012.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: II
Subject Name: Low Power VLSI Design
SubjectCode:VES202 L – T – P – C:4-0-0-4
Course Objectives:
Sl. No
Course Objectives
1 To summarize the power optimization and trade off in digital circuits.
2 To illustrate the power estimation at different abstract levels.
3
To classify the general purpose and special techniques for low power
system design.
4 To learn software co design in low power design
Course Outcomes:
Course
outcome
Descriptions
CO1
Understand the need for low power design and different sources of power
dissipation in CMOS circuits. (L2)
CO2
Demonstrate the different power optimization technique with trade off at
various levels of abstraction.(L3, L4)
CO3
Identify special techniques for low power applications.(L3)
CO4 To get familiar with software co design for low power designs.(L2)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Introduction to Low Power VLSI design and Analysis: Introduction to low
power VLSI design, Need for low power, Charging and Discharging
Capacitance, Short-Circuit Current in CMOS, CMOS leakage current,-Static current, Basic principles of low power design.
12
II
Simulation and Probabilistic Power Analysis: Spice Circuit Simulation,
Discrete
Transistor Modeling and Analysis, Gate level Logic Simulation, Architecture
level Analysis, Probabilistic Power Analysis-Random logic signal, probability
and frequency, power analysis techniques, signal entropy.
12
III
Circuit level and Logic level design techniques: Circuit, transistor and gate
sizing, pin ordering, network restructuring and reorganization, adjustable
threshold voltages, logic-Gate reorganization, signal gating, logic encoding, Pre-computation logic.
10
IV Special low power VLSI design techniques: Power reduction inclock
networks, CMOS floating node, Delay balancing, Switching activity reduction,
parallel architecture voltage reduction, operator reduction, loop unrolling.
10
V
Software design and Power estimation: Low power circuit design style,
Sources of Software Power Dissipation, Software power estimation, Co-
design for low power.
8
Text Books:
Sl
No
Text Book title
Author
Volume and Year
of Edition
1
Practical Low Power Digital VLSI
Design
Gary Yeap Springer US, Kluwer
Academic Publishers,
2002.
2 Low power CMOS VLSI circuit design Kaushik Roy, Sharat
C. Prasad
Wiley Inter science
Publications",1987.
21
Reference Book:
Sl
No
Text Book title
Author
Volume and Year
of Edition
1
Low Voltage Low Power VLSI
Subsystems
Kiat-Seng Yeo,
Kaushik Roy
Tata Mc-Graw Hill, 2009. 13
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: II
Subject Name: Advances in VLSI Design
Subject Code:VES203 L – T – P –C:4-0-0-4
Course Objectives:
Sl.No Course Objectives
1
To make the students to learn the principles, operations and quantitative
analysis of the semiconductor devices MESFETs, MODFETs and
MOSFETs.
2 To make the students to learn the revolutionary advances and
evolutionary advances in CMOS VLSI.
3 To make the students to learn special circuit layouts and technology
mapping and system design.
Course Outcomes
Course
outcome
Descriptions
CO1 Design of CMOS circuits using MOSFETs and transmission gates (L1)
CO2 Quantitative analysis of MESFETs and the concept of modulation doping (L2)
CO3
Quantitative analysis of MOSFETs and small signal modelling of
MOSFETs, MESFETs (L4)
CO4
Beyond CMOS and design of special circuit layouts and technology
mapping and system design.(L4)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Unit 1:
Review of MOS Circuits:MOS and CMOS static plots, switches, comparison between CMOS and BI - CMOS.
MESFETS: MESFET and MODFET operations, quantitative description of
MESFETS. (Text1)
12
II
Unit 2:MIS Structures and MOSFETS: MIS systems in equilibrium, under
bias, small signal operation of MESFETS and MOSFETS. (Text1)
10
III
Unit 3: Short Channel Effects and Challenges to CMOS: Short channel
effects, scaling theory, processing challenges to further CMOS miniaturization
Beyond CMOS: Evolutionary advances beyond CMOS, carbon Nano tubes.
(Text1)
10
IV
Unit 4:BeyondCMOS:Contd..
Conventional vs. tactile computing, computing, molecular and biological
computing Mole electronics-molecular Diode and diode- diode logic, Defect
tolerant computing. (Text1)
System Design: CMOS design methods, structured design methods, Strategies
encompassing hierarchy, regularity, modularity & locality, CMOS Chip design
Options, programmable logic. (Text2)
10
V
Unit 5:
System Design:Contd.. Programmable inter connect, programmable structure,
Gate arrays standard cell approach. (Text2)
SpecialCircuit Layouts and Technology Mapping: Introduction, Talley
circuits, NAND-NAND, NOR- NOR, and AOI Logic, NMOS, CMOS
Multiplexers, Barrel shifter. (Text3)
10
Text Books:
Sl No
Title Authors Volume and Year of Edition
1 Introduction to Semi-Conductor Device Kevin F Brennan Cambridge publications.
2 Principles of CMOS VLSI Design: A
System Perspective
Neil Weste and K.
Eshragian,
2nd edition, Pearson
Education (Asia) Pte.
Ltd., 2000.
3 Introduction to VLSI Design Eugene D Fabricius Mc Graw Hill,
International Edition
(Original Edition
1990).
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Reference Books:
Sl
No
Title
Authors Volumeand Year of
Edition
1 CMOS VLSI Design: A Circuits and
System perspective,
Neil H E Weste,
David Haris,Ayan,
3 rd edition, Pearson
Education (Asia) Pvt.
Ltd., 2000.
2 Basic VLSI Design Douglas A.
Pucknell& Kamran
Eshraghian
Wiley Indian PHI 3rd
Edition (original
edition 1994), 2005.
3 Modern VLSI design: System on Silicon Wayne, Wolf, Pearson Education,
Second Edition ,
2002
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: II
Subject Name: Real Time Embedded System
Subject Code:VES204 L – T – P –C:4-0-0-4
Course Objectives:
Sl.No
Course Objectives
1 The objective of the course is to learn and understand the implementation and
applications of the embedded system.
2
Discuss the historical background of Real-time systems and its classifications.
3
The course also covers the various software development approaches and a
operating system services required. Hence the course is the unified approach of both
hardware and software in designing the embedded system.
4
Discuss the languages to develop software for Real- Time Applications. The
objective of the course is to learn and understand the implementation and
applications of the embedded system.
Course Outcomes:
Course outcome
Descriptions
CO1 Describe the differences between the general computing system and the embedded system, also recognize the classification of embedded systems.(L2)
CO2 Become aware of the architecture of the ARM processor and its programming
aspects (assembly Level)(L3)
CO3
Become aware of interrupts, software optimization., Design real time embedded
systems using the concepts of RTOS, commercially available RTO’s, Analyze
various examples of embedded systems(L3)
:
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Unit 1:Introduction: Real Time System, Types, Real Time Computing, Design Issue, Sample
Systems, Hardware Requirements- Processor in a system, System Memories,
System I/O, Other Hardware Devices (A/D, D/A, USART, Watchdog Timers,
Interrupt Controllers). Device Drivers, Interrupt Servicing Mechanism &
Interrupt Latency.
12
II
Unit 2:ARM Processor Fundamentals and ARM7TDMI: ARM Processor Registers, current program status register, Pipeline
Exceptions, Interrupt and vector table, Reset operation. ARM7 TDMI
processor block diagram, ARM7TDMI Features, programmer’s model, sample
programs
[Text: 2 chapter1.1 to 1.4 & chapter 2.1 to 2.4]
10
III
Unit 3: Real Time Operating System: Fundamental Requirements of RTOS,
Real Time Kernel Types, Schedulers, Various Scheduling modules with
examples, Latency (Interrupt Latency, Scheduling Latency and Context
Switching Latency), Tasks, State Transition Diagram, Task Control Block.
Inter-task communication and synchronization of tasks.
10
IV
Unit 4:Memory and File management: Pipelining and Cache Memories,
Paging and Segmentation, Fragmentation, Address Translation.
10
V
Unit5:Introduction to VX Works/Mucos/pSOS;Example systems.,
development and Verification of Real Time Software: Building Real Time
applications; Considerations such as double buffing.
10
Text Books:
Sl
No
Title
Authors Volume and Year
of Edition
1 An Embedded software primer,
Pearson Education Inc. David E. Simon 2nd edition, Pearson
Education (Asia)
Pte. Ltd., 2000.
2 ARM System Developer’s Guide Andrew N. Sloss,
Dominic Symes and
Chris
Wright..
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
3 Real-Time Systems Design and
Analysis- an Engineer’s Handbook Philip. A. Laplante, Second Edition, PHI Publications.
Reference Books:
Sl
No
Title
Authors Volumeand Year of
Edition
1 Real-Time Systems
3.Jane W.S. Liu, Pearson Education
Inc.,2000.
2 Embedded Systems: Architecture,
Programming and Design Rajkamal Tata McGraw Hill,
New Delhi.
3 Embedded Real Time Systems:
Concepts Design and Programming Dr. K.V.K K Prasad, Dreamtech Press
New Delhi.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: II
Subject Name: Digital System Design using Verilog
Subject Code:VES251 L – T – P – C:4-0-0-4
Course Objectives :
Sl.No
Course Objectives
1
Understand the concepts of Real world circuits, Models and Design Methodology.
2
Discuss the Combinational Circuits and Sequential Circuits , its verilog code and its Verification.
3 Implement the design of systems like Memories, interconnect etc.
4 Design and develop the processor basics and I/O interfacing.
Course Outcomes :
Course
outcome
Descriptions
CO1
Interpret the knowledge of Digital Systems and Embedded Systems.(L2)
CO2
Design of Combinational circuits and its Verification.(L3)
CO3 Design of sequential Circuits and memories.(L3)
CO4 Outline the Concepts of Design methodology and I/O Interfacing
circuits(L2)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Unit 1:
Introduction and Methodology: Digital Systems and Embedded Systems,
Binary Circuit Elements, Real-World Circuits, Models, Design Methodology.
Combinational Basics: Boolean Functions and Boolean Algebra, Binary
Coding, Combinational Components and Circuits, Verification of
Combinational Circuits.
11
.
II
Unit 2:
Number Basics: Unsigned and Signed Integers, Fixed and Floating-point
Numbers.
Sequential Basics: Storage elements, Counters, Sequential Data paths and
Control, Clocked Synchronous Timing Methodology.
11
II
Unit 3:
Memories: Concepts, Memory Types, Error Detection and Correction.
Implementation Fabrics: ICs, PLDs, Packaging and Circuit Boards,
Interconnection and Signal Integrity
10
III
Unit 4:
Processor Basics: Embedded Computer Organization, Instruction and Data,
Interfacing with memory.
I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial Transmission, I/O software.
10
IV
Unit 5:.
Accelerators: Concepts, case study, Verification of accelerators.
Design Methodology: Design flow, Design optimization, Design for test.
10
Text Book:
Sl
No
Text Book title
Authors Volume and Year
of Edition
1
Digital Design: An Embedded Systems
Approach Using VERILOG
Peter J. Ashenden
Elsevier, 2010.
Reference Books:
Sl
No
Text Book title
Authors Volume and Year
of Edition
1 A Verilog HDL Primer J. Bhasker Second Edition, Star
Galaxy, 2005
2 A Verilog Synthesis: A Practical Primer J. Bhasker Star Galaxy, 1998
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: II
Subject Name: Solar Cells and Thin Film Technologies
Subject Code:VES252 L – T – P – C :4-0-0-4
Course Objectives:
Sl. No
Course Objectives
1
The course is intended for students who have interest in alternate energy sources as a
contributor to sustainability.
2
It provides a comprehensive treatise on the science and technology of solar energy, its
collection and the design principles that need to be understood for its effective use in a
variety of installations and uses.
3
Understand the factors that influence the use of solar radiation as an energy source; know the various active and passive technologies that are available for collecting solar energy.
4
The ability to apply design principles to selection of an appropriate solar energy installation
to meet the requirement.
5
This course is designed for those students who are interested in thin film fundamentals and
processing for various industrial applications.
Course Outcomes:
Course
outcome
Descriptions
CO1
Gain knowledge about the available solar energy and the current solar energy conversion
and utilization processes.(L2)
CO2
Have a working knowledge of semiconductor physics, optical systems, photovoltaic
engineering, load matching, and storage and grid connections.(L1)
CO3
Be able to comprehend the challenges in sustainable energy processes, perform cost
analysis, and design different cell systems for different applications meeting residential and
industrial needs.(L3)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
CO4
Familiarization of different properties of a thin film material Identify emerging
applications using thin film based devices.(L1)
UNIT Description Hours
I
SOLAR IRRADIANCE:
Basics of light: properties of light, energy of photon, photon flux, spectral
irradiance, radiant power density, black body radiation, sun radiation.
Solar Radiation:The Sun, solar radiation in space, solar radiation outside the
earth’s atmosphere, terrestrial solar radiation, solar radiation at the earth’s
surface, atmospheric effects, air mass, motion of the sun, solar time, declined ion
angle, elevation angle, azimuth angle, the sun’s position, solar radiation on a
tilted surface, arbitrary orientation and tilt, calculation of solar insulation,
measurement of solar radiation.
12
II
PN JUNCTION
Basics: Semiconductor materials, semiconductor structure, conduction in
semiconductor, band gap, intrinsic carrier concentration, doping, and equilibrium
carrier concentration.
Generation: Absorption of light, absorption coefficient, absorption depth,
generation rate.
Recombination: Types of recombination, life time, diffusion length, surface
recombination.
Carrier Transport: Movements of carriers in semiconductor, diffusion, drift.
PN Junction: Formation of a PN junction, PN junction diode, bias of PN
junctions, diode equations, diode equation for PV, ideal diode equation
derivation, basic equations, applying basic equations to a PN junction, solving
for depletion region and quasi-neutral regions, finding total current.
12
III
SOLAR CELLS:
Principles of solar cell operation: Electrical characteristics, optical properties,
typical solar cell
structures, ideal efficiencies. Crystalline silicon solar cells: Manufacturing and properties of Crystalline
silicon, high-efficiency laboratory cells, screen-printed cells, laser-processed
cells, HIT cell, rear-contacted cells, thin silicon solar cells – light trapping,
voltage enhancements, silicon deposition and crystal growth.
10
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
IV
THIN-FILM SILICON SOLAR CELLS: Hydrogenated amorphous silicon (a-
Si:H) layers , hydrogenated microcrystalline silicon (μSi:H) layers, p-i-n and n-i-
p structures, tandem and multi-junction solar cells.
9
V
RECENT ADVANCES IN THIN-FILM SOLAR CELLS: CdTe based thin
film solar cells, uInSe2 (CIS) based thin-film solar cells, thin-film GaAs solar cells, Chalcopyrite Based
Solar Cells, concentrator silicon solar cells, dye-sensitized thin-film solar cells,
organic solar cells
9
Text Books:
Sl
No
Text Book title Author Volume and Year
of Edition
1 Principles of Solar Cells, LEDs and
Diodes: The role of the PN junction
Adrian Kitai, John Wiley & Sons,
2011
2 Solar Cells: Materials, Manufacture and Operation
Augustine McEvoy,
L. Castaner, Tom
Markvart,
2nd edition, Newnes,2012.
Reference Books:
Sl
No
Text Book title Author Volume and Year
of Edition
1 Thin-Film Silicon Solar Cells Arvind Shah Illustrated
edition, EPFL Press, 2010.
2 Advances in Thin-Film Solar Cells M. Dharmadasa Illustrated edition,
CRC Press, 2012.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: II
Subject Name: RF VLSI Design
SubjectCode:VES253 L – T – P – C :4-0-0-4
Course Objectives:
Sl. No
Course Objectives
1
To explore the various performance measures of RF circuits.
2
To acquire knowledge on the design of RF filters, amplifiers and oscillators
Course Outcomes:
Course
outcome
Descriptions
CO1 Understand the various performance measures of RF circuits.(L2)
CO2 Understand the design of RF filters, amplifiers and oscillators.(L2)
CO3 Analyze the various types of power amplifiers operations with respect to efficiency.(L3)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
PERFORMANCE PARAMETERS OF RF CIRCUITS: Gain Parameters,
Non-linearity parameters, Noise figure, Phase Noise, Dynamic range, RF front
end performance parameters, performance trade-offs in an RF circuit.
10
II
FILTER DESIGN: Modern filter design, Frequency and impedance scaling,
High Pass filter design, Band pass filter design, Band reject filter design, the
effects of finite Q.
12
III
HIGH FREQUENCY AMPLIFIER DESIGN: Zeros as Bandwidth enhances,
Shunt-series Amplifier, Bandwidth enhancement with frequency Doublers,
Tuned amplifiers, Neutralization and uni lateralization, cascaded Amplifiers.
10
IV
MIXERS AND OSCILLATORS: Mixer fundamentals, Nonlinear systems as
Linear mixers, multiplier based mixers, Subsampling mixers. Problems with
purely linear oscillators, Tuned oscillator, Negative Resistance oscillators,
10
V
RF POWER AMPLIFIERS: General considerations, Class A, AB, B and C
Power amplifier, Class D, E and F amplifiers, modulation of power amplifiers,
RF Power amplifier design examples.
10
Text Books:
Sl
No
Text Book title
Author
Volume and Year of
Edition
1
Adaptive Low Power Circuits for
Wireless Communication (Analog
Circuits and Signal Processing)
Aleksandar Tasic,
Wouter.A.Serdijn,
John.R.Long
Springer, 1st Edition,
2006.
2 RF Circuit design Chris Bowick Newnes (An imprint
of Elesvier Science),
1stEdition, 1997.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Reference Book:
Sl
No
Text Book title
Author
Volume and Year
of Edition
1 The design of CMOS Radio-Frequency
Integrated Circuits
Thomas.H. Lee Cambridge
University Press, 2nd
Edition, 2004
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: II
Subject Name: VLSI Lab
SubjectCode:VES207 L – T – P –C:0-0-3-1
Course Objectives:
Sl.No.
Course Objectives
1 To learn the use of schematic editor, physical design and circuit
simulation tools.
2
To design and verify the functionality of combinational and sequential
circuits.
3 To perform AC and DC analysis of circuits edited using physical design tool.
CourseOutcomes:
Course
outcome
Descriptions
CO1 Design and simulate gate level, circuit schematics and layouts for combinational and sequential circuits.(L3)
CO2 Able to check the design rules for the edited layouts.(L2)
CO3
Analyze the working and performance of the circuits in schematic editor
and physical design tool.(L4)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Sl.No. Description
I
Lay out editing and circuit simulation of NMOS, Pseudo NMOS and CMOS
Inverters.
II
Lay out editing and circuit simulation of CMOS based basic gates and design
of digital circuits using CMOS gates.
III Lay out editing and circuit simulation of transmission gate (TG) and
transmission gate (TG) based digital circuits
IV
Study of full adder and parallel adder
V
Study of flip – flops, serial register and counters
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: IV
Subject Name: Reliability Engineering
Subject Code:VES411 L – T – P –C:4-0-0-4
Course Objectives :
Sl.No
Course Objectives
1
Understand and emphasizes dependability in the lifecycle
management of a product.
2
Apply and identify and manage assets reliability risks that
could adversely affect plant or business operations.
3 Understand the concepts related to reliability engineering
Course Outcomes :
Course
outcome
Descriptions
CO1 Interpret the basic concepts of reliability engineering and its measures.(L2)
CO2 Predict the reliability at system level using various models.(L3)
CO3 Design the test plan to meet the reliability requirements(L3)
CO4 Predict and estimate the reliability from failure data(L1)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Introduction :Basic definitions: Reliability, Availability, Serviceability,
Failure rate, Reliability Mathematics, Failure distribution - constant failure
rate model, Time dependent failure rate models and its types, Bath tub curve.
case study or Videos on Human Reliability, Software Reliability.
12
II
System Reliability: Reliability Block Diagram - Series, Parallel & combined
series parallel configurations; redundant-active and passive types, Failure
Mode, Effects and Criticality Analysis (FMECA), Failure Reporting, Analysis
and Corrective Action System (FRACAS),Fault Tree Analysis (FTA), System
state analysis-Markov Model, Availability, Downtime.
10
III
Reliability testing: Failures and types of failures; Intrinsic & extrinsic
failures; Failure cascade; Failure mode; Failure rate, MTTF, MTBF,
Accelerated life testing (ALT) -Qualitative ALT, Quantitative ALT & its
types, AF, Samples
10
IV
Reliability estimation and life Prediction: Types of Failure data - Data
censoring, Parametric and Non Parametric distribution, Probability density
function, Exponential, Normal, lognormal & weibull distributions, weibull
Goodness of fit distributions, Electronics reliability prediction-parts count,
parts stress method, MIL standard, Naval Surface Warfare Center(NSWC).
10
V
Reliability Management: Design for Reliability, Relationship between
Reliability and safety factor, Stress-Strength interference theory,
Reliability growth testing, Reliability centered maintenance (RCM),
Spares planning.
10
Text Books:
Sl
No
Text Book title
Author
Volume and Year
of Edition
1 Reliability Engineering
Kailash C. Kapur,
Michael Pecht,
John Wiley & Sons,
2014.
2 Reliability Engineering
Srinath L.S East-West Press Pvt
Ltd, New Delhi,1998.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Reference Books:
Sl
No
Text Book title
Author
Volume and Year
of Edition
1 Reliability and Risk analysis
Modarres Marshal Dekker
Inc.1993.
3 Introduction to Reliability in Design Smith
C.O.RoyBillington
and Ronald N. Allan
McGraw Hill,
London, 1976.
4 An introduction to Reliability and
Maintainability engineering Charles E. Ebeling, TMH, 2004
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: IV
Subject Name: High Speed VLSI Design
SubjectCode:VES412 L – T – P –C:4-0-0-4
Course Objectives:
Sl.No
Course Objectives
1
To make the students to learn the process variability and
non-clocked logic styles
2
To make the students to learn the circuit design margin and
design variability
3
To make the students to learn latching strategies, interface
techniques and clocking styles
Course Outcomes:
Course
outcome
Descriptions
CO1
Study of front-end -of-line variability considerations, charge loss
mechanisms, back-end-of- line variability considerations. (L1)
CO2
Design of single and dual-rail domino, and latched domino structures.(L4)
CO3 Circuit Design margin and design variability(L2)
CO4 Study of Latching Strategies, Interface Techniques, Clocking styles. (L2)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Unit 1:Process Variability: Introduction, Front-end -of-line variability
considerations, charge loss mechanisms, back-end-of- line variability
considerations.
12
II
Unit 2:Non-Clocked logic styles: Introduction, static CMOS structures, DC
VS logic, Non-clocked pass-gate families.
Clocked logic styles: Introduction, single-rail domino logic styles. Dual-rail
domino structures, latched domino structures, clocked pass gate logic
10
III
Unit 3: Circuit Design margin and design variability: Introduction, process
induced variation, design induced variations, and application induced
variations, Noise.
Introduction, basic latch design, latching single ended logic.
Latching Strategies:, latching differential logic, race-free latched for pre-
charge logic.
10
IV
Unit 4:Interface Techniques: Introduction, signaling standard, chip-chip
communication networks, ESD protection, Driver design techniques, receiver
design techniques.
10
V
Unit 5:
Clocking styles: Introduction, clock jitter and skew, clock generation and clock distribution.
10
Text Books:
Sl
No
Title
Authors
Volume and Year of
Edition
1
High Speed CMOS Design Styles
Kerry Bernstein &
et. al.,
Kluwer, 1999
2 High Speed Digital Design Howard Johnson &
Martin Graham A Handbook of
Black Magic,
Prentice Hall PTR,
1993
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Reference Books:
Sl
No
Title
Authors
Volumeand Year of
Edition
1 Digital Systems Engineering William S. Dally &
John W. Poulton
Cambridge
University Press,
1998.
2
High Speed Digital Circuits
Masakazu Shoji
Addison Wesley
Publishing Company, 1996..
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: IV
Subject Name: VLSI Testing and Verification
SubjectCode:VES413 L – T – P –C:4-0-0-4
Course Objectives:
Sl.No
Course Objectives
1
Understand the various benefits involved in VLSI Testing.
2 Apply the concepts of testing and fault modeling
3
Understand the concepts related to advanced Design for
testability and Fault diagnosis.
Course Outcomes:
Course
outcome
Descriptions
CO1
Interpret the different challenges involved in VLSI Testing and Fault
Modeling.(L2).
CO2
Explain various design for testability and self test and test algorithm.(L2).
CO3
Explain the design concepts of fault diagnosis.(L2).
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Basics of testing and fault modelling: Introduction to Testing - Faults in
digital circuits - Modelling of faults - Logical Fault Models – Fault detection -
Fault location - Fault dominance - Logic Simulation - Types of simulation -
Delay models - Gate level Event-driven simulation.
8
II
Test generation for combinational and Sequential Circuit: Test generation
for combinational logic circuits - Testable combinational logic circuit design -
Test generation for sequential circuits - design of testable sequential circuits.
12
III
Design for testability: Design for Testability - Ad-hoc design - Generic scan
based design - Classical scan based design - System level DFT approaches.
10
IV
Self-test and test algorithms: Built-InSelf Test - Test pattern generation for
BIST - Circular BIST - BIST Architectures – Testable Memory Design - Test
algorithms - Test generation for Embedded RAMs.
12
V
Fault Diagnosis: Logic Level Diagnosis - Diagnosis by UUT reduction - Fault
Diagnosis for Combinational Circuits - Self-checking design - System Level
Diagnosis.
10
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Text Books:
Sl
No
Text Book title
Authors
Volume and Year
of Edition
1 Digital Systems and Testable Design
M. Abramovici,
M.A. Breuer and A.D. Friedman,
Jaico Publishing House.
2 Essentials of Electronic Testing for
Digital, Memory and Mixed-Signal
VLSI Circuits
M.L. Bushnell and
V.D. Agrawal,
Kluwer Academic
Publishers.
Reference Books:
Sl
No
Text Book title
Authors
Volume and Year
of Edition
1 Design Test for Digital IC's and
Embedded Core Systems A.L. Crouch Prentice Hall International.
2 Digital Circuit Testing and Testability
P.K. Lala
Academic Press,
2002.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: IV
Subject Name: Internet of Things
Subject Code:VES421 L – T – P – C :4-0-0-4
Course Objectives:
Sl.No
Course Objectives
1
Understand the way the number of devices in the Physical world, with
different type of technologies, the mode of interconnections and the
integration is enabled in order that intelligent services are provided.
2
Obtain information about collaborating and integrating the data from
different objects subjected to non-uniformity, inconsistency and
inaccuracy
3
Understand the Complete way of realizing smart services like
surveillance networks.
Course Outcomes :
Course
outcome
Descriptions
CO1 Outline the OSI model for the IOT/M2M Systems. (L1)
CO2 Interpret the architecture and design principles for IOT. (L3)
CO3 Study the Programming for IOT applications. (L3 & L4)
CO4
Describe the conventional Protocols which are adaptive to the Wireless
Sensor networks. (L2)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Overview of Internet of Things: IoT Conceptual Framework, IoT
Architectural View, Technology Behind IoT, Sources of IoT,M2M
communication, Examples of IoT. Modified OSI Model for the IoT/M2M
Systems, data enrichment, data consolidation and device management at
IoT/M2M Gateway, web communication protocols used by connected
IoT/M2M devices, Message communication protocols (CoAP-SMS, CoAP-
MQ, MQTT,XMPP) for IoT/M2M devices.
12
II
Architecture and Design Principles for IoT: Internet connectivity, Internet-
based communication,IPv4, IPv6,6LoWPAN protocol, IP Addressing in the
IoT, Application layer protocols: HTTP, HTTPS,FTP,TELNET and ports.
10
III
Data Collection, Storage and Computing using a Cloud Platform:
Introduction, Cloud computing paradigm for data collection, storage and
computing, Cloud service models, IoT Cloud- based data collection, storage
and computing services using Nimbits.
10
IV
Prototyping and Designing Software for IoT Applications: Introduction,
Prototyping Embedded device software, Programming Embedded Device
Arduino Platform using IDE, Reading data from sensors and devices, Devices,
Gateways, Internet and Web/Cloud services software development.
Programming MQTT clients and MQTT server. Introduction to IoT privacy
and security. Vulnerabilities, security requirements and threat analysis, IoT
Security Tomography and layered attacker model.
10
V
Communication Protocols: Physical Layer and Transceiver Design
Considerations, MAC Protocols for Wireless Sensor Networks, Low Duty
Cycle Protocols And Wakeup Concepts - S-MAC , The Mediation Device
Protocol, Wakeup Radio Concepts, Contention based
protocols(CSMA,PAMAS), Schedule based protocols (LEACH, SMACS,
TRAMA) Address and Name Management in WSNs, Assignment of MAC
Addresses, Routing Protocols- Energy-Efficient Routing, Geographic Routing,
Hierarchical networks by clustering.
10
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Text Books:
Sl
No
Text Book title
Author
Volume and Year
of Edition
1 Internet of Things-Architecture and
design principles
Raj Kamal McGraw Hill
Education
2 Protocols and Architectures for Wireless
Sensor Networks
Holger Karl &
Andreas Willig
John Wiley, 2005.
3 Wireless Sensor Networks- An
Information Processing Approach
Feng Zhao &
Leonidas J. Guibas.
Elsevier, 2007
Reference Books :
Sl
No
Text Book title
Author Volume and Year
of Edition
1 Wireless Sensor Networks Technology,
Protocols and Applications
Kazem Sohraby,
Daniel Minoli &
Taieb Znati.
John Wiley, 2007
2 Wireless Sensor Network Designs Anna Hac John Wiley, 2003.
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: IV
Subject Name: CMOS Mixed Signal Circuit Design
SubjectCode:VES422 L – T – P – C :4-0-0-4
Course Objectives:
Sl.No
Course Objectives
1 To know mixed signal circuits like PLL, DAC, ADC.
2
To gain knowledge on basic design requirements needed
for building converters.
3
To acquire advanced knowledge on design of different
architectures in mixed signal mode.
Course Outcomes
Course
outcome
Descriptions
CO1
Understand different building blocks required for the design of mixed
signal circuits. (L2)
CO2
Understand various design aspects associated with designing analog and
digital converters(L2)
CO3
Analyse different design modifications to improve the performance of
various converters(L4)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Phase Locked Loop: Characterization of a comparator, basic CMOS
comparator design, PLL - simple PLL, charge-pump PLL, applications of PLL.
11
II
Switched-Capacitor Circuits: General Considerations, Sampling Switches,
Switched-Capacitor Amplifiers, Switched-Capacitor Integrator.
10
III
Sampling Circuits: Basic sampling circuits for analog signal sampling,
performance metrics of sampling circuits, different types of sampling switches.
Sample-and-Hold Architectures- Open-loop & closed-loop architectures, open-
loop architecture with miller capacitance, multiplexed-input architectures,
recycling architecture, switched capacitor architecture, current-mode
architecture.
11
IV
D/A Converter Architectures: Input/output characteristics of an ideal D/A
converter, performance metrics of D/A converter, D/A converter in terms of
voltage, current, and charge division or multiplication, switching functions to
generate an analog output corresponding to a digital input. Resistor-Ladder
architectures, Current steering architectures.
11
V
A/D Converter Architectures: Input/output characteristics and quantization
error of an A/D converter, performance metrics of pipelined architectures,
Successive approximation architectures, interleaved architectures.
09
Text Books:
Sl
No
Text Book title
Author
Volume and Year of
Edition
1
Design of analog CMOS integrated
circuits
Razavi
McGraw Hill,
Edition 2002
2
Principles of data conversion system design
Razavi
Wiley IEEE Press,
1st Edition, 1994
3
CMOS Mixed-Signal circuit design
Jacob Baker
Wiley Student
edition, IEEE Press, 2009
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Reference Books:
Sl
No
Text Book title
Author Volume and Year
of Edition
1 Analog MOS Integrated Circuit for
signal processing
Gregorian, Temes John Wiley & Sons,
1986.
2 CMOS: Circuit Design, layout and
Simulation
Baker, Li, Boyce PHI, 2000
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Department of Electronics and Communication
M.Tech in VLSI & Embedded systems
Syllabus for the Academic Year –2020 - 2021
Semester: IV
Subject Name: System Verilog
Subject Code:VES423 L – T – P – C:4-0-0-4
Course Objectives :
Sl.No
Course Objectives
1
Understand digital system verification using object oriented methods
2
Learn the System Verilog language for digital system verification.
3
Create/build test benches for the basic design/methodology.
4 Use constrained random tests for verification and Understand concepts of functional coverage.
Course Outcomes :
Course
outcome
Descriptions
CO1 Explain OOPs concepts and system Verilog data types,(L2)
CO2
Write test benches for moderately complex digital circuits.(L1)
CO3
Use System Verilog language and Appreciate functional coverage. (L3)
CO4
Apply constrained random tests benches using System Verilog and
Analyze a verification case and apply System Verilog to verify the
design(L3)
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
UNIT Description Hours
I
Unit 1:
Verification Guidelines: The verification process, basic test bench
functionality, directed testing, methodology basics, constrained random
stimulus, randomization, functional coverage, test bench components, layered
testbench.
Data Types: Built in Data types, fixed and dynamic arrays, Queues,
associative arrays, linked lists, array methods, choosing a storage type,
creating new types with type def, creating user defined structures, type
conversion, Enumerated types, constants and strings, Expressionwidth.
12
II
Unit 2:
Procedural Statements and Routines: Procedural statements, Tasks,
Functions and void functions, Task and function overview, Routine arguments,
returning from a routine, Local data storage, time values.
Converting the test bench and design: Separating the test bench and design,
The interface construct, Stimulus timing, Interface driving and sampling,
System Verilog assertions.
10
III
Unit 3:
Randomization:
Introduction, Randomization in System Verilog, Constraint details, Solution
probabilities, Valid constraints, In-line constraints, Random number functions,
Common randomization problems, Iterative and array constraints, Random
control, Random Number Generators.
10
IV
Unit 4:
Threads and Interprocess Communication: Working with threads,
Disabling threads, Interprocess communication, Events, semaphores,
Mailboxes, Building a test bench with threads and Interprocess
Communication.
10
V
Unit 5:
Functional Coverage: Coverage types, Coverage strategies, Simple coverage
example, Anatomy of Cover group and Triggering a Cover group, Data
sampling, Cross coverage, Generic Cover groups, Coverage options,
Analyzing coverage data, measuring coverage statistics duringsimulation.
10
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY-TUMAKURU (A constituent College of Siddhartha Academy of Higher Education,Tumakuru)
Dept of ECE
Text Book:
Sl
No
Text Book title
Authors
Volume and Year
of Edition
1 System Verilog for Verification – A
guide to learning the Test bench
languagefeature.
Chris Spear Springer
Publications,2nd
Edition, 2010
Reference Books:
Sl
No
Text Book title
Authors Volume and Year
of Edition
1 System Verilog for Design- A guide to
using system verilog for Hardware
design and modeling.
Stuart Sutherland,
Simon Davidmann,
Peter Flake
Springer Pulications,
2nd Edition, 2006.
2 System Verilog for Design -A Guide to
Using System Verilog for Hardware
Design and Modeling,
Stuart Sutherland, Simon Davidmann,
Peter Flake,
Springer Science & Business Media, 2nd
Edition15-Sep-2006 .