Utilizing Printed Electronics Methods for the Fabrication of Multi-layer PC Boards
D. R. HinesLaboratory for Physical Sciences
College Park, MD
John Bolger, Leon LantzDepartment of Defense, Ft Meade, MD
Rich Lewis and Rick Trudeau
KeyW Corporation, Hanover, MD
• Goal: Demonstrate the capability of additive manufacturing to fabricate multi-layer PC boards on demand.
• Utilize a 2-layer power supply design requiring a 1 Amp current carrying capability.
• Print alternating layers of Silver nano-particle (AgNP) and polyimide (PI) inks.
• Populate, functionally verify, and perform reliability testing of 14 boards.
Overview
Requirements
Metal Ink
Dielectric Ink
layer 2layer 1
20 mm
16 m
m
Electrical Current Requirement: 1 Amp
Future Layers : Minimum Feature size & pitch <100 um
Feature Sizes:Biggest 2 – 5 mmSmallest 250 um
Printing Methods
Syringe
Ink-Jet
Aerosol-Jet
Considerations for Materials Selections
Droplet Formation
Substrate Wettability
Drying/Sintering Temperature
Solvent Compatibility Thermal Compatibility
• Polyimide coated SiO2/Si substrate
• Ag nanoparticle ink– Solvents: IPA, Ethylene Glycol– Thermal: requires sintering at 255 ˚C to obtain resistivity 6 x 10-8 Ω m
• Polyimide ink– Solvent: NMP – Thermal: requires thermal cure up to 300 ˚C
• Selected materials are stable to all solvent and thermal processing requirements
Materials
• Ag ink: – Print speed 3 mm/sec– Tip Diameter 150 um tip– Ink Stream Diameter 40 um– 200 pL/sec (est.)
• PI ink:– Print speed 6 - 8 mm/sec – Tip Diameter 300 um tip– Ink Stream Diameter 180 um– 7000 pL/sec (est.)
Print Parameters
• Thermally oxidized Si wafer• Spin coated polyimide (5 um)
– Cure: 255 ˚C, 90 min• First Metal Layer (5 um, 2 Passes) and sinter• Dielectric Layer (10 um, 2 Passes) and cure• Second Metal Layer (5 um, 2 Passes) and sinter• Mount substrate on carrier board• Stencil print conductive adhesive• Pick-and-place• Thermal Cure using reflow oven• Removal from Carrier board• Mounted on test board
Process Flow
Board Fabrication Steps
Component Assembly Steps
Serpentine Fill
Perimeter Fill
BorderFill
Pitch
Pattern Fill SchemaPrinter Process Issues
Aerosol-jet printing requirement for the fabrication of Solid Features
40 mm wideline
200 mm wideline
Polyimide Dielectric layer
Ag nanoparticle Ink Sintered at 255 ˚C
Printed Test Structures
Cartoon of Test Structure
Evaluation of Printed Structures
Printed Interconnected Layers Printed two-layer Structure
Ag
Si PI PISi
Ag
Cross-sectional Measurements
Mea
sure
d W
idth
, mm
0
50
100
150
200
250
0 50 100 150 200 250
12 4 8
Targeted Width, mm
Number of
Print Passes
Evaluation of Printed StructuresWidth Measurements
Number of Print Passes
0
5
10
15
20
25
0 5 10 15 20 25
50 um100 um150 um200 um
1 2 4 8
Mea
sure
d Th
ickn
ess,
mm
Targeted Thickness, mm
TargetedWidth
Evaluation of Printed StructuresThickness Measurements
0
20
40
60
80
100
120
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
CalculatedMeasured
Resis
tan
ce
,
Area-1, um-2
R = r L (1/A) = (6.4 ± 0.1)x10-8 W m
Resi
stan
ce, W
Measured Area-1, mm-2
Calculated
Measured
Evaluation of Printed StructuresResistance Measurements
Evolution of 2-layer Board Design
1st Gen
2nd Gen3rd Gen
1-layer Power Supply Board (Ink-Jet printed)
Bottom Layer Top LayerRequired connections
‘vias’
2-Layer Board Artwork
Metal Layers and Interconnects
Creation of Dielectric layer
Metal Layers overlap Remove overlap at ‘vias’
2-Layer Board Artwork
Bottom Metal Layer Top Metal LayerDielectric Layer
Final Artwork2-layer Power Supply Board
~1 mm
Build up of 2-layer Boards
(26) 2-layer Power Supply Boards Fabricated
and Submitted for
Reliability Testing
2-Layer Board Performance Test Process
• Eight (8) boards in Temperature Cycling – 2000 cycles from 0 to 90 ˚C
• Six (6) boards in HTOL @ 90 ˚C– Over 2200 hours to date
• Six (6) boards to Enter Humidity Testing– 85 ˚C/85% RH
Reliability Evaluation
Performance Test Results
High Temperature Operational Life Testing at 90 ˚C
Total of 18 Individual Voltage Regulators -
After more than 2000 hours at 90 ˚C14 Still Operational
2 Show fluctuations & 2 ‘Dead’
4-Layer Boards - Original Artwork
Dielectric 3 Dielectric 2 Dielectric 1
Metal - Bottom Metal - Sig2 Metal – Sig1 Metal – Top
4-Layer Boards - Direct-write Artwork
Dielectric 3 Dielectric 2 Dielectric 1
Metal - Bottom Metal - Sig2 Metal – Sig1 Metal – Top
• Continue reliability evaluation (2-layer boards)– 85 ˚C/85% RH
• Fabrication of 4-layer boards
Future Work
C = r 0 (A/d)
Material r C (1 mm x 1 mm2)
C (1 mm x 1 cm2)
Polyimide dielectric 3 25 pF 1 nF
Barium Titanate nanoparticle dielectric
40 300 pF 12 nF
Dielectric constants of high-k Materials
SiO2 3.9Al2O3 9HfSiO4 11ZrO2 25HfO2 25Ta2O5 27La2O3 30LaAlO3 30Nb2O5 35TiO2 30–40 (Anatase), 80–100 (Rutile)BaTiO3 1700SrTiO3 2000Pb(Zr,Ti)O3, (Pb,La)(Zr,Ti)O3 2500CaCu3Ti4O12 80 000M. Osada and T. Sasaki, Adv. Mater. 24, 210 (2012)
Printed Capacitors
Integrated Components
Si Capacitors as Substrate
Capacitor Interconnect layer
Power Supply Layers
Hybrid Printed Electronic Device on Kapton
2x4 array of 200 nm Thick Si Semiconductor Elements Transfer Printed onto a Kapton Substrate
Next Step: Add dielectric Layer and Gate Electrode.
Ag Nanoparticle Ink
Source
Drain