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VHDL8 Practical example v2b
VHDL 8
Practical example
A single board sound recorder
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The sound recorder hardware(click the picture to see the demo)
VHDL8 Practical example v2b
http://youtu.be/nUheLfsGyYo
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VHDL8 Practical example v2b
Part 1
General concept of memory
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VHDL8 Practical example v2b
Basic structure of a
microprocessor system CPU
Memory
Input/output and peripheral devices Glue logic circuits
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VHDL8 Practical example v2b
A computer system with a
microprocessor
Micro-
Processor
(CPU)
memory
Peripheral devices: serial, parallel interfaces; real-time-clock etc.
Clock
Oscillator
Peripheral devices: serial, parallel
interfaces; real-time-clock etc.
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VHDL8 Practical example v2b
Internal and external interfacing
CPU
memory
Peripheral devices: USB ports,
Graphic card, real-time-clock etc.
Keyboard
mouse
Light,
Temperature
sensors
Effectors: such asMotors,
Heaters,
speakers
Internal
interfacing
External
interfacing
Peripheral IOinterface
devices: such
as USB bus,
parallel bus,
RS232 etc.
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VHDL8 Practical example v2b
CPU, MCU are microprocessors
CPU: Central Processing unit
Requires memory and input output system tobecome a computer (e.g. Pentium).
MCU: micro-controller unit (or single chipcomputer)
Contains memory, input output systems, canwork independently (e.g. Arm7, 8051).
Used in embedded systems such as mp3players, mobile phones.
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VHDL8 Practical example v2b
Memory systems
RAM/ROM
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VHDL8 Practical example v2b
Different kinds of Memory (RAM)
Random access memory (RAM): datawill disappear after power down.
Static RAM (SRAM): each bit is a flip-flop
Dynamic RAM (DRAM): each bit is a smallcapacitor, and is needed to be rechargedregularly
Since we only discuss static (SRAM) here,so the terms SRAM and RAM will be usedinterchangeably.
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VHDL8 Practical example v2b
Different kinds of Memory (ROM)
Read only memory (ROM)
UV-EPROM
EEPROM
FLASH ROM
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VHDL8 Practical example v2b
UV-EPROM
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VHDL8 Practical example v2b
Flash memory
Or SD (secure digital card)http://www.sandisk.com/download/Product%20Manuals/Product%20ManualSDCardv1.7.pdf
http://images.google.com.hk/imgres?imgurl=http://www.sandisk.com/download/photos/retail/sd-2gb.jpg&imgrefurl=http://www.sandisk.com/corporate/media/photos-sd-card.asp&h=937&w=750&sz=486&tbnid=UMjydX0Z3I0J:&tbnh=147&tbnw=117&hl=zh-TW&start=4&prev=/images%3Fq%3Dsd%26svnum%3D10%26hl%3Dzh-TW%26lr%3D%26sa%3DGhttp://images.google.com.hk/imgres?imgurl=http://www.sandisk.com/download/photos/retail/sd-2gb.jpg&imgrefurl=http://www.sandisk.com/corporate/media/photos-sd-card.asp&h=937&w=750&sz=486&tbnid=UMjydX0Z3I0J:&tbnh=147&tbnw=117&hl=zh-TW&start=4&prev=/images%3Fq%3Dsd%26svnum%3D10%26hl%3Dzh-TW%26lr%3D%26sa%3DG7/28/2019 Vhdl Sound
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VHDL8 Practical example v2b
Memory is like a tall buildingAddress cannot change; content (data) can change
Address content, e.g. A 32K-byte RAM
16-bit Address
(H=Hex)
8-bit content (data)
7FFF H 35H
7FFF H 23H
0ACD H 24H
0001 H 32H
0000 H 2BH
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VHDL8 Practical example v2b
How a computer works?
Program is in memory
CPU
programcounter (16
bit) [PC]:
Keeps
track of
program
location
16-bitAddress
(H=Hex)
8-bitcontent
(data)
7FFF H 35
7FFF H 23
0ACD H 24
0001 H 32
0000 H 2B
(goto0ACD)
After power up
PC=0000H
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VHDL8 Practical example v2b
A simple program in memory After power up, first instruction is in 0000H
An exampleAddress
(H=Hex)
8-bit machine
code
instructions
(Hex)
8-bit content
(data)
0AC3 25 Instruction j+3
0AC2 72 Instruction j+2
0AC1 3B Instruction j+1
0AC0 24 Instruction j
0001 xx Instruction 2
0000 2B Instruction 1
Register
A
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VHDL8 Practical example v2b
Program to find 2+3=?
Address(H=Hex)
8-bit content (data)
0AC3 Send content of 0AC2 to output port0AC2 (so this is the answer for 2+3 =5)
0AC1 Add 2 to Reg .A and save in next
location
0AC0 Save 3 into Reg. A
0001
0000 Goto address 0AC0 H
Register
A
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VHDL8 Practical example v2b
CPU and Static memory (SRAM) interface
Exercise: show the address space of the CPU
and memory
Data bus is bi-directional DIN,DOUT are using the
same bus (D0-D7)
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VHDL8 Practical example v2b
Exercises 8.1
A) What is the address space for an
address bus of 24 bits?
B) How many address bits are required for
a space of 4G bytes?
C) Why do most computers use 8-bit as
the bit length of an address?
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VHDL8 Practical example v2b
Memory read/write
Timing diagrams
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VHDL8 Practical example v2b
CPU and Static memory (SRAM)
read (from SRAM to CPU) timing
Figure 1
8-bit data bus
Address bus
/CS
/OE
Data
bus(DOUT)
T0 T1 T2Data bus is bi-directional
DIN,DOUT are using the
same bus (D0-D7)
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VHDL8 Practical example v2b
CPU and Static memory (SRAM) write (from CPU to
SRAM) timing
Address bus
/CS
/WE
Data
bus(DIN)Figure 2
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VHDL8 Practical example v2b
Exercises 8.2A
(A): Redesign the CPU/SRAM interfaces
circuit in figure 1 so that the address-range
is 8000-FFFFH instead of 0000-7FFFH.
Data bus is bi-directional DIN,DOUT are using the
same bus (D0-D7)
Figure 1
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VHDL8 Practical example v2b
Exercises 8.2B
(B): Redesign the CPU/SRAM interface
circuit in figure 1 to add another SRAM to
make the system occupies the whole
0000-FFFFH address-range.
Data bus is bi-directional DIN,DOUT are using the
same bus (D0-D7)
Figure 1
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VHDL8 Practical example v2b
How to read timing diagrams ?
part1 Valid bus
High-to-low, low-to-high uncertain regions
A14-
A0valid
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VHDL8 Practical example v2b
How to read timing diagrams?
part2 Float (High-Z) to uncertain then valid
T0 T1 T2
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VHDL8 Practical example v2b
Exercise8.3 , explain this timing
diagram
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VHDL8 Practical example v2b
Address decoding
From
http://www.myconfinedspace.com/2008/09/30/ddr-1x-ssd-ram-drive/
Usually a large memory
storage requires multiple
memory chips
We need a memory decoder
to control these chips
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VHDL8 Practical example v2b
Exercises 8.4
A CPU supports 128K-byte (has address
pin A0-A16 = 17 pins, so 217=128K) of
memory area.
Exercise: How many 32K-SRAMs do we need?
E i 8
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VHDL8 Practical example v2b
Exercise 8.5a
Address lines:
A15, A16
A0-A14
/WR/RD
Data bus
D0-D7
Address decoder /CS0
/CS1
/CS2
/CS3
A0,A1
A CPU supports 128K-byte (has address pin A0-A16 =17 pins, so 2^17=128K) of memory area. We need an
address decoder to enable the (/CS) input of eachSRAM. Complete the following diagram.
32K
SRAM2
/CS
A0-A14/OE
/RD
D0-D7
32K
SRAM3
/CS
A0-A14/OE
/RD
D0-D7
32K
SRAM4
/CS
A0-A14/OE
/RD
D0-D7
32K
SRAM1
/CS
A0-A14
/OE
/RD
D0-D7
E i 8 5b :Memory decode for a
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VHDL8 Practical example v2b
Exercise 8.5b :Memory decode for a
system with 128K-byte size using four
32-byte RAM chips , fill in the blanks.
A16,A15,..A0
(17 bits) Address range
( 5 hex.)
Range size
0 0xxx xxxx xxxx xxxx 0 0000 - 0 7FFF H
32K
0 1xxx xxxx xxxx xxxx 0 8000 - 0 FFFFH
32K
_ _xxx xxxx xxxx xxxx 1 0000 - 1 7FFFH
__ K
1 1xxx xxxx xxxx xxxx
_ ____ - _ ____H 32K
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VHDL8 Practical example v2b
Exercise 8.5c: fill in the address decoder truth
table
A16 ,A15 /CS0 /CS1 /CS2 /CS3
0 0
0 1
1 0
1 1
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VHDL8 Practical example v2b
Address decode rules
Decode the upper address lines using a
decoder.
Connect lower address lines directly to
memory devices.
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VHDL8 Practical example v2b
Exercise 8.6
Fill in the modes (in, out, inout or buffer) ofthe input/output signal.
SRAM
(memory)
CPU
address
lines (A0-
A16)
data lines
(D0-D7)
/CS,/OE and
/WE lines
Exercise 8 7
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VHDL8 Practical example v2b
Exercise 8.7
Referring to thefigure, what
would happen if
/RD of the CPU
(connected to/OE) goes up
before the data
valid region
occurs?
Exercise 8 8 :
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VHDL8 Practical example v2b
Exercise 8.8 : Referring to the
Figure,
if tAS=0ns,
twc=100ns,tCW=
80ns, give
comments onthe limits of tAW,
tWP and tDW..
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VHDL8 Practical example v2b
Part 2
The sound recorder
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VHDL8 Practical example v2b
The sound recorder
Overall diagram
Xilinx based
hardware
ramResetRec
Play
Digital to analog
converter
amplifier
Analog to digital
converterMicrophone
amplifier microphone
DA0->7
AD0->7
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VHDL8 Practical example v2b
Memory (32K) interface
entity record1_entity is port ( --user inputs
clk40k_in: in STD_LOGIC;
reset, rec, play : in std_logic;
-- for ram only
bar_we27: buffer STD_LOGIC; bar_ram_we27: out STD_LOGIC; -- pin 27 w
bar_ram_ce20: out STD_LOGIC; -- pin20 /E
bar_ram_oe22: out STD_LOGIC; --pin22 G
ram_address_buf: buffer std_logic_vector(14 downto 0); --A0->14
ram_data_inout: inout std_logic_vector(7 downto 0); --DQ0->7 da_data_out: buffer std_logic_vector(7 downto 0); --DA0->7
ad_data_in: in std_logic_vector(7 downto 0) ); --AD0->7
end;
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VHDL8 Practical example v2b
Static memory (SRAM 32Kbytes)
data pins
Diagrams are obtained from data sheet of M28256 at http://www.st.com/
Datasheet of a 64K Static Ramhttp://docs-europe.electrocomponents.com/webdocs/0b7b/0900766b80b7b917.pdf
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VHDL8 Practical example v2b
M28256 Memory read timing
diagrams
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VHDL8 Practical example v2b
M28256 Write mode timing
diagram
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VHDL8 Practical example v2b
Flow diagram
S_init
s_rec_address_change :rec01
s_rec_we_ce_down :rec02
s_rec_read_from_ad_to_reg1 :rec03
s_rec_writeto_from_reg1_to_ram :rec04
s_play_address_change: play01
s_play_ce_oe_down : play02
s_play_read_from ram_to_reg1 :play03
s_play_write_from reg1_to_da :play04
Rec=0 Play=0
ram_address_buf =all1
ram_address_buf =not all1ram_address_buf =all1
ram_address_buf =not all1
Reset =0
Reset
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VHDL8 Practical example v2b
architecture
architecture record1_arch of record1_entity is
-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (s_init,
s_rec_address_change, s_rec_we_ce_down,
s_rec_read_from_da_to_reg1, s_rec_writeto_da_ram,
s_play_address_change,s_play_ce_oe_down,
s_play_read_in_reg1, s_play_writeto_da );
signal state_ram1: Sreg0_type;
signal data_reg1: std_logic_vector (7 downto 0); -- temporary storage
begin
-- concurrent signal assignement
--diagram ACTIONS;
--clock divider
--to be continued ;
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VHDL8 Practical example v2b
Process() and state s_init
process (CLK40k_in,reset)
begin
if reset = '0' then --loop count
state_ram1
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VHDL8 Practical example v2b
State s_rec_address_change
------------ sound record cycle starts here, ram write cyclewhen s_rec_address_change => -- state: rec01
bar_ram_we27
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VHDL8 Practical example v2b
States: s_rec_read_from_da_to_reg1 and
s_rec_we_ce_down
when s_rec_read_from_da_to_reg1=> --state: rec02 bar_ram_we27
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VHDL8 Practical example v2b
States: s_rec_writeto_da_ram,
listen to what have recorded (optional)
when s_rec_writeto_da_ram=> -- state: rec04 bar_ram_we27
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VHDL8 Practical example v2b
State: s_play_address_change
--------- sound playback state machine
cycle starts here
To be done by students in the lab.
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VHDL8 Practical example v2b
Conclusion
Showed how to make a single board
sound recorder by VHDL
Can be modified for digital camera, mp3
player etc.