Post on 10-Feb-2017
transcript
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Electrical and Computer Engineering Network for Computational Nanotechnology
Birck Nanotechnology Center Purdue University, West Lafayette, Indiana USA
Lundstrom 5.3.2013 nanoHUB.org
EDS Mini-colloquium, Mexico City, May 3, 2014
From Lilienfeld to Landauer:
Understanding the nanoscale transistor:
Mark Lundstrom
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history of the field-effect transistor
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Lilienfeld, 1926 Heil, 1934
concept
Atalla and Dawon Kahng Bell Labs, 1959
demonstration
Intel IEDM, 2012
22 nm FinFET
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NMOS-II
Hewlett-Packard Journal, Nov. 1977
NMOS II: 5 microns = 5000 nm
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Moore’s Law
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http://en.wikipedia.org/wiki/Moore's_law Micro- electronics
Nano- electronics
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MOSFET IV characteristic
(Courtesy, Shuji Ikeda, ATDF, Dec. 2007) S
D
G
circuit
symbol
gate-voltage controlled resistor
gate-voltage controlled
current source
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MOSFET IV: low VDS
gate-voltage controlled resistor
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velocity saturation
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104 105
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MOSFET IV: velocity saturation
(Courtesy, Shuji Ikeda, ATDF, Dec. 2007)
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textbook MOSFET model
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(Courtesy, Shuji Ikeda, ATDF, Dec. 2007)
gate-voltage controlled resistor
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gate-voltage controlled current source
Velo
city
(cm
/s)
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carrier transport nanoscale MOSFETs
D. Frank, S. Laux, and M. Fischetti, Int. Electron Dev. Mtg., Dec., 1992.
quasi-ballistic
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Ener
gy
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MOSFET: IV (2-piece approximation)
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current = charge times velocity
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1) Low VDS:
2) High VDS:
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model for ID(VG, VD)
If we can make the average velocity go smoothly from the low VD to the high VD limit, then we will have a smooth model for ID(VG, VD).
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drain voltage dependent average velocity
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empirical saturation function
✓
✓
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“MIT Virtual Source” model
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Only a few device-specific input parameters to this model: 1)
2)
3)
4)
5)
The parameter, β, is empirically adjusted to fit the IV. Typically, β ≈ 1.4 – 1.8 for both N- and P-MOSFETs.
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MIT Virtual Source Model
32 nm technology
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questions
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1) Why does the traditional MOSFET model (based on transport physics that is not valid at the nanoscale) continue to describe the IV characteristics of nano-MOSFETs?
2) How does the velocity saturate in a ballistic or quasi-ballistic MOSFET?
3) What is the meaning of the “apparent mobility” and the “injection velocity.”
4) What will happen below 10 nm?
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outline
1) Introduction
2) The MOSFET as a barrier-controlled device 3) The MOSFET as a nano-device
4) Connecting the traditional and Landauer models
5) What will happen below 10 nm?
6) Summary
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energy band diagrams
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source drain
SiO
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silicon
S G D
(Texas Instruments, ~ 2000)
electron potential energy vs. position
the transistor as a barrier controlled device
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source drain channel
low gate voltage
VD = VS = 0
the transistor as a barrier controlled device
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low gate voltage
source drain channel
high drain voltage
the transistor as a barrier controlled device
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high gate voltage
source high drain voltage
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how transistors work
2007 N-MOSFET
(Courtesy, Shuji Ikeda, ATDF, Dec. 2007)
E.O. Johnson, “The IGFET: A Bipolar Transistor in Disguise,” RCA Review, 1973
understanding MOSFET IV characteristics
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electrostatics + transport
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semiclassical transport in nanoscale MOSFETs
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Velo
city
(cm
/s)
D. Frank, S. Laux, and M. Fischetti, Int. Electron Dev. Mtg., Dec., 1992.
Ener
gy
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quantum transport
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L = 10 nm
n(x, E)
nanoMOS (www.nanoHUB.org)
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outline
1) Introduction
2) The MOSFET as a barrier-controlled device
3) The MOSFET as a nano-device 4) Connecting the traditional and Landauer models
5) What will happen below 10 nm?
6) Summary
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Landauer approach to transport
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gate
nano-device
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the DD equation for the 21st Century
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nano-device
bulk semiconductor
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“Lessons from Nanoscience”
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http://nanohub.org/topics/LessonsfromNanoscience
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i) small drain bias
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nano-device
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small drain bias
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ballistic transport and quantized conductance
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W --> B. J. van Wees, et al. Phys. Rev. Lett. 60, 848–851,1988.
1) conductance is quantized 2) upper limit to conductance
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ii) large drain bias
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nano-device
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ballistic MOSFET: linear region
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near-equilibrium
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linear region with MB statistics
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ballistic MOSFET: linear region
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near-equilibrium
ballistic MOSFET: saturated region
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saturated region with MB statistics
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ballistic MOSFET:
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the ballistic IV (Boltzmann statistics)
K. Natori, JAP, 76, 4879, 1994.
ballistic channel resistance
ballistic on-current
“velocity saturation”
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velocity saturation in a ballistic MOSFET
Increasing VDS
-10 -5 0 5 10
ΕΧ vs. x for VGS = 0.5V 1) 2)
3) 4)
(Numerical simulations of an L = 10 nm double gate Si MOSFET from J.-H. Rhew and M.S. Lundstrom, Solid-State Electron., 46, 1899, 2002)
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“velocity overshoot”
Lundstrom Fall 2012
Velo
city
(cm
/s)
D. Frank, S. Laux, and M. Fischetti, Int. Electron Dev. Mtg., Dec., 1992.
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comparison with experiment: Silicon
A. Majumdar, Z. B. Ren, S. J. Koester, and W. Haensch, "Undoped-Body Extremely Thin SOI MOSFETs With Back Gates," IEEE Transactions on Electron Devices, 56, pp. 2270-2276, 2009. Device characterization and simulation: Himadri Pal and Yang Liu, Purdue, 2010.
• Si MOSFETs deliver > one-half of the ballistic on-current. (Similar for the past 15 years.)
• MOSFETs operate closer to the ballistic limit under high VDS.
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comparison with experiment: InGaAs HEMTs
Jesus del Alamo group (MIT)
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scattering and transmission
X X X
λ0 is the mean-free-path for backscattering
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the quasi-ballistic MOSFET
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on-current and transmission
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the quasi-ballistic MOSFET
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scattering under high VDS
low VDS
high VDS
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outline
1) Introduction
2) The MOSFET as a barrier-controlled device
3) The MOSFET as a nano-device
4) Connecting the traditional and Landauer models 5) What will happen below 10 nm?
6) Summary
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MIT VS Model: why does it work?
32 nm technology
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connection to traditional model (low VDS)
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connection to traditional model (high VDS)
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the MOSFET as a BJT
‘bottleneck’ “collector”
“base”
E.O. Johnson, “The IGFET: A Bipolar Transistor in Disguise,” RCA Review, 1973
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Landauer VS model
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outline
1) Introduction
2) The MOSFET as a barrier-controlled device
3) The MOSFET as a nano-device
4) Connecting the traditional and Landauer models
5) What will happen below 10 nm? 6) Summary
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limits to barrier control: quantum tunneling
from M. Luisier, ETH Zurich / Purdue
1) 2)
3) 4)
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5 nm MOSFETs?
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Unpublished results from Saumitra Mehrotra, G. Klimeck group, Purdue University.
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outline
1) Introduction
2) The MOSFET as a barrier-controlled device
3) The MOSFET as a nano-device
4) Connecting the traditional and Landauer models
5) What will happen below 10 nm?
6) Summary
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top of the barrier / VS model
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under strong control of gate with weak influence of the drain
For large VDS, most of the additional voltage drop occurs on the drain end of the channel.
In a “well-tempered” MOSFET, the height of the energy barrier is mostly controlled by the gate voltage and only weakly controlled by the drain voltage.
Current is controlled by a bottleneck near the beginning of the channel
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the MIT VS model: Why does it work?
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summary
• Understanding MOSFETs means understanding electrostatics and transport.
• The Landauer approach provides a clear, physical approach to transport at the nanoscale.
• 10 nm and below is still uncharted territory.
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questions
For more information, take a nanoHUB-U short course: “Nanoscale transistors” on nanoHUB-U https://nanohub.org/groups/u/self_paced_nanoscale_transistors
This talk will be available soon at: www.nanoHUB.org