Post on 30-Apr-2018
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EE141EE141-- Spring 2005Spring 2005Digital Integrated Digital Integrated CircuitsCircuits
Lecture 26Lecture 26Semiconductor MemorySemiconductor Memory
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Administrative StuffAdministrative StuffHomework 9 posts tomorrow
just for practice. No need to turn in.Poster presentations next Th. 1:30-5:30pm BWRC
Sign up for a 10-min time slot (office door 511 Cory) Poster template on web-site.
Last lecture on Tu – Invited talk by Dr. Stefan Rusu (Intel)
A Perspective of Digital ICs in the Nanoscale Era Final Exam: Fr. May 13!
3106 Etcheverry, 5-8pmHKN review today. Your feedback is important!
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BWRCBWRC
Berkeley Wireless Research Center2108 Allston Way, Suite 200Berkeley, CA 94704-1698The Berkeley Wireless Research Center is located at the SE corner of Shattuck and Allston Way above Eddie Bauer....across the street from the Central Berkeley BART station. Enter on the Allston side of the building.Ring the button to enter.
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MemoryMemory
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MOS NAND ROMMOS NAND ROM
All word lines high by default with exception of selected row
WL [0]
WL [1]
WL [2]
WL [3]
VDDPull-up devices
BL[3]BL[2]BL[1]BL [0]
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MOS NAND ROM LayoutMOS NAND ROM Layout
No contact to VDD or GND necessary;
Loss in performance compared to NOR ROMdrastically reduced cell size
Polysilicon
Diffusion
Metal1 on Diffusion
Cell (8λ x 7λ)
Programmming usingthe Metal-1 Layer Only
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NAND ROM LayoutNAND ROM LayoutCell (5λ x 6λ)
Polysilicon
Threshold-alteringimplant
Metal1 on Diffusion
Programmming usingImplants Only
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Equivalent Transient Model for MOS NOR ROMEquivalent Transient Model for MOS NOR ROM
Word line parasiticsWire capacitance and gate capacitanceWire resistance (polysilicon)
Bit line parasiticsResistance not dominant (metal)Drain and Gate-Drain capacitance
Model for NOR ROM VDD
Cbitrword
cword
WL
BL
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Equivalent Transient Model for MOS NAND ROMEquivalent Transient Model for MOS NAND ROM
Word line parasiticsSimilar to NOR ROM
Bit line parasiticsResistance of cascaded transistors dominatesDrain/Source and complete gate capacitance
Model for NAND ROMVDD
CL
rword
cword
cbit
rbit
WL
BL
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PrechargedPrecharged MOS NOR ROMMOS NOR ROM
PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.
WL [0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Precharge devices
BL [2] BL [3]
GND
pref
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NonNon--Volatile MemoriesVolatile MemoriesThe FloatingThe Floating--gate transistor (FAMOS)gate transistor (FAMOS)
Floating gate
Source
Substrate
Gate
Drain
n+ n+_p
tox
tox
Device cross-section Schematic symbol
G
S
D
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FloatingFloating--Gate Transistor ProgrammingGate Transistor Programming
0 V
2 5 V 0 V
DS
Removing programming voltage leaves charge trapped
5 V
2 2.5 V 5 V
DS
Programming results inhigher VT.
20 V
10 V 5 V 20 V
DS
Avalanche injection
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A “ProgrammableA “Programmable--Threshold” TransistorThreshold” Transistor
“ 0” -state “ 1” -state
DVT
VWL VGS
“ON ”
“OFF”
ID
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FLOTOX EEPROMFLOTOX EEPROMFloating gate
Source
Substratep
Gate
Drain
n1 n1
FLOTOX transistor Fowler-Nordheim I-V characteristic
20–30 nm
10 nm
-10 V10 V
I
VGD
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EEPROM CellEEPROM Cell
WL
BL
VDD
Absolute threshold controlis hardUnprogrammed transistor might be depletion
2 transistor cell
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Flash EEPROMFlash EEPROM
Control gate
erasure
p-substrate
Floating gate
Thin tunneling oxide
n1 source n1 drainprogramming
Many other options …
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CrossCross--sections of NVM cellssections of NVM cells
EPROMFlashCourtesy Intel
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Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――EraseErase
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Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――WriteWrite
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Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――ReadRead
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NAND Flash MemoryNAND Flash Memory
Unit Cell
Word line(poly)
Source line(Diff. Layer)
Courtesy Toshiba
GateONO
FGGateOxide
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NAND Flash MemoryNAND Flash Memory
Word linesSelect transistor
Bit line contact Source line contact
Active area
STI
Courtesy Toshiba
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ReadRead--Write Memories (RAM)Write Memories (RAM)STATIC (SRAM)
DYNAMIC (DRAM)
Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential
Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended
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66--transistor CMOS SRAM Cell transistor CMOS SRAM Cell
WL
BL
VDD
M5M6
M4
M1
M2
M3
BL
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CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)WL
BL
VDD
M 5M 6
M 4
M1 VDDVDD VDD
BL
Q = 1Q = 0
Cbit Cbit
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CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)
00
0.2
0.4
0.6
0.8
1
1.2
0.5
V o l t a g e r i s e [ V ]
1 1.2 1.5 2Cell Ratio (CR)
2.5 3
Vol
tage
Ris
e (V
)
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CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write)
BL = 1 BL = 0
Q = 0Q = 1
M1
M4
M5
M6
VDD
VDD
WL
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CMOS SRAM Analysis (Write)CMOS SRAM Analysis (Write)
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6T6T--SRAM SRAM —— Layout Layout VDD
GND
WL
BLBL
M1 M3
M4M2
M5 M6
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ResistanceResistance--load SRAM Cellload SRAM Cell
Static power dissipation -- Want RL largeBit lines precharged to VDD to address tp problem
M3
RL RLVDD
WL
Q Q
M1 M2
M4
BL BL
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33--Transistor DRAM CellTransistor DRAM Cell
No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn
WWL
BL1
M1 X
M3
M2
CS
BL2
RWL
VDD
VDD 2 VT
DVVDD 2 VTBL 2
BL 1
X
RWL
WWL
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3T3T--DRAM DRAM —— LayoutLayout
BL2 BL1 GND
RWL
WWL
M3
M2
M1
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11--Transistor DRAM CellTransistor DRAM Cell
Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
∆V BL VPRE– VBIT VPRE–CS
CS CBL+------------= =V
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DRAM Cell ObservationsDRAM Cell Observations1T DRAM requires a sense amplifier for each bit line, due
to charge redistribution read-out.DRAM memory cells are single ended in contrast to
SRAM cells.The read-out of the 1T DRAM cell is destructive; read
and refresh operations are necessary for correct operation.
Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD
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Sense Amp OperationSense Amp Operation
DV(1)
V(1)
V(0)t
VPRE
VBL
Sense amp activatedWord line activated
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11--T DRAM CellT DRAM Cell
Uses Polysilicon-Diffusion CapacitanceExpensive in Area
M1 wordline
Diffusedbit line
Polysilicongate
Polysiliconplate
Capacitor
Cross-section Layout
Metal word line
Poly
SiO2
Field Oxiden+ n+
Inversion layerinduced byplate bias
Poly
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SEM of polySEM of poly--diffusion capacitor 1Tdiffusion capacitor 1T--DRAMDRAM
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Advanced 1T DRAM CellsAdvanced 1T DRAM Cells
Cell Plate Si
Capacitor Insulator
Storage Node Poly
2nd Field Oxide
Refilling Poly
Si Substrate
Trench Cell Stacked-capacitor Cell
Capacitor dielectric layerCell plateWord line
Insulating Layer
IsolationTransfer gateStorage electrode
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EE 141 SummaryEE 141 SummaryDigital CMOS design is kicking and wellSome major challenges down the road:
CostPower consumptionRobustnessComplexity
Some new circuit solutions and design methodologies are bound to emergeAdditional interesting material:
Implementation Strategies for Digital Ics – Ch. 8, Inserts E, F.
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That’s all FolksThat’s all Folks
Thanks for the fun semester.And … good luck in your future endeavors!