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Design Metrics

EE141EE141-- Spring 2004Spring 2004Lecture 3Lecture 3

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Last LecturesLast Lectures

Moore’s lawChallenges in digital IC design in the next decade.Manufacturing process

TodayDesign metrics

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AdministriviaAdministrivia

If you have not signed-in on the class roster, please do so after the lecture.Problems?

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Design MetricsDesign Metrics

How to evaluate performance of a digital circuit (gate, block, …)?

CostReliabilityScalabilitySpeed (delay, operating frequency) Power dissipationEnergy to perform a function

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Cost of Integrated CircuitsCost of Integrated Circuits

NRE (non-recurrent engineering) costsdesign time and effort, mask generationone-time cost factor

Recurrent costssilicon processing, packaging, testproportional to volumeproportional to chip area

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NRE Cost is IncreasingNRE Cost is Increasing

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Die CostDie Cost

Single die

Wafer

From http://www.amd.com

Going up to 12” (30cm)

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G. Moore, ISSCC 2003

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Cost per TransistorCost per Transistor

0.00000010.0000001

0.0000010.000001

0.000010.00001

0.00010.0001

0.0010.001

0.010.01

0.10.111

19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012

cost: cost: ¢¢--perper--transistortransistor

Fabrication capital cost per transistor (Moore’s law)

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YieldYield

%100per wafer chips ofnumber Total

per wafer chips good of No. ×=Y

yield Dieper wafer Dies

costWafer cost Die

×=

( )area die2

diameterwafer

area die

diameter/2wafer per wafer Dies

2

××π−×π=

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DefectsDefects

α−⎟⎠⎞

⎜⎝⎛

α×+= area dieareaunit per defects

1yield die

α is approximately 3

4area) (die cost die f=

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Some Examples (1994)Some Examples (1994)

$4179%402961.5$15000.803Pentium

$27213%482561.6$17000.703Super Sparc

$14919%532341.2$15000.703DEC Alpha

$7327%661961.0$13000.803HP PA 7100

$5328%1151211.3$17000.804Power PC 601

$1254%181811.0$12000.803486 DX2

$471%360431.0$9000.902386DX

Die cost

YieldDies/wafer

Area mm2

Def./ cm2

Wafer cost

Line width

Metal layers

Chip

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ReliabilityReliability――Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuits

i(t)

Inductive coupling Capacitive coupling Power and groundnoise

v(t) VDD

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DC OperationDC OperationVoltage Transfer CharacteristicVoltage Transfer Characteristic

V(x)

V(y)

VOH

VOL

VM

VOHVOL

fV(y)=V(x)

Switching Threshold

Nominal Voltage Levels

VOH = f(VOL)VOL = f(VOH)VM = f(VM)

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Mapping between analog and digital signalsMapping between analog and digital signals

VIL

VIH

Vin

Slope = -1

Slope = -1

V OL

V OH

Vout

“ 0” VOL

VIL

VIH

VOH

UndefinedRegion

“ 1”

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Definition of Noise MarginsDefinition of Noise Margins

Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate Output Gate Input

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Noise BudgetNoise Budget

Allocates gross noise margin to expected sources of noiseSources: supply noise, cross talk, interference, offsetDifferentiate between fixed and proportional noise sources

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Key Reliability PropertiesKey Reliability Properties

Absolute noise margin values are deceptivea floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)

Noise immunity is the more important metric –the capability to suppress noise sourcesKey metrics: Noise transfer functions, Output

impedance of the driver and input impedance of the receiver;

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Regenerative PropertyRegenerative Property

v0

v1

v3

finv(v)

f(v)

v3

out

v2 in

Regenerative Non-Regenerativev2

v1

f(v)

finv(v)

v3

out

v0 in

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Regenerative PropertyRegenerative Property

A chain of inverters

v0 v1 v2 v3 v4 v5 v6

2

V (

Vol

t)

4

v0

v1v2

t (nsec)0

�1

1

3

5

6 8 10Simulated response

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FanFan--in and Fanin and Fan--outout

N

Fan-out N Fan-in M

M

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The Ideal GateThe Ideal Gate

Ri = ∞Ro = 0Fanout = ∞NMH = NML = VDD/2g = ∞

V in

V out

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An OldAn Old--time Invertertime Inverter

NMH

Vin (V)

V

o ut

(V )

NML

VM

0.0

1.0

2.0

3.0

4.0

5.0

1.0 2.0 3.0 4.0 5.0

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Delay DefinitionsDelay Definitions

Vout

tf

tpHL tpLH

tr

t

Vin

t

90%

10%

50%

50%

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Ring OscillatorRing Oscillator

v0 v1 v5

v1 v2v0 v3 v4 v5

T = 2 × tp × N

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A FirstA First--Order RC NetworkOrder RC Network

vout

vin C

R

tp = ln (2) τ = 0.69 RC

Important model – matches delay of inverter

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Power DissipationPower Dissipation

Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)

Peak power: Ppeak = Vsupplyipeak

Average power:

( )∫ ∫+ +

==Tt

t

Tt

t supplysupply

ave dttiT

Vdttp

TP )(

1

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Energy and EnergyEnergy and Energy--DelayDelay

Power-Delay Product (PDP) =

E = Energy per operation = Pav × tp

Energy-Delay Product (EDP) =

quality metric of gate = E × tp

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A FirstA First--Order RC NetworkOrder RC Network

E0 1→ P t( )dt

0

T

∫ Vdd isupply t( )dt

0

T

∫ Vdd CLdVout0

Vdd

∫ CL Vdd• 2= = = =

Ecap Pcap t( )dt

0

T

∫ Vouticap t( )dt

0

T

∫ CLVoutdVout0

Vdd

∫12---C

LVdd• 2= = = =

vout

vin CL

R

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Next LectureNext Lecture

A First Glance at an Inverter