EE141 1 EE141 1 EE141-S04 EE141 EE141- Spring 2004 Spring 2004 Digital Integrated Digital Integrated Circuits Circuits Lecture 28 Lecture 28 Semiconductor Memory Semiconductor Memory EE141 2 EE141-S04 Administrative Stuff Administrative Stuff Homework 10 posted – just for practice. No need to turn in. Poster presentations tomorrow. No lecture. Sign up for time slot (office door of Prof. Rabaey). Poster template on web-site. Last lecture on Th – overview of future trends in digital IC design. Project 2 + Final discussion. Also HKN review. Your feedback is important!
Transcript
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EE141EE141-- Spring 2004Spring 2004Digital Integrated Digital Integrated CircuitsCircuits
Homework 10 posted – just for practice. No need to turn in.Poster presentations tomorrow. No lecture. Sign up for time slot (office door of Prof. Rabaey). Poster template on web-site.Last lecture on Th – overview of future trends in digital IC design. Project 2 + Final discussion. Also HKN review. Your feedback is important!
Advantages:Advantages:1. Shorter wires within blocks1. Shorter wires within blocks2. Block address activates only 1 block => power savings2. Block address activates only 1 block => power savings
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Block Diagram of 4 Block Diagram of 4 MbitMbit SRAMSRAM
Subglobalrow decoder
Global row decoder
Subglobalrow decoder
Block 30
Block 31
128 K Array Block 0
Block 1
Clockgenerator
CS, WEbuffer
I/Obuffer
Y-addressbuffer
X-addressbuffer
x1/x4controller
Z-addressbuffer
X-addressbuffer
Predecoder and block selectorBit line load
Transfer gateColumn decoder
Sense amplifier and write driverLocal row decoder
[Hirose90]
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ReadRead--Only Memory CellsOnly Memory Cells
WL
BL
WL
BL
1WL
BL
WL
BL
WL
BL
0
VDD
WL
BL
GND
Diode ROM MOS ROM 1 MOS ROM 2
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MOS OR ROMMOS OR ROM
WL[0]
VDD
BL[0]
WL[1]
WL[2]
WL[3]
Vbias
BL[1]
Pull-down loads
BL[2] BL[3]
VDD
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MOS NOR ROMMOS NOR ROM
WL[0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Pull-up devices
BL [2] BL [3]
GND
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MOS NOR ROM LayoutMOS NOR ROM Layout
Programmming using theActive Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (9.5λ x 7λ)
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MOS NOR ROM LayoutMOS NOR ROM Layout
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (11λ x 7λ)
Programmming usingthe Contact Layer Only
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MOS NAND ROMMOS NAND ROM
All word lines high by default with exception of selected row
WL [0]
WL [1]
WL [2]
WL [3]
VDD
Pull-up devices
BL [3]BL [2]BL [1]BL [0]
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MOS NAND ROM LayoutMOS NAND ROM Layout
No contact to VDD or GND necessary;
Loss in performance compared to NOR ROM
drastically reduced cell size
Polysilicon
Diffusion
Metal1 on Diffusion
Cell (8λ x 7λ)
Programmming usingthe Metal-1 Layer Only
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NAND ROM LayoutNAND ROM LayoutCell (5λ x 6λ)
Polysilicon
Threshold-alteringimplant
Metal1 on Diffusion
Programmming usingImplants Only
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Equivalent Transient Model for MOS NOR ROMEquivalent Transient Model for MOS NOR ROM
Word line parasiticsWire capacitance and gate capacitanceWire resistance (polysilicon)
Bit line parasiticsResistance not dominant (metal)Drain and Gate-Drain capacitance
Model for NOR ROM VDD
Cbit
rword
cword
WL
BL
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Equivalent Transient Model for MOS NAND ROMEquivalent Transient Model for MOS NAND ROM
Word line parasiticsSimilar to NOR ROM
Bit line parasiticsResistance of cascaded transistors dominatesDrain/Source and complete gate capacitance
Model for NAND ROMVDD
CL
rword
cword
cbit
rbit
WL
BL
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PrechargedPrecharged MOS NOR ROMMOS NOR ROM
PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.
Static power dissipation -- Want RL largeBit lines precharged to VDD to address tp problem
M3
RL RL
VDD
WL
Q Q
M1 M2
M4
BL BL
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33--Transistor DRAM CellTransistor DRAM Cell
No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn
WWL
BL1
M1 X
M3
M2
CS
BL2
RWL
VDD
VDD 2 VT
DVVDD 2 VTBL 2
BL 1
X
RWL
WWL
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3T3T--DRAM DRAM —— LayoutLayout
BL2 BL1 GND
RWL
WWL
M3
M2
M1
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11--Transistor DRAM CellTransistor DRAM Cell
Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
∆V BL VPRE– VBIT VPRE–CS
CS CBL+------------= =V
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DRAM Cell ObservationsDRAM Cell Observations1T DRAM requires a sense amplifier for each bit line, due
to charge redistribution read-out.DRAM memory cells are single ended in contrast to
SRAM cells.The read-out of the 1T DRAM cell is destructive; read
and refresh operations are necessary for correct operation.
Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD
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Sense Amp OperationSense Amp Operation
DV(1)
V(1)
V(0)
t
VPRE
VBL
Sense amp activatedWord line activated
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11--T DRAM CellT DRAM Cell
Uses Polysilicon-Diffusion Capacitance
Expensive in Area
M1 wordline
Diffusedbit line
Polysilicongate
Polysiliconplate
Capacitor
Cross-section Layout
Metal word line
Poly
SiO2
Field Oxiden+ n+
Inversion layerinduced byplate bias
Poly
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SEM of polySEM of poly--diffusion capacitor 1Tdiffusion capacitor 1T--DRAMDRAM
