ESD Protection Circuits: Basics to nano-metric ASICsee.sharif.edu/~adic/Lecture_ESD_40.pdf · 1 ESD...

transcript

ESD Protection Circuits: Basics to nano-metric ASICs

Manoj SachdevUniversity of Waterloo

msachdev@ece.uwaterloo.ca

September 2007

OutlineGroup IntroductionESD BasicsBasic ESD Protection CircuitsNano-metric ESD ChallengeESD circuits for nano-metric regime

Group Introduction5 PhDs, 2 masters and 2 PDFs

Applied, industrially driven researchGenerous funding levels

Core strengths in circuit design, testing, quality and reliability

Group: Low Power ResearchDriven by low power signal processing & bio-implantable applications Research focus

Active power reduction, clocking strategiesDynamic voltage scaling architecture for portable app.Leakage power reduction: Investigation of RBB effectiveness with scaling

Group: High Performance CircuitsDriven by high speed arithmetic circuits (Adders, register files, ALU), and CDRsResearch focus

To build timing diagnostics into multi-GHz ALUsLeakage and active power reductionClock de-skewingThermal issues in high performance circuits

Group: Memory ResearchDriven by embedded SRAMs and Soft Error RobustnessResearch Focus

SRAM cell stability & ckttechniques for detectionLow power embedded SRAMsSoft Error Robust memories & flip-flopsError Correction Circuit’s for soft error mitigation

Group: ESD ResearchDriven by reducing chip failures due to ESDResearch Focus

ESD strategies for multiple supply domainsESD protection circuits for High speed I/OsFast response ESD protection circuits

OutlineGroup IntroductionESD BasicsBasic ESD Protection CircuitsNano-metric ESD Challenge ESD circuits for nano-metric regime

ESD Basics :Motivation

Electrostatic Discharge (ESD) is responsible for up to 70% of failures in semiconductor industryAn ESD event creates high currents and electric fields in semiconductor devices

High currents may lead to thermal runawayHigh electric fields cause dielectric breakdown

ESD BasicsWhen two dissimilar materials are separated an ESD charge may develop Caused by the removal of electrons from surface atoms of materialsFactors

Magnitude of static chargeContact qualityRate of separation

Human Body Model (HBM)

A BR Rb=1.5k

Cb=100pFV

Mimics the human touching of the Device Under Test (DUT)Voltages as high as 10kV can be developedHBM modeled by series resistance (Rb = 1.5kΩ) and capacitance (Cb = 100pF)

Machine Model (MM)

A BR 0.5uH

200pFV

Represents the damage caused by charged machine touching the DUTVoltages as high as 100-500V can be generatedMM is modeled by capacitance (C = 200pF) and series inductance of machine (0.μ5H)

Charge Device Model (CDM)

Discharge event between charged DUT and grounded conductorModeled by Capacitor (Cap) in series with DUTTotal Capacitance (Cap) is dependant on Device, package impedance

ESD Stress Comparison

HBM rise time ~ 2-10ns, decay time 130-170nsCDM very high amplitude , occurs for 500ps-1000ps

CDM failures on rise due to automated manufacturing

Negative ESD with respect to VSS

(NS-mode)

Zapping ModesPositive ESD with respect to VSS

(PS-mode)

Zapping ModesPositive ESD with respect to VDD

(PD-mode)

Negative ESD with respect to VDD

(ND-mode)

HBM / MM / CDM TestersHBM/MM/CDM testers apply ESD stress to the DUTMagnitude/polarity of the stress set by the userTest can be destructive

Results in pass or fail

The device fails when leakage is increased significantly

ICMS-700 HBM/MM tester

TLP TesterTransmission Line Pulse (TLP) is becoming popular

Measures I-V characteristic of the DUT Non-destructive

Programmable current pulse of 100ns are applied to the DUT2nd breakdown current determines the ESD robustness

Barth 4002 TLP tester

ESD Protection MethodsSnapback-based

Turn on before oxide breakdown Minimum parasitics

Non-snapback-basedTrigger and conduct during the whole ESD eventDo not trigger under normal power-up

Diode Under ESD ConditionsForward biased:

Low trigger voltageLow on resistance

Reverse biased:High trigger voltageHigh on resistance

MOS Under ESD ConditionsHas a parasitic bipolar transistor

Avalanche breakdown gives Igen and Isub

When Vbase = 0.7V, npn turns on SnapbackWhen I(drain) = It2 , npn can be destroyed

n+ n+Igen

IsubVbase

Snapback Protection: MOSFETMOSFET is used in Grounded- Gate configuration (GGNMOS)

Substrate and Gate triggering is often needed

I/OPAD

VDDPAD

VSSPAD

PreDriver

Buffer stageESD ProtectionDevice

GGNMOS

ESD Protection Wish ListVt1 < Oxide breakdown

To trigger NMOS before oxide breaks downVt2 > Vt1

To ensure uniform triggering of all fingersVh > VDD

To enhance latch-up immunity (VDD + 10%)It2 as high as possible

Increase current carrying capability ↑ESD

A GGNMOS cannot meet all the above requirements for contemporary technologies

SCR Under ESD ConditionsSCR is a pnpn device

In CMOS the junctions are: p+-nwell-psub-n+

n-well

n+ p+n+p+I/O

VDDPAD

VSSPAD

PreDriver

Buffer stageESD ProtectionDevice

SCR CharacteristicAvalanche breakdown of nwell-psub ↑ IRnwell and IRpsub

When VBE reaches 0.7V, npn (or pnp) turns onPositive feedback turns on the pnp (or npn) Snapback

Rp-sub

Rn-well

I(anode)

V(anode)

(Vt1, It1)

(Vh, Ih)

(Vt2, It2)

ESD Devices: ComparisonProtection level:

SCR and FB diode are the best

Trigger voltage:FB Diode is too lowNMOS is the bestSCR should be modified

Holding voltage: NMOS is ok SCR should be modified

Figure of meritProtection level/Capacitance

Non-Snapback Protection: ClampsESD event V(1) rises turning on M0

RCCC + inverters should keep M0 “on” to discharge all ESD energyAdvantages

Protect against different zapping conditions

DisadvantagesCan turn on during normal power-up

ESD event:tr: between 100ps and 60nsduration: up to 1μs

Regular power-up:In millisecond range

Hot plug app. power-upas low as 1μs

Challenges with Scaling

Breakdown Voltage of CMOS devices is decreasingTraditional ESD structures not scaling with technology scaling

Larger ULSI, thinner metallization, shallower junctionsIncreasingly difficult to provide low impedance, low capacitancedischarge path

0 20 40 60 80 100 120

Current (A)

Time (ns)

Challenges: Charged Device Model

Lower Technologies (90nm , 65nm) damage occur at lower voltagesTraditional ESD circuits trigger slower

High speed chips larger package decoupling capHigher CDM discharge current!!

CDM failures on rise due to automated manufacturing

Challenges: Multiple Supply Domains

Multiple supply domains in SoC’sPin to pin ESD protection requirementMultiple zapping modes

Challenge to Overcome Noise Coupling & ground-bouncing issues between analog & digital supplies

Challenges: Multiple Chip Module

Resistance of the path can be very high (Multiple Chip Module)Minimization of Parasitic Capacitance attributed to the High Speed I/O’s due to ESD Circuit

Strategy – Device SimulationMOS models, circuit simulators are not designed to handle snapback behaviorESD circuits are designed with device simulators (Medici and Sequoia)

Device cross section is created in the simulatorQuasi-DC simulation predicts DC characteristic, i.e. Vt1and Vh

It2 is estimated using thermal simulation and monitoring maximum temperature of the ESD protection device

Design Steps1. Calibrate the device simulator with the

desired technology Junction depth and substrate doping are available from technology documents

2. Verify the technology model by simulating a MOS transistor

Trial and error is used to achieve the typical I(on), Vth, current gain and

3. Draw the cross-section of the ESD device

Design Example #1 – LVTSCR

Mesh of the Low-Voltage-Triggered SCR (LVTSCR) created in MediciReducing grid spacing increases accuracy and simulation time

p-typen-typecontactoxide

Snapback Protection RequirementsReduce first breakdown voltage

SCR has higher Vt1 compared to MOSVt1 of both MOS and SCR are higher than oxide breakdown voltage

Latch-up immunityVery important in SCR devices

Increasing second breakdown currentSCR has higher It2 per width

Reducing parasitic capacitanceSCR provides protection with less capacitance

I(anode)

V(anode)

(Vt1, It1)

(Vh, Ih)

(Vt2, It2)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

V(Gate) (V)

Gate-Coupling↑Vgs ↑Isub npn triggers faster ↓Vt1

For higher Vgs (strong inversion region): impact ionization is decreased Vt1 increases

0 0.25 0.5 0.75 1 1.25 1.5

V(Sub) (V)

Substrate Triggering↑Vsub Transistor triggers with lower ↓Vt1

GST-LVTSCRSCR is modified by adding a gate electrode to reduce Vt1(LVTSCR)MG provides gate triggering

Can be as small as 5μm

MS provides substrate triggeringSimulation results

Vt1 reduces from 12V to 4.85V

Semenov et. al., Microelectronics Reliability, 2005

GST-LVTSCR (Measurement)GST-LVTSCR was fabricated in 0.13μm CMOS technologyTLP measurements

Vt1 = 5VIt2 = 1.8A

HBM measurementsDevice passes ±3kV 0.00E+00

5.00E-01

1.00E+00

1.50E+00

2.00E+00

2.50E+00

0 2 4 6 8 10

Voltage (V)

Current (A)

1.00E-12 1.00E-10 1.00E-08 1.00E-06 1.00E-04

Leakage (A)

TLP I-VTLP Leakage

Example #2 – Increasing VhIn holding region both Q1 and Q2 are in saturationSCRVh= VEB1+ VCE2(sat)

High Vh SCR (RE is added)Vh = VEB1+ VCE(sat) + REI1Vh = VEB1 + VCE(sat)+ VEB1RE/Rn-well

RE↑ → Vh↑

Cathode

Rn-well

Rp-sub

n+ p+ n+ p+

n-well

Anode CathodeRE

Semenov et. al., ISQED, 2004

0.0001

10 5 10 15 20 25

V(anode) (V)

Log I(anode) (A)

0.00E+00

2.00E-02

4.00E-02

6.00E-02

8.00E-02

1.00E-01

1.20E-01

0 1 2 3 4 5 6 7 8

V(anode) (V)

I(anode) (A)

LVTSCRHighVhMOSHighVhDiode

Increasing Holding VoltageSimulation results

Applied to SCRVh is increased without an increase in Vt1

RE is implemented with diode and MOS and applied to LVTSCRTLP Measurement results

Vh is increased from 2.29V to 3.49V and 4.55VIncrease in Vt1 is less than 8%

Example #3 – ESD Clamps

To solve false triggering, the triggering circuit is divided into rise time detector and delay elementTime constant is approximately 40nsDelay of the delay element should be more than 1μs

Thyristor-Based Clamp

CMOS thyristor is used to create the delay elementRCCC= 40nsR1 to keep M0 off under normal conditions

Rise Time Detector

Delay Element

Hossein et. al., ESD Symposium 2007

Circuit-Level SimulationThe clamp is circuit simulated with 2kV HBM stressV(3) shows that clamp turns off after 1μsPeak voltage of the clamp is less than 6V

0E+0 3E-7 5E-7 8E-7 1E-6 1E-6 2E-6

Time (s)

Device-Level SimulationDevice simulation is done with SequoiaPeak temperature is in transistor M0

During a 2kV HBM stress Tmax of the clamp is 375KHot-spot is in the gate-drain boundary

MeasurementsClamp was fabricated in 0.18μm technologyHBM test

Clamp passes 3kV stress and fails at 3.5kV

TLP testLeakage current is 7nASecond breakdown current is 1.8A

0 5 10 15

Voltage (V)

1E-09 0.0000001 0.00001 0.001 0.1 10Log Leakage (A)

TLP I-VTLP Leakage

Example #4 – CML Driver Design

Two stage 3Gbps CML driver is designed in 0.13μm CMOS tech.Bias of the driver is provided through an external resistor

Diff. Input 400mV

Diff. Output 800mV

Rise/fall time 150ps

Jitter 1ps

Measured Results

0 100 200 300 400 500 600 700

ESD Capacitance (fF)

Jitter (fs)

Vout tr Jitter

CML (simulation) 850mV 116ps 229fs

CML+MOS (measured) 500mV 315ps 3.7ps

CML+LVTSCR (measured) 700mV 148ps 700fs

Beyond CESD=150fF jitter increases significantly

Both Protection schemes achieved 3kV HBM protection

Hossein et. al., CICC 2007

ConclusionESD remains major cause of chip failures

ESD affects entire manufacturing from devices systems

Significant challenges for nano-metric technologiesESD circuit design is an art

Device simulator are useful in design process

AcknowledgementHelp of Hossein Sarbishaei, SumanjitSingh, and Oleg Semenov is greatly appreciated for this presentation

ESD Protection Circuits: Basics to nano-metric ASICsee.sharif.edu/~adic/Lecture_ESD_40.pdf · 1 ESD...

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