FPGA Introduction - International Centre for Theoretical...

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2384-10

ICTP Latin-American Advanced Course on FPGADesign for Scientific Instrumentation

SISTERNA Cristian Alejandro

19 November - 7 December, 2012

Universidad Nacional de San Juan Instituto de Investigaciones Antisismicas

Av. San Martin 1290 - Oeste 5400 San Juan ARGENTINA

FPGA Introduction

FPGA INTRODUCTION

ICTP 2012 - CUBA

Cristian AlejandroSisterna, MScUniversidad Nacional San Juan Argentina

Agenda2

Introduction FPGA ArchitectureConfiguration and routing cellsBasic slice resources available in Xilinx FPGAsBasic I/O resources available in Xilinx FPGAsClocking resources

Memory blocks and distributed memoryMultipliers and DSP blocksRouting

Spartan 6, Virtex 6, Virtex 7FPGA Configuration

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Introduction

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PLDs Evolution

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Programmable

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FPGA: Competitive Market

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Altera Inc. Actel Corp.

Lucent Technology Philips Semiconductors

Intel Corp. Motorola Semiconductors

QuickLogic Cypress

Lattice Semiconductors AMD

Vantis Xilinx

FPGA20002012

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FPGA Architecture

FPGA? – What is it?

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Programmable Logic, Interconnections and RoutingProgrammable in System (ISP)Dedicated Blocks:

MemoryClock ControlDSP blocksEmbedded processor(s)Gigabits serial transmission/receptionEthernet controllerMemory controllers

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FPGA? – What is it? (cont.)

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Up to1200 I/O More than 40 I/O standards. Single ended, DifferentialsMore than 40.000 Flips-Flops and Look-Up-Tables (LUTs)Soft-Coded Processors, 8051, ARM3PLLs and DLLs available (2-12) per device. Up to 550MHz.Programmable output impedanceDedicated hard coded blocks:

ProcessorsPCI E interfaceGigabit transceivers

Dedicated DSP blocksMemory blocks

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FPGA Architecture

columns

RAM MemoryBlock

DSPBlock

I/O Block

FPGA Architecture (cont.)

I/O Block

DSPBlock

RAM MemoryRAM

ComInterfaces

Spartan-6 FPGA Architecture

Block RAM

BUFGBUFIO

Memory Controller

PCIe Endpoint

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Spartan 3 InternalView

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General Altera FPGA Architecture

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FPGA Silicon View

Resources Available in an FPGA

ASMBL™ Column-Based

Architecture

500 MHz SmartRAM™BRAM/FIFO

0.6 - 11.1 GbpsRocketIO™

SelectIO withChipSync™Technology:

- 1 Gbps LVDS- 600 Mbps SE

500 MHz Xtreme DSP™ Slice

500 MHzXesium™ Clocking

IntegratedSystem Monitor

IntegratedTri-Mode

Ethernet MACCores

Integrated 450 MHzPowerPC Cores

4th GenerationAdvanced Logic

Xilinx FPGA Architecture Alignment

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Virtex-6 FPGAs Spartan-6 FPGAs

150K Logic Cell

Device

760K Logic Cell

Device

Common Resources

3.3 Volt compatible I/O

Hardened Memory Controllers

LUT-6 CLB

DSP Slices

BlockRAM

HSS Transceivers*

Parallel I/O FIFO Logic

System Monitor

Tri-mode EMAC

PCIe® Interface

High-performance Clocking

Basic Architecture 17Cristian Sisterna

Xilinx FPGAs Overview

FPGA Configuration and Routing Cell

FPGA Logic Configuration Options

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FPGA Routing Options

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Logic and Routing Configuration

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Configuration & Routing Bits 110101011101010010001

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FPGA Configuration Cells

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Tipos de CeldasSRAMAnti-FuseFlashFlash y SRAM

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FPGA Cell Comparison

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SRAM Anti_fuse Flash

Technology LatestOne or Two

generation behindOne or Two

generation behind

Speed Slower Faster Slower

Volatility yes No No

Power Poor Better Medium

Density Good Best Medium

Radiation Tolerant Poor Best Medium

External Configuration Yes No No

Cell size 1 1/10 1/7

Reprogrammable Yes No Si

Instant-On No Yes Yes

Security Poor Very Good Very Good

Config. Transistors 6 Transistors Tiny 2 transistors

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FPGA Architecture: Big Fight

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Who is the big winner of thisfight?????

In general the FPGA arquitecture is similar among the largestvendors. Even though each vendor states the its FPGA is the

BEST. . .

The final user

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FPGA Architecture

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The FPGAs from Xilinx are divided in

Spartan 2-3-6 Virtex 2-2P-4-5-6

High performanceExpensive

Good performanceGreat relation price/performance

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CLB SLICEs

Spartan 3 – FPGA

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S3 - Configurable Logic Block (CLB)

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S3 - CLB – Actual Internal View

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S3 - CLB – Main Logic

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Two LUTsTow flip-flopsFour outputs

Two combinationalsTwo registered

Control Input for FFs

I/O carry chain

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S3 – Half Slice Detailed View

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S3 - Look-Up Table

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A B C D Z0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1

. . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

The LUT configuration is not responsibility of the designer

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S3 - CLB Register Elements

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S3 - CLB – Carry Logic

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S3 - Different Type of SLICEs

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CLB Internal

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S6 - SLICEs

SLICEM: Full sliceLUT can be used for logic and memory/SRLHas wide multiplexers and carry chain

SLICEL: Logic and arithmetic onlyLUT can only be used for logic (not memory)Has wide multiplexers and carry chain

SLICEX: Logic onlyLUT can only be used for logic (not memory)No wide multiplexers or carry chain

SLICEX

SLICEM

SLICEX

SLICEL

S6 – SLICEs39

8 Registers

Carry Logic

Wide Function Muxes

Distributed RAM / SRL logic

SliceM (25%) SliceL (25%) SliceX (50%)

8 Registers

Carry Logic

Wide Function Muxes

Optimized for Logic

8 Registers

S6 - SLICE

Basic Architecture 40

Four LUTsEight storage elements

Four flip-flop/latches

Four flip-flops

F7MUX and F8MUXConnects LUT outputs to create wide functions

Output can drive the flip-flop/latches

Carry chain (Slice0 only)Connected to the LUTs and the four flip-flop/latches

LUT/RAM/SRL

S6 - 6-Input LUT with Dual Output

6-input LUT can be two 5-input LUTs with common inputsMinimal speed impact toa 6-input LUT

One or two outputs

Any function of six variables or two independent functions of five variables

5-LUTD

A5A4A3A2A1

5-LUTD

A5A4A3A2A1

Configuring LUTs as a Shift Register (SRL)

A[4:0]

Q31 (cascade out)

Shift Register LUT Example

Operation D - NOP must add 17 pipeline stages of 64 bits each1,088 flip-flops (hence 136 slices) or

64 SRLs (hence 16 slices)

20 Cycles

64Operation A

8 Cycles 12 Cycles

Operation B

3 Cycles

Operation C

20 Cycles

Paths are StaticallyBalanced

17 Cycles

Operation D - NOP

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V5 Slice L

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I/O Resources

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Spartan 3I/O Block

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I/O Block

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Spartan 6 I/O Block Diagram

Electrical Resources

Termination

Logical ResourcesIn

IOSERDES

IOLOGIC

IOSERDES

IOLOGIC

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IOSERDESParallel to serial converter (serializer)Serial to parallel converter (De-serializer)

IODELAYSelectable fine-grained delay

SDR and DDR resources

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S6 - FPGA Supports 40+ Standards

Each input can be 3.3 V compatibleLVCMOS (3.3 V, 2.5 V, 1.8 V, 1.5 V, and 1.2 V)LVCMOS_JEDECLVPECL (3.3 V, 2.5 V)PCII2C*

HSTL (1.8 V, 1.5 V; Classes I, II, III, IV)DIFF_HSTL_I, DIFF_HSTL_I_18DIFF_HSTL_II*

SSTL (2.5 V, 1.8 V; Classes I, II)DIFF_SSTL_I, DIFF_SSTL18_IDIFF_SSTL_II*

LVDS, Bus LVDSRSDS_25 (point-to-point)

S6 - FPGA I/O Bank Structure

All I/Os are on the edges of the chipI/Os are grouped into banks

30 ~ 83 I/O per banks

Eight clock pins per edge

Common VCCO, VREFRestricts mixture of standards in one bank

The differential driver is only available in Bank0 and Bank2

Differential receiver is available in all banks

On-chip termination is available in all banks

BANK 0

BANK 2

BANK 4 BANK 5

BANK 3 BANK 1

BANK 0

BANK 2

BANK 3 BANK 1

Chip View(LX45/T and Smaller)

Chip View(LX100/T and Larger)

I/O Resources

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Digital Controlled Impedance (DCI)Drive StrenghtSlew RateBus Hold (Bus keeper)Pull-up/Pull-downDifferential TerminationIODelay (V5, V6, V7)

FixedVariable

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FPGA Memory

FPGA Block RAM (BRAM) Features

18 kb sizeWith multiple size configuration

Multiple configuration optionsTrue dual-port, simple dual-port, single-port

Two independent ports access common dataIndividual address, clock, write enable, clock enable

Independent widths for each port

Byte-write enable Different modes:

Write firstRead first, then write No change

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Dual-Port BRAM

18k Memory

S3 - Memory Block (BRAM)

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BRAMs Usages

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BRAM Configuration Size

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16.383

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BRAM Forced Location

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LOC <instance> = RAMB16_X#Y#

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Location Constraint:

SLICEM Used as Distributed SelectRAM Memory

SinglePort

DualPort

SimpleDual Port

QuadPort

32x2 32x4 32x6 32x8 64x1 64x2 64x3 64x4

128x1128x2 256x1

32x2D32x4D64x1D64x2D

128x1D

32x6SDP 64x3SDP

32x2Q64x1Q

Uses the same storage that is used for the look-up table function

Synchronous write, asynchronous readCan be converted to synchronous read using the flip-flops available in the slice

Various configurations Single port

One LUT6 = 64x1 or 32x2 RAM

Cascadable up to 256x1 RAM

Dual port (D)1 read / write port + 1 read-only port

Simple dual port (SDP)1 write-only port + 1 read-only port

Quad-port (Q)1 read / write port + 3 read-only ports

S6 - Memory Controller59

Only low cost FPGA with a “hard” memory controller

Guaranteed memory interface performance providingReduced engineering & board design time

DDR, DDR2, DDR3 & LP DDR support

Up to 12.8Mbps bandwidth for each memory controller

Automatic calibration features

Multiport structure for user interfaceSix 32-bit programmable ports from fabric

Controller interface to 4, 8 or 16 bit memories devicesce

EEPROM

Spartan-6Spartan-6

DRAMDDRDDR2DDR3LP DDR

DRAMDRAMDDRDDR2DDR3LP DDR

FPGA Multipliers and DSP Blocks

Different Multipliers/DSP Blocks

S3 – Multiplier Locations

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Spartan 3 - Multiplier

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P = A x B

36 = 18 x 18

Pipelining (optional)

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Virtex 5/6 - Conexiones del DSP48E64

Virtex 5/6 - Bloque DSP48E65

FPGA Routing

Routing

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Transistor de Paso

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Routing (cont.)

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Routing Delay Report

Routing (cont.)

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Routing (cont.)

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Clock Resources

S3 – Digital Clock Manager

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S3 – Digital Clock Manager (cont.)

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CLK2X180

CLKDIV

CLKFX180

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DCM Purposes

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Elimintating clock skewClock phase shifting

VariableFixed

Multiply and Divide input clock, to generate a new frequencyDuty cycle 50%Rebuffer clock input

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DCM Aplication

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Skew eliminationon internal clocksignals

Skewelimination onexternalclock signal

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Dedicated Clokc Routing

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HGFEDCBA

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DedicatedClockRouting: Real application

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Spartan-6 FPGA I/O Clock Network

Special clock network dedicated to I/O logical resourcesIndependent of global clock resourcesSpeeds up to 1 GHz

Multiple sources for clocking I/O logicBUFIO2: for high-speed dedicated I/O clock signalsBUFPLL: for clocks driven by the PLL in the CMT

CMT PLL

IO bank

IOLOGIC

P NBUFIO2

BUFPLLP N P N

IOLOGIC IOLOGIC IOLOGIC

Spartan-6 FPGA Clock Management Tile (CMT)

dcm1_clkout<9:0>

dcm2_clkout<9:0>10

pll_clkout<5:0>6

CLKOUT<5:0>

10CLKIN

CLKFB DCM

Clocks from BUFG

CLKOUT<9:0>

GCLK Inputs

Feedback clocks from BUFIO2FB

Spartan 6 - Virtex 6 - Virtex 7

Virtex® Product & Process Evolution82

Virtex

Virtex-E

Virtex-II

Virtex-II Pro

Virtex-4

Virtex-5

1st Generation 2nd Generation 3rd Generation 4th Generationn 5th Generation 6th Generation

220-nm

180-nm

150-nm

130-nm

Virtex-6

Virtex-6 and Spartan-6 FPGA Sub-Families

Spartan-6LX FPGA

Spartan-6LXT FPGA

Virtex-6 LXT FPGA

Virtex-6SXT FPGA

Virtex-6HXT FPGA

• Lowest Cost Logic • Lowest Cost Logic • Low-Cost Serial Connectivity

• High Logic Density • High-Speed Serial

Connectivity

• High Logic Density• High-Speed Serial

Connectivity• Enhanced DSP

• High Logic Density • Ultra High-Speed Serial

Connectivity

LogicBlock RAMDSPParallel I/OSerial I/O

Virtex-6 CXT FPGA

• Upto 3.75Gbps serial connectivity and corresponding logic performance

Virtex 784

Common elements enable easy IP reuse for quickdesign portability across all 7 series families

Design scalability from low-cost to high-performance

Expanded eco-system support

Quickest TTM

Precise, Low Jitter ClockingMMCMs

Logic FabricLUT-6 CLB

DSP EnginesDSP48E1 Slices

On-Chip Memory36Kbit/18Kbit Block RAM

Enhanced ConnectivityPCIe® Interface Blocks

Hi-perf. Parallel I/O ConnectivitySelectIO™ Technology

Artix™-7 FPGA

Kintex™-7 FPGA

Virtex®-7 FPGA

Hi-performance Serial I//O ConnectivityTransceiver Technology

The Xilinx 7 Series FPGAs

Industry’s Lowest Power and First Unified Architecture Spanning Low-Cost to Ultra High-End applications

Three new device families with breakthrough innovations in power efficiency, performance-capacity and price-performance

FPGA Configuration

FPGA Master

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FPGA Slave

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FPGA Introduction - International Centre for Theoretical...

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