Post on 22-Dec-2015
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Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France
LHCb upgrade meeting
Tests tools for Analog and Digital parts
Typical acquisition sequenceBasic DAQ tests and resultsTools to test Analog part First tests with AX FPGATools to test A3PE FPGA (SSO & SSI)Conclusion : next steps
Caceres ThierryDuarte Olivier
Olivier Duarte / Thierry Caceres
Reminder : Typical acquisition sequence
LHCb upgrade meeting 2December 16th 2011
Write Acq Register
(PC)
Beginning L0
sequence
Time
DiscretTime
1 2 3
1 2 3
Beginning latency delay
End of latency delay
1 2 3
Recording data in RAM (512 points) FIFO full
Data readout by USB
25 ns to 65,5µs
Trigger Generator
PC write start sequence bit of Acquisition (Acq) Register. Beginning of L0 sequence. Each trigger pulse involve pulse shape. At the end of the latency delay recording 512 points of data (Max). At the end of the record the system write one “end of acquisition”bit in the
Acq_Register . The PC scrutinize the Acq_Register, when the “end of acquisition” is high the PC
download data with the USB interface.
Write Data Ctrl
Olivier Duarte / Thierry Caceres
Reminder : Basic DAQ tests
LHCb upgrade meeting 3
Soft Trigger(or external)
Trigger generator block
Latency Trigger Generator
Pulses Generator
Spy FIFO (8 ADC channels) (96x512)
ADC_0(12 bits)
ADC_1(12 bits)
ADC_2(12 bits)
ADC_3(12 bits)
ADC_4(12 bits)
ADC_5(12 bits)
ADC_6(12 bits)
ADC_7(12 bits)
Fixed value (Firmware) FromCounters
Trig
ADC_7 [11]
USB Interface
Wr
Clk 40 Mhz
Latency Wr FIFOWr FIFO
All times adjustable
DiscretTime
Fixed data, counter and pulse stand in for ADC data from analog mezzanine
December 16th 2011
A3PE
Olivier Duarte / Thierry Caceres
Tools to test Analog part
LHCb upgrade meeting 4
SPY_FIFO
ANALOG_PULSE_FIFO
ClkUSB
PATTERN_FIFO
setup_register[8]
96 96
9696
96
96
88
setup_register[9]
setup_register[9]
{Add 0x1C}
96
A3PE
RDWR
RDWR
RDWR
(96 x 512)
(8 x 512)
(96 x 512)
{Add 0x1F}
{Add 0x06}0
1
0
1
Buffer_FIFOs(12x8) USB wr
0
1
USB_data
USB_data 8
8
USBdata
8
8
8 x 12bits
96
8
USB_data
96
December 16th 2011
12 bit ADC data from Analog Mezzanine
(x8)
Analog Pulse ( 1 per ADC Channels)
Clk 40 Mhz
Wr : USBRd : USB or 40 Mhz
Wr : USB or 40 MhzRd : USB
Wr : USBRd : USB or 40 Mhz
ADC emulation SPY data
Trigger for Analog
FIFO pattern Generate digital
signals Check FPGA
computations
SPY FIFO storage of processing results
ANALOG PULSE FIFOgenerate trigger of analog pulses
Olivier Duarte / Thierry Caceres
First tests with AX FPGA
LHCb upgrade meeting 5
A3PE FPGA AX FPGA
Rd/WrRegister D Q
Clk
D Q
Clk
D Q
Clk
D Q
Clk
QD
ClkQ
D
Clk
Rd/WrRegister
USB interface
Bank
0Ba
nk 1
Bank
1Ba
nk 0
Delay Chip
I2C
A3PE_Clk
A3PE_Clk
A3PE_Clk
AX_Clk
AX_Clk ??
A3PE_Clk
AX_Clk
1,5v < VccIOB_Var < +2,5v)
VccIOB_Var
VccIOB_Var
32
32
Reminder : ProASIC3 families are based on nonvolatile flash technology
=> reprogrammable The latest antifuse FPGA family
=> Not reprogrammable
A3PE
AX
Idea : RAM pattern to test the A3PE IOs functioning by exchanging data between the 2 FPGA (SSO and SSI)
December 16th 2011
Olivier Duarte / Thierry Caceres
Tools to test A3PE FPGA (SSO & SSI)
LHCb upgrade meeting 6
From_AX_FIFO
A3PE
CLK_1
ClkUSBTo_AX_FIFO
setup_register[10]
32
32
32 32
3232
setup_register[11]
RegUSB32
3232 32
32
32
_q3 AX500
setup_register[11]
32
32
BUSLSBAXTOA3PE
BUSMSBAXTOA3PE
32
32
_q2
_q _q1
{Add 0x1D}(32 x 512)
{Add 0x1E}(32 x 512)
RdWr 0
1
0
1
32
32
Buffer_FIFOs
USB_data
32
8
USB_data 8
32USB_data 8
32
December 16th 2011
WrRd
Idea : RAM pattern to test the A3PE IOs functioning by exchanging data between the 2 FPGA (SSO and SSI)
Wr : USBRd : USB or Clk_1
Wr : USB or Clk_1Rd : USB
USB Rd / Wr the FIFO (To_AX and From_AX).
From Delay Chip
Ctrl. Wr / Rd pattern
Start / Stop and latency missing (not implemented yet)
Sequence: To_AX _FIFO Rd/Wr by USB Start commande Loop on to AX_FIFO until
stop command Programmable latency to
capture data from To_AX_FIFO to FROM_AX_FIFO
Olivier Duarte / Thierry Caceres
Conclusion
LHCb upgrade meeting 7
Digital electronic is ok, several adjustment have been done (Tests with Carlos at LAL in November).
Do you have other needs of firmware to test the analog mezzanine ? ?
Started Production of third mother digital board (ready in Jannuary)
Should we considered a 8 channel prototype FEB for the end of 2012 with GBT ?
Packing is in stand by. Waiting for decision on GBT bandwith.
December 16th 2011
Olivier Duarte / Thierry Caceres LHCb upgrade meeting 8
SPARE
December 16th 2011
Olivier Duarte / Thierry Caceres
Reminder : Basic DAQ tests results
LHCb upgrade meeting 9
Fixed value 456 h (1110)
Fixed value 456 h (1110)
Fixed value ABC h (2748)
Fixed value ABC h (2748)
Not connected FFF h ?
Not connected FFF h ?
Counters
Channel 8[11]
Trigger generator block
2047
4095
December 16th 2011
Olivier Duarte / Thierry Caceres
First tests with AX FPGA
LHCb upgrade meeting 10
AX FPGA
D Q
Clk
D Q
Clk
Bank
1Ba
nk 0
AX_Clk
AX_Clk
1,5v < VccIOB_Var < +2,5v)
VccIOB_Var
VccIOB_Var
32
32
Reminder : ProASIC3 families are based on not volatile flash
technology => reprogrammable
AX is the latest antifuse FPGA family => Not reprogrammable
AX programmation with Silicon Scultor
Olivier Duarte / Thierry Caceres
Clock tree
LHCb upgrade meeting 11