Multilevel Inverter

transcript

ABSTRACT

FPGA Based Hybrid Power Cascaded Multilevel Inverter is an step towards

the introduction of FPGA capabilities in the field of power electronics and in

this project we have tried to utilize the fast switching capability of FPGA on

cascaded multilevel inverter, as FPGA can enhance the functionality of any

multilevel network due to its relatively far better processing speed then any

microcontroller or general microprocessors. FPGA was used for the

mathematical calculations and the mathematically formulated results were

then transformed into the Verilog code so as for the calculations of various

parameters of the inverter circuitry. FPGA was also holding the charge of

controlling the smooth battery charging phenomenon by charging circuitry

having a variable potential showing renewable energy sources at input.

Further more FPGA was used to interact with the LabVIEW where a user

friendly monitoring environment was built for the end user with the help of

block diagram programming.

TABLE OF CONTENTS

SECTION TOPIC PAGE

SECTION1

1.1 1.2 1.3 1.4

1.4.1 1.4.1.1

1.4.2.1 1.4.2.2

1.4.2.3

1.4.3.1 1.4.3.2

INTRODUCTION FPGA IN MODERN POWER ELECTRONICS XILINX SPARTAN3E KIT FPGA IN OUR PROJECT

CONTROLLING OF MULTI LEVEL INVERTER GATE SIGNAL GENERATION VIA FPGA

CONTROLLING OF CHARGE CONTROLLER CIRCUITRY INTRODUCTION CHARGE CONTROLLER CIRCUIT AND

CONTROL STRATEGY SOFTWARE FLOW FOR BATTERY

CHARGING CALCULATION OF PARAMETER AND

INTERFACING WITH LABVIEW CALCULATING PARAMETERS LABVIEW INTERFACING

6-78-91011

15-1920

20-2121-24

26-2728

SECTION 2

2.1 2.1.1 2.1.2

2.2 2.2.1 2.2.2

2.2.2.1

2.2.2.1.1 2.2.2.1.2

2.2.2.2 2.2.2.2.1

2.3.1 2.3.2 2.3.2.1 2.3.2.2

2.4.3 2.4.4

INVERTER

INTRODUCTION MODIFIED SINEWAVE INVERTERS TRUE SINEWAVE INVERTERS

MULTILEVEL INVERTERS ADVANTAGES OF MULTILEVEL INVERTERS GENERAL TOPOLOGIES OF MULTILVEL

INVERTER DIODE CLAMPLED MULTILEVEL

INVERTER ADVANTAGES DISADVANTAGES

CASCADED H-BRIDGE INVERTER ADVANTAGES

DESIGN AND SPECIFICATION OF OUR INVERTER OUR CIRCUIT INTRODUCTION CIRCUIT OPERATION

SWITCH POSTIONS OF CIRCUIT TRANSISTORS USED

REVIEW OF CIRCUIT SIMULATION AND PCB LAYOUT CIRCUIT SIMULATION WITH PWM ON

MULTISIM CIRCUIT SIMULATION WITH COMPARATOR

ON MULTISIM CIRCUIT SIMULATION WITH PIC16F877A CIRCUIT LAYOUT ON ORCAD

29-303030

31-363233

34343536

37383940

SECTION 3

3.1 3.1.1 3.1.2 3.1.2.1

3.1.3 3.1.3.1 3.1.3.2 3.1.3.3 3.1.3.4

CHARGE CONTROLLER

CHARGE CONTROLLER INTRODUCTION OBJECTIVE

SALIENT FEATURES DESIGN OF CHARGE CONTROLLER

DC-AC CONVERTER TRANSFORMER RECTIFIER CIRCUIT REVERSE CURRENT PROTECTION

THE BATTERY BANK CHARGER

45-50454646474849495051

3.2.1 3.3

IMPORTANCE OF CHARGER MAXIMUM POWERPOINT TRACKING

SECTION 4

4.1 4.2 4.3 4.4

4.5 4.6

LABVIEW MONITORING

OBJECTIVE WHAT WE REQUIRED WHAT IS LABVIEW MONITORING REQUIRMENT AND CHALLENGES FOR

LABVIEW BLOCK DIAGRAM ON LABVIEW FRONT PANEL ON LABVIEW

57585961

SERIAL

NUMBERFIGURE NUMBER AND NAME

NUMBER

1. Fig. 1.1 Spartan 3E Development Kit 10

2. Fig.1.2(a) Three level output 12

3. Fig.1.2(b) Five Level Output 12

4. Fig.1.3 Multilevel Inverter Topology for Seven Level 13

5. Fig.1.4 Block Diagram Of Gate Signals 16

6. Fig.1.5 Gate signals with dead Time 17

7. Fig.1.6 Simulation of Gate Signals 19

8. Fig.1.7 Circuit Diagram of the H-Bridge made on Proteus 22

9. Fig.1.8 Transformer with Multiple Tapping 23

10. Fig.1.9 Block Diagram for Charge Controller 24

11. Fig.1.10 Software Flow design 25

12. Fig.1.11 Code For Serial Interfacing written on Verilog 28

13. Fig 2.1 GENERAL H-BRIDGE MULTILEVEL INVERTER 36

14. Fig 2.2 OUR USED CMI FROM IEEE RESEARCH PAPER 38

15. Fig 2.3 TABLE OF SWITCH POSTIONS OF CASCADED 3 STAGE INVERTER 39

16. Fig 2.4 SECTION OF DATA SHEET OF IRF540N 40

17. Fig 2.5 CIRCUIT SIMULATION WITH PWM ON MULTISIM 41

18. Fig 2.6 CIRCUIT SIMULATION WITH COMPARATERS ON MULTISIM 42

19. Fig 2.7 CIRCUIT SIMULATION WITH PIC16F877A ON PROTEUS 43

20. Fig 2.8 CIRCUIT LAYOUT DESIGN ON ORCAD 44

21. Fig.3.1 Block Diagram of the Charge Controller 47

22. Fig.3.2DC-AC conversion by H-Bridge 49

23. Fig.3.3 130w poly crystalline solar module 56

24. Fig 4.1 BLOCK DIAGRAM OF LabVIEW PROGRAMMING 63

25. Fig 4..2 FRONT PANNEL OF LabVIEW PROGRAMMING 64

1.1) INTRODUCTION

The advancements in hardware technology has led to the presence of Field

Programmable Gate Arrays (FPGA) that are large enough to accommodate a

complete system on a single device. These devices are called “system on a

programmable chip” (SOPC). This SOPC design allows designers to place a

numerous number of functions onto a (System On a Programmable Chip) and

to reprogram this chip from the desktop thus reducing engineering costs from

prototyping and testing of new designs.

Before the coming of programmable logic, custom logic circuits were built at

the circuit board level using basic components, or at the logic gate level in

costly application-specific (custom) integrated circuits. The FPGA is an

integrated circuit that contains numerous (64 to over 10,000) identical logic

cells that can be watched as standard components. An Individual logic cell can

independently take any one of the limited set of personalities. The individual

cells are interlinked by a matrix of wires and programmable switches. A

user's design is carried out by specifying the simple logic function for each

cell and selectively closing the switches in the interconnect matrix. The array

of logic cells are interconnected form a fabric of basic building blocks for

logic circuits. Complicated designs are created by fusing these basic blocks to

create the wanted circuit.

For the past decade, Digital Signal Processors (DSP) had been introduced in

Power Electronics Applications providing an essential feature of design reuse

and modified use of previously designed components.

While using the latest components, an algorithm in an FPGA may run with a

sampling frequency of 20MS/s. This offers the chance of utilizing the

switching times of advanced power transistors. Whereas microprocessors can

only count and switch on instruction or interrupt level (interrupt latency),

FPGAs are able to do that on cycle level. As a result, the jitter was scaled

down. The processing of FPGA can provide the signal processing, the

sequence control system, the supervision or the activating of signals at the

same time. That is the reason FPGAs behave as an extraordinary platform for

implementing algorithms, e.g. for inverters, converters or other power

applications. So the motivation behind using a “FPGA” was accelerated due to

the increased functionality, performance and flexibility that these solutions

presented over other approaches to system design.

1.2) FPGA IN MODERN POWER ELECTRONICS

In the modern years digital control methods are becoming the most

widespread solution in modern power electronics applications. The

microprocessors, DSP processor and application specific integrated

circuits (ASIC) are accountable for improved performance of the power

converters . At the same time the design of digitally controlled power

electronics is affected by several problems, such as , software portability,

sampling rate, re-usability, peripheral devices and register settings specific

for each microprocessor. These problems can be alleviated by Field

Programmable Gate Array circuits (FPGA). It does eliminate the code

portability trouble as Verilog hardware description language and several

developing tools are almost device independent. In this project we have

propose a novel FPGA based control algorithm for conventional and

cascaded multilevel inverter, a charge controller and interfacing with

LabVIEW.

It can greatly increment the capacitors charging time and drop-off their

discharging time by putting in low order harmonics to expand the

modulation index range. FPGA controller algorithm has not only a wider

modulation index range but in addition it would support less harmonics,,

low output switching frequency, high conversion efficiency, high output

power quality and only on one chip.

The requirement in Controlling Power Circuits is constantly growing:

lower output voltages with higher currents and lower ripple. With the

assistance of digital controllers, these and other requirements can be

realized by simpler means. Microcontrollers often do not provide enough

computing power. In particular problems will come up when it comes to

controlling various voltages. In accession, errors within a function might

cause the whole controller to collapse. As a effect, supervising functions

are often realized externally. As for non-simultaneously controlling

functional units in the FPGA, this risk does not exist. Supervising

functions can be integrated into FPGA, employing its high computation

power. By means of this, the integration level will be expanded, and the

PCB design will be simplified.

1.3) XILINX SPARTAN-3E FPGA KIT

SPECIFICATIONS

The Spartan 3e board, shown in the Figure.1.1 below, utilizes up to 1 million

gates and contains a large number of I/O’s to facilitate implementation.

Xilinx Devices: Spartan-3E FPGA (XC3S500E-4FG320C)CoolRunner™-II CPLD (XC2C64A-5VQ44C)Platform Flash (XCF04S-VO20C)Clocks: 50 MHz crystal clock oscillator

Memory: 128 Mbit Parallel Flash16 Mbit SPI Flash64 MByte DDR SDRAMConnectors and Interfaces: Ethernet 10/100 PhyJTAG USB downloadTwo 9-pin RS-232 serial portPS/2- style mouse/keyboard port, rotary encoder with push buttonFour slide switchesEight individual LED outputsFour momentary-contact push buttons100-Pin expansion connection ports Three 6-pin expansion connectorsDisplay: 16 character - 2 Line LCD

Fig. 1.1 Spartan 3E Development Ki

1.4) FPGA IN OUR PROJECT

FPGA has become very popular in recent years, it is being used in various

applications where Digital Signal Processing is required. It is being used

for Defense purposes and Image recognition applications.

FPGA and Power Electronics had no relation before but now FPGA has

revolutionized the field of Power Electronics. Its use in modern day Power

Electronics has brought up remarkable flexibilities in Power related

applications.

FPGA is playing a major role in our project, we are using it for :

1) Controlling of Multi level Inverter

2) Controlling of Charge Controller

3) Interfacing With LabView

1.4.1 Controlling Of Multilevel Inverter

Multilevel inverters have been making immense concern in recent

years, particularly in high-powered and power quality applications. They

are beneficial over conventional three-level ones; close to sinusoidal output

waveforms, lower filter size, lower electro-magnetic interference (EMI),

and lower total harmonic distortion (THD) are some of the features

that make it popular among research workers and industries. A multilevel

inverter's output consists of numerous intermediate voltage levels

stepped through. Fig.1.2 shows a phase-output voltage for three-level

and five-level inverters.

Fig.1.2(a) Three level output Fig.1.2(b) Five Level Output

Commonly, there are three basic topologies for multilevel inverters:

neutral point clamped (NPC) or diode clamped, flying capacitor (FC)

or capacitor clamped and cascaded H-bridge (CHB). The most basic

transition processes developed for multilevel inverters are multi carrier

pulse-width modulation (PWM), selective harmonic elimination (SHE),

and spacevector modulation (SVM). In multicarrier PWM, the carriers

can be arranged as follows: phase shifted (PS), phase disposition (PD),

phase opposition disposition (POD), or alternate phase opposition

disposition (A POD) modulations Emersion of field-programmable gate

array (FPGA) technology produced opportunities for its digital execution

in industrial control system. FPGA technology offers shorter design

cycle, much faster computation speed, reduced cost, less-complex

circuitry and convenient application in algorithm modification. FPGA-

based digital controllers have been successfully used in applications

such as PWM inverters, multilevel converters, power-factor correction ,

and electrical-machine control.

Proposed Circuit :

Fig.1.3 Multilevel Inverter Topology

for Seven Level

Fig.1.3 Displays the proposed

Multilevel inverter's

Topology with a RL load,

modified from conventional

full-bridge inverter, this

inverter consists of seven MOSFET switches and three separate DC sources

with a RL load. MOSFETS because of their fast switching nature are being

used for switching purpose at appropriate firing angles, due to this we can

obtain seven different output voltage levels.

In this circuit we have used 7 MOSFETS to generate Seven Voltage Levels at

the output. This is achieved by providing signals to the MOSFETS in a

controlled manner as different combinations of MOSFETS will generate all

the voltage levels respectively. As shown in the Table.1.1 on next page , seven

switch combinations relate to Seven different Voltage Levels. Three Switches

will be operated at one time, switches S2 and S7 remain active for the

positive cycle of the output whereas S3,S4 and S5 determines the voltage

levels from Vdc to 3Vdc respectively. Switches S1 and S6 remain active for

the negative cycle of the output whereas S3,S4 and S5 determines the voltage

levels from –Vdc to -3Vdc respectively.

Table.1.1 Switching Conditions

1.4.1.1 GATE SIGNAL GENERATION VIA FPGA

Control algorithm of the proposed inverter was digitally implemented in

an Xilinx Spartan 3-e board. The Spartan-3E board has Cool runner II

FPGA . Features used on the Spartan-3E board are a 50 MHz oscillator

for clock source, one pushbutton switch for system reset and I/O ports

for gate signals.

Fig.1.4 Block Diagram Of Gate Signals

Fig.1.4 presents the block diagram of a single-phase Gate Signal generator

developed in Xilinx Design Suite. The Xilinx software is the most

comprehensive environment available for a FPGA design. The

implementation of Gate Signal generator was done in Verilog HDL

At first the Sinusoidal signal of 50Hz frequency is taken as reference. The

time period of this frequency was calculated using this formula ; T=1/F,

which came out to be 20ms. From this we find out that the positive half cycle

of the output wave is of 10ms and the negative half cycle is of 10ms.

As the oscillator of our FPGA is of 50Mhz so with this information we find

out that a single Clock Cycle of an FPGA is of 20ns . Our task was to design a

logic with which we can use the clock cycles of our FPGA oscillator and

match it to our requirement of 2ms per Voltage level and keeping in mind the

dead time of 40ns to avoid short circuiting of MOSFETS, which is included in

the 2ms time .

To achieve this task we used the counter logic, If one Clock cycle of our

Oscillator is of 20ns than to make it 2ms we will be counting the cycles for

100,000 times as (20ns*100,000) = 2ms. Out of those 100,000 cycles 999,998

cycles will be for making the switches high and 2 cycles will be used as dead

time in which all transistors will be off to avoid any short circuiting

Conditioning is done in Verilog to check for a Variable name count, and if its

value reaches 999,998 than for the first voltage level output of switches S2,

S7 and S3 are made high and others are made low. All outputs will be set to

low for 2 more cycles to avoid any short circuiting as shown in Fig.1.5. This

process is repeated for all switch combinations.

Fig.1.5 Gate signals with dead Time

This is a part of the program written on Verilog for Gate signals

always @ (posedge clk50)

if(count==1)

q=7'b0100101;

/*operating transistor Q2,Q7 and Q3 for the time period of almost 2ms*/

if(count==99998)

q=7’b0000000;/*to avoid short circuit of transistor*/

if(count==100000)

q=7'b0101001;

/*operating transistor Q2,Q7 and Q4 for the time period of 2ms*/

if(count==199998)

q=7’b0000000;/*to avoid short circuit of transistor*/

if(count==200000)

q=7'b0110001;

Fig.1.6 Simulation of Gate Signals

Figure 1.6 shows the simulation of Verilog Code which was written and

simulated on ModelSim.

1.4.2 CONTROLLING OF CHARGE CONTROLLER

CIRCUITRY

1.4.2.1 Introduction

The main function of a charge controller in a complete PV system is to keep

the battery at maximum attainable charge whilst keeping it safe from

overcharge by the PV Module and from unnecessary discharge by the loads.

While some Solar systems can be sufficiently designed without the usage of

charge control, any system that has irregular loads, user interference, optimum

or Small battery storage (to minimize initial cost) generally requires a battery

charge controller. The controlling strategy or control algorithm of a battery

charge controller specifies the effectualness of battery charging and solar array

utilization, and finally the ability of the system to fulfill the load demands.

Additional features such as warning signals, temperature compensation,

voltage sensing loads and specific algorithms can increase the potential of a

charge controller to preserve the health and prolong the lifetime of a battery,

also providing an indication of operative status to the system caretaker.

Significant roles of battery charge controllers and systems are to:

1. Avoiding the Battery to Overcharge: to restrict the energy provided to the

battery by the PV array when the battery gets full charged.

2. Avoiding the Battery to Over discharge: to unplug the battery from

electrical loads as the battery arrives at low state of charge.

3. Allow for Load Control Functions: to automatically disconnect and connect

an electrical load at an intended time, for Instance running a lighting load from

sundown to sunrise.

General charge controllers do not charge a battery when they Go past a set

point voltage level, and restart charging when battery voltage falls back below

that level. The Charging Technique that we are using is more electronically

advanced, setting charging rates depending upon the battery's voltage level, to

provide charging closer to its maximum electrical capacity. Charge controllers

may also monitor battery temperature to avoid overheating. Our charge

controller systems will display data and will do logging of data to track flow

of electric charges over time.

1.4.2.2 Charge Controller Circuit and Controlling Strategy

The Charge Controller circuit that we are using is divided in different parts

with different operations and controlling strategy using FPGA. Our circuit has

the first part of a H-Bridge Inverter which takes the DC voltages from the

Solar Panel(PV array) and converts it to AC voltages. The H-Bridge is made

up of MOSFETS which are being controlled by signals from FPGA, simple

High and Low signals are given to the MOSFETS to produce an AC signal at

its output as shown in Fig.1.6. below:

Fig.1.7 Circuit Diagram of the H-Bridge made on Proteus

The Output of the H-Bridge is feed to a Transformer with multiple tapping on

its Secondary side as shown in Fig.1.7. The Transformer is made in such a

sense that voltages from 18V to 10V are being step downed to 13.8V which is

the charging voltage for a battery. On different tapping 13.8V is appearing for

different range of input voltages provided by the PV array.

Fig.1.8 Transformer with Multiple Tapping

There will be a switch controlled by FPGA on the output of all the Secondary

Windings which will be checking for which switch to be on with respect to the

input voltage. A FPGA program will check for the input voltages from 18V to

10V and respectively activate the switch. The Secondary side of the

transformer is connected to a bridge rectifier followed by a filter and then it is

connected to the Batteries. The Voltage from the battery is sensed using a

voltage divider and is given to an 8-bit ADC which will provide the required

digital values to the FPGA for calculation of parameters such as Threshold

Voltage, Vrms, Distortion Factor, Harmonic Distortion using Verilog

Programming.

Fig.1.9 Block

Diagram for Charge Controller

Fig.1.8 shows the charge controller circuit block diagram. FPGA is an

intelligent Digital Signal Processor. It will continuously monitor the input

voltages of the Solar Panel and the battery output voltage and makes ON and

OFF the switches which are placed at the secondary tapping of transformer.

The output of voltage and circuit is given to ADC (analog to digital converter)

IC, which is converting analog voltage into digital values. FPGA shall read

digital values at ADC output and will take the required action to charge the

battery voltage. In also continuously show the battery voltage on LCD display.

1.4.2.3 Software Flow for Battery Charging

The program for FPGA is written in Verilog HDL language for FPGA. The

flow chart is explained below.

Fig.1.10 Software Flow design

System first initializes and will monitor the battery voltage and will show it on

the LCD display panel. When battery voltage is below some lower threshold

voltage it will measure the amount of voltage of input PV cell and the battery

voltage and it will activate the switch on secondary tapping of the transformer

so that battery will get charged. When battery voltage is at the upper threshold

voltage it will make OFF the switch so that charging will be stopped.

This system uses an algorithm which enhances the efficiency of the system.

LCD display has made it more user friendly to display voltages. FPGA

implementation improves its efficiency, speed, reliability and user

friendliness.

1.4.3 Calculation of Parameters and Interfacing with

LabVIEW

1.4.3.1 Calculating Parameters :

The Output Voltage is sensed from the battery connected to the charge

controller and is being used to calculate parameters which are :

RMS Voltage

Total Harmonic Distortion(THD)

Fundamental Voltage

Distortion Factor

These parameters are calculated through Verilog Programming by using

mathematical formulae and functions. Below is the part of the code written in

Verilog to calculate these parameters.

always @ (*)beginout1=c1;out2=c2;out3=c3;out4=c4;out5=c5;vm1=v1*3/255*4; /*conversion of potential*/vm2=v2*3/255*4; /*conversion of potential*/vm3=v3*3/255*4; /*conversion of potential*/

vrms=(2*(vm1*vm1)+(2*(vm1+vm2)*(vm1+vm2))+((vm1+m2+vm3)*(vm1+vm2+vm3)))/5; /*calculation of vrms through mathematically driven formula*/

for(n=1;n<=99;n=n+2)beginif(n==1) /*calculation of fundamental voltage*/x_def=n*3.142/5;x_def2=2*n*3.142/5;x_def3=3*n*3.142/5;x_def4=4*n*3.142/5;x_def5=n*3.142;bn=(2/3142)*1000*(1/n)*(-(vm1*out1)+(vm1)-((vm1+vm2)*out2)+((vm1+vm2)*out1)-((vm1+vm2+vm3)*out3)+((vm1+vm2+vm3)*out2)-((vm1+vm2)*out4)+((vm1+vm2)*out3)-(vm1*out5)+(vm1*out4));vo1=bn*10000000/14142135;elsex_def=n*3.142/5;x_def2=2*n*3.142/5;x_def3=3*n*3.142/5;

x_def4=4*n*3.142/5;x_def5=n*3.142;bn=(2/3142)*1000*(1/n)*(-(vm1*out1)+(vm1)((vm1+vm2)*out2)+((vm1+vm2)*out1)((vm1+vm2+vm3)*out3)+((vm1+vm2+vm3)*out2)-((vm1+vm2)*out4)+((vm1+vm2)*out3)(vm1*out5)+(vm1*out4));von=((bn*10000000/14142135)/(n*n))**2)+von;enddf=(von**(1/2)/vo1); /*calculation of Distortion Factor*/thd=((vrms*vrms)-(vo1*vo1))/vo1; /*calculation of Total Harmonic Distortion*/end

1.4.3.2 LabVIEW Interfacing:

The parameters and the output Voltages are displayed on LabVIEW using

serial interfacing with the FPGA.

Some part of the code for serial interfacing of FPGA is shown below in

Fig.1.10 :

Fig.1.11 Code For Serial Interfacing written on Verilog

2.1) INTRODUCTION

An Inverter is one of the most common power electronics circuitry being used

from decades of history resulting in the availability of number of transformed

INVERTER2

versions of this functioning circuit varying from each other from different

specifications and parameters but the principle action of all are same that is to

convert Direct Current into Alternative Current at desired output voltage and

desired frequency with the help of desired utilization of components resulting

in desired amount of preciseness whereas The converted Ac can be attained at

any voltage and frequency,and all of the result depend upon the transformer

selection, switching circuitry and the overall operation and circuit controlling

circuitry.

According to the functionality and response effected by their cost , inverters

are of two main types

Modified sine wave inverters

True sine wave. inverters

2.1.1 Modified sine wave inverters

A modified sine wave inverter can give sufficient power that is needed for

household appliances. It is cheaper, but it has certain compact with loads such

as Refrigerator, ovens, Computers, Printers, and Wireless devices. All cheap

inverters are "modified sine wave inverters". These inverters are commonly

available at electric stores, and electronic stores etc. They usually don’t have

many features such as auto-start and other controlling abilities. These devices

are usually only about 50%-60% efficient, there they have significant power

losses and the half or quarter of the power is lost in the system before reaching

the output.

2.1.2 True Sine wave inverters

This type of sine wave inverter is designed to improve the power, and

efficiency and it even improve the quality of power which is supplied by grid

stations . It is used where higher Electronic Components are to operated,

These Inverters have the relation of output and Input that is efficiency which

is ideally up to 94% but 80%-85% is properly achieved. And this power can

be used in Motors, High efficiency based Computers and other electronically

equipped devices.

2.2) Multilevel Inverters

Dealing with Multilevel Inverters is a like dealing with a different technique

because multilevel inverters are emerging as a new breed of power Inverters

options for high-power applications.Multilevel inverter is utilized in a power

electronic circuitry that it can be operated both in rectifier modeas well as

inverter.The concept of multilevel inverter has been

introducedtsince1975 .The term multilevel began with the three-level inverter

the elementary concept of a multilevel inverter is to get higher power and

series of switches are used with many lower voltage dc sources that perform

the conversion of power by synthesizing a staircase waveform. Batteries,

Capacitors, and can be used as the multiple voltage sources. The commutation

of the power switchesiaggregate these dc sources in order to get high output

voltage, however the semiconductor switches voltage depends only upon the

rating of the sources to which they are connected to.

A multilevel inverter has several advantages over a simple inverter of 2 level

that uses high switching frequencyipulsewidth modulation (PWM).

2.2.1 ADVANTAGES OF MULTILEVEL INVERTERS

Multilevel inverter doesn’t only generate the desirable output voltages

with low distortion, but also can decreases the dv/dt stresses, and

through the problems of electromagnetic compatibility (EMC) can be

reduced.

Multilevel inverter produce smaller Common Mode voltage so with that

we can reduce the stress on the bearings of general electrical motor

where as Common Mode voltage can also be eliminated through

advanced modulation techniques.

Multilevel inverter has low distortion input current with drawing

capability

It is handy in terms of switching frequency as Multilevel inverter can

beoperated both at fundamental switching frequency as well as high

switching frequency(PWM).Whereas Lower switching frequency

usually means it has higher efficiency and lower switching loss.

2.2.2 GERNAL TOPOLOGIES OF MULTILEVEL

INVERTER

Basically there are three different multilevel inverter topologies that are

described as follows.

Diode Clamped

Cascaded H-Bridges

Flying Capacitors

The above mention first two of the three topologies are widely used having

different forms with respect to there requirement in power electronics

applications

2.2.2.1 DIODE CLAMPED MULTILEVEL INVERTER

The above mentioned types was resulted as the power electronics concerns

were focused on the increasing power of inverters (increase in current or

voltage).Some started to research on Current Source Inverters in order to

increase the current.and some started to research on Voltage Source Inverters

in order to increase the Voltage instead of current.In order to do accomplish

new to new inverters topologies were developed. .A. Nabae, I. Takahashi and

H. Akagi in 1981, presented a newneutral-point-clamped PWM inverter

(NPC-PWM).This Inverter was basically athree-level diode-clamped

inverter.Later on in 1990s the experiment on four,five and six level diode

clamped inverters topologies was also made.It is used for static variable speed

motor drives, var compensation, and interconnections of high-voltage system.

2.2.2.1.1 Advantages

It minimizes the capacitance requirement of the inverter by sharing

common dc.

For fundamental frequency switching the frequency is high.

2.2.2.1.2 Disadvantages

For a single Inverter the Real power flow is difficult because the

intermediate levels willitend to overcharge orrdischarge without

precisedmonitoringandocontrol.

The number of clamping diodes required is 4 timesyrelated to the

number of levels,therefore higher no. of levels will results in the

damage in the system.

2.2.2.2 CASCADED H-BRIDGE INVERTER

A single-phase cascaded H-Bridge inverter of k-level or n-stage is like a

complete multiple of a general H-BIRDGE circuit and the n-numbers of stages

can be attained by cascading that very circuitry for n-times where as they

operates on the separate dc source and is connected to a single-phase H-bridge

inverter. Each H-bridge inverter level can generate different output voltages ,

with the help of different combinations of the switches that turned on for

obtaining different multiples of +Vdc,and same numbers of multiples of -Vdc.

The 0 output can be obtain by turning all the swiches off whereas All full

bridge inverters outputs are connected in series such that the waveform which

is synthesized is the sum of the outputs of outputs. The number of phase

voltage levels k is defined by k = 2m+1, where mis the number of

individualidcisources.Cascaded H-bridge Multilevel Inverter is being getting

so much attention due to its wide advantages as a dc as well as ac interface.

2.2.2.2.1 Advantages:

Comparing to other Multilevel Inverters it requires the least number

of components.

Can generateialmost reasonable sinusoidaliwaveformivoltage while

only switching oneitime per fundamentalicycle.

Cascaded H-Bridge Multilevel inverter is to make direct parallel or

series connection to high voltage power system without any rating of

transformer.

It has high efficiency which is due to minimum switching frequency.

Fig 2.1 GENERAL H-BRIDGE MULTILEVEL INVERTER

2.3) DESIGN AND SPECIFICATIONS OF OUR 7-

LEVEL 3- STAGE INVERTER

2.3.1 OUR CIRCUIT INTRODUCTION

The technique we have used is the transformed version of the cascaded h-

bridge inverter which is being proposed in the IEEE research paper which

allow us to get access to the greater numbers of the stages of voltages without

increasing the exact multiple of components with each increasing stage and

has provide us with the an efficient solution of reducing component usage

round to 33 percent with every preceding stage which is very fundamental in

regards of any higher order of voltage stage requiring circuitry and help us to

reach higher voltage levels with same amount of components.

2.3.2 CIRCUIT OPERATION

The circuit we have selected has a remarkably easy operational technique that

can enable us to add further more stages, the current circuitry which we have

selected comprise of 7 levels of voltage and is a 3 stage inverter it consist of 7

transistors out of which a set of 2,2 transistors are specified for the controlling

of positive and negative cyclic operations respectively where as rest of the

three are used to open and close the different voltage levels in each cycle like

Vdc 2Vdc and 3Vdc

Fig 2.2 OUR USED CASCADED MULTILEVEL INVERTER FROM IEEE

RESEARCH PAPER

2.3.2.1 SWITCH POSITIONS OF CIRCUIT

SWITCHES OUTPUT

S2,S7,S3 VDC

S2,S7,S4 2VDC

S2,S7,S5 3VDC

S2,S7,S4 2VDC

S2,S7,S3 VDC

S1,S6,S3 -VDC

S1,S6,S4 -2VDC

S1,S6,S5 -3VDC

S1,S6,S4 -2VDC

S1,S6,S3 -VDC

Fig 2.3 TABLE OF SWITCH POSTIONS OF CASCADED 3 STAGE INVERTER

2.3.2.2 TRANSISTOR USED

IRF540 (N-Channel Mosfet)

Fig 2.4 SECTION OF DATA SHEET OF IRF540N

2.4) REVIEW OF INVERTER CIRCUIT

SIMULATIONS AND PCB DESIGN

2.4.1 CIRCUIT SIMULATION WITH PWM ON MULTISIM

Fig 2.5 CIRCUIT SIMULATION WITH PWM ON MULTISIM

2.4.2 CIRCUIT SIMULATION WITH COMPARATERS ON

MULTISIM

Fig 2.6 CIRCUIT SIMULATION WITH COMPARATERS ON MULTISIM

2.4.3 CIRCUIT SIMULATION WITH PIC16F877A ON PROTEUS

Fig 2.7 CIRCUIT SIMULATION WITH PIC16F877A ON PROTEUS

2.4.4 CIRCUIT LAYOUT DESIGN ON ORCAD

Fig 2.8 CIRCUIT LAYOUT DESIGN ON ORCAD

3.1 THE CHARGE CONTROLLER

3.1.1 INTRODUCTION

The charging of batteries is always an issue when we are talking about the

usage of batteries in any power backup or alternate energy systems. Batteries

must be charged in such a way that minimum of the system power is lost

while they are charging and the charging time also needed to be small as

possible. Furthermore, overcharging the batteries and letting them to be

discharged below a particular point DOD (depth of discharge) point also

decreases the battery life.

To overcome all of these problems, and for increasing the efficiency of the

system, the need of a charge controller is evident. A charge controller, also

known as the charge regulator or a battery regulator will set the limits at which

rate electric current will be added to or drawn from batteries. It prevents

overcharging and may prevent against over voltage , which can reduce battery

performance or life span and may pose a safety risk. It may also prevent

completely draining (deep discharging) a battery, or perform controlled

discharges depending on the battery technology, to protect battery life. The

accepted design will provide this output with the least amount of total losses.

3.1.2 OBJECTIVE

CHARGE CONTROLLER3

Alternate energy systems comprise of batteries for increasing the backup

time, in the absence of the sources of power (wind and solar energy). We need

to charge the battery bank in minimum time without trading off for the battery

life for our system. The battery life is reduced by over charging and also by

discharging it below the DOD (depth of discharge) point. We have converted

the batteries in series , so the battery equalization also needed to be maintained

for a longer battery life.

3.1.2.1 SALIENT FEATURES

No PWM charging required as the charge controller provides the

appropriate analogue voltage to control the pass element.

Reverse current protection.

Over charge protection.

Over discharge protection.

Charge equalization of series connected batteries.

Charge status indication.

3.1.3 DESIGN OF THE CHARGE CONTROLLER

The type of charge controller that we are using is constant voltage type, as

there are some limitations in charging a lead acid battery with constant current

so then we would never be reaching MPPT(maximum power point tracking)

because of which our efficiency will be cut down.

Our aim while designing a charge controller was to keep it as simple as we

can. Fig 3.1 Shows the Block Diagram of our Charge Controller,

Fig.3.1 Block Diagram of the Charge Controller

The charge controller consist of the following main parts:

1. DC-AC converter

2. TRANSFORMER

3. RECTIFIER

4. REVERSE CURRENT PROTECTION

3.1.3.1 DC-AC CONVERTER

There are different methods for conversion of direct current to alternating

current. We have used H-Bridge for dc to ac conversion. In which the

controlled gate pulses are provided by FPGA (FIELD PROGRAMMABLE

GATE ARRAY). We have used MOSFET IRF540 for designing H-Bridge. It

is significantly fast in switching and has higher current rating. The output is

shown in Fig.3.2.

Timings and Current Ratings :

td(on)(turn on delay time)=11ns

tr(rise time)=35ns

td(off)(turn off delay time)=39ns

tf(fall time)=35ns

Isd(source drain current)=33AIsdm(source drain current pulsed)=110A

Fig.3.2 DC-AC conversion by H-Bridge

3.1.3.2 TRANSFORMER

We are this transformer to regulate our input voltages. This transformer is

specially designed to handle voltages from 10V to 18V at its primary side and

generate outputs of 14V on Multiple Tappings which is the optimum voltage

required to charge the battery. Output of the H-Bridge is provided to the

Primary windings of the Transformer and on the multiple secondary windings

a Relay is connected which is energized by the FPGA checking for the range

of input voltages. Then the output is feed to the Rectifier circuit.

3.1.3.3 RECTIFIER CIRCUIT

The Output of the Transformer is feed to the rectifier circuit which is made

using a bridge configuration of diodes and to have a smooth DC output a filter

made up of an Inductor and a Capacitor is attached before the batteries which

are being charged.

3.1.3.4 REVERSE CURRENT PROTECTION

For the prevention of reverse current we are using diode UF4007

Fast recovery time.

Current rating of 30A.

3.2 THE BATTERY BANK CHARGER

3.2.1 IMPORTANCE OF CHARGER

Battery life and capacity both are most critical and both the parameters are

strongly affected by different methods of charging. Battery capacity is the

rating of the specific battery i.e number of ampere-hours that a charged battery

is rated to be provided at a defined discharge rate. Rated capacity is basically

used for expressing as the unit for charging and discharging current rates of

battery, for instance a 4 amp-hour battery charging at 800mAmpere is said to

be charging at a rate of ‘C/5’ . two ways are used to measure battery life

performance, stand by life and cycle life. Float life or Standby life , refers to

the measure of how long the battery can be sustained in a fully charged state

and when called upon will it be able to provide proper service. Cycle life

denotes to the measure of discharge and charge cycles that a battery will not

die out before its capacity is reduced to its specific threshold level The

measure which actually indicates useful life expectancy will depend on the

particulars of the application. Generally, both parameters of battery life will be

important.

When a typically used lead acid batter starts charging, different chemical

reactions takes place on positive and negative plates of the battery. Lead

sulphate ( PbSO4), is first converted to lead and then get coated on battery’s

negative plate, on the other plate i.e positive plate lead dioxide get coated. The

overcharge reaction will begin , when the majority of the lead sulphate are

converted and coated, which results in the generation of oxygen and hydrogen

gas. In unsealed batteries it will lead to quick loss of water. In other case for

sealed batteries, if charging rate is moderate, the majority of oxygen and

hydrogen will react to recombine before occurring of dehydration.

In both type of batteries, prolonged charging rate significantly above C/10,

will result in dehydration, accelerated grid corrosion and reduced service life.

3.3 MAXIMUM POWER POINT TRACKING

Hybrid renewable energy system can be of different types, using different

methods, in which one of measure is Solar system. The advantage of Solar

hybrid system is that when grid and Solar power production are used together,

the reliability of the system is enhanced. Additionally, the battery storage size

can be reduced because of the less reliance on any one method of power

production, often when there is as when solar power is not available , grid can

be used as back up for charging.

PHOTOVOLTAIC cells operate at a single point where the values of the

Voltage (V) and current (I) of the PV cell result in a maximum power output.

These values which is equal to V/I , correspond to a particular load resistance.

PHOTO VOLTAIC cell has an exponential relationship between current(I)

voltage(V), and the MPP (maximum power Point ) occurs at the knee of the

curve, where the resistance gets equal to the negative of the differential

resistance (V/I = -dV/dI) . Maximum power point tracker (MPPT) utilizes

control logic or circuit for searching of this point and thus allowing the

converter circuitry to extract the maximum power from a cell.

When there is no solar power available (at night or may be in some adverse

weather) an Off-grid PV power system use battery bank to supply its loads.

Although when the battery pack voltage fully charged might be closed to the

PV Array's Peak Power Point, this is unlikely to be true when the battery is

partially discharged. Charging might start at a voltage considerably below

Array Peak Power Point, and Maximum Power Point Tracking (MPPT) can

resolve this problem.

When the battery bank in an off-grid system is fully charged and PHOTO

VOLTAIC production begins to exceed local loads, Maximum Power Point

Tracking (MPPT) will stop operating the PV Array at its Peak Power Point as

the excess power will now be wasting. The Maximum Power Point Tracking

(MPPT) must then shift the operating point of array away from the PV peak

power point until and unless power production exactly matches the demand. In

a grid tied PV system, the grid is essentially a battery with almost infinite

charge storing capacity. The grid can always absorb surplus PV power, and it

can cover shortfalls in PV production (e.g., at night). Batteries are thus needed

only for protection from grid outages. The Maximum Power Point Tracking

(MPPT) in a grid-tied PV system will always be operating the PV array at its

Peak Power Point unless when the batteries are full so the grid fails and there

are insufficient local loads . It would then have to back the PV Array away

from its Peak Power Point as in the off-grid case.

Maximum Power Point Tracking (MPPT) can be configured to drive an

electric motor without an accumulator. They allow for substantial advantages,

especially when starting a motor with load. This can need an initiating current

that is comfortably above the short-circuit rating of the PHOTOVOLTAIC

panel. A Maximum Power Point Tracking (MPPT) can step the panel's

comparatively, high voltage and low current cut down to the low voltage and

high current required for starting the motor. Once the motor starts and its

current requirements have dropped, the Maximum Power Point Tracking

(MPPT) will automatically increase the voltage to normal. The suggested

Charge Controller will monitor the battery voltage with continuous intervals.

Whenever the battery potential reaches the lower threshold point, immediately

the Field Programmable Gate Array(FPGA) will start charging. The Field

Programmable Gate Array(FPGA) will continuously monitor and charge the

battery. On reaching at upper threshold voltage it will disconnect the battery

means it will switch OFF the MOSFET so that there will be no more battery

charging.

SOLAR PANEL

Fig.3.3 130w poly crystalline solar module

4.1) OBJECTIVE:

The objective of this part was to provide the system debugger or system

maintenance in charge with a suitable environment for monitoring. Providing

a suitable monitoring environment means to enable the system debugger or

system maintenance in charge to observe the wide spread system under one

roof and on a single bench, and the monitoring tool used should be that much

capable so as it can allow the end user to get full knowledge of the state and

condition of the operations and flow of outputs and inputs of the system.

Since monitoring in regards of the hybrid power systems means to gather

information from the various parts of the systems and display them via

suitable monitoring mechanism. As hybrid power systems are always spread

on wide areas consisting of solar panels, wind turbine, battery banks,

conventional power sources, there switching circuitries, there forward

circuitries like MPPT, charge controller, DC to DC converter, inverter and etc.

So end user required a very efficient mechanism for monitoring these devices

and their parameters.Which can manage all the information without involving

very complex circuitry.

LABVIEW MONITORING4

4.2) WHAT WE REQUIRED:

for our FPGA based Hybrid Power Cascaded Multilevel Inverter and

Monitoring System we have utilized the efficient switching and controlling

capabilities of the FPGA which enables us to produce an efficient output from

the multistage inverter then we have selected an efficient circuitry from the

IEEE research paper that allows us to reduce the circuit complexity and the

components without effecting the output.

So we required to buildup an efficient environment for monitoring which can

further enhance our system overall response and functionality by providing a

suitable monitoring environment to our end user so he can monitor the

following desired parameters of our cascaded Multilevel Inverter

Vrms of the Inverter

Total Harmonic Distortion

Distortion Factor

Harmonic Distortion

4.3) WHAT IS LABVIEW MONITORING:

LabVIEW is an extremely productive environment for generating customized

applications of visualization which are help full in monitoring and interacting

with real-world data, signals or information that are sent to it for monitoring.

For a monitoring a system the monitoring tool should be capable of

identifying the changes,breakdowns, shoot-up and different types of variation

accruing in the system so as it can collect all these information and represent it

to the end user with its visualizing environment. The processing abilities of

LabVIEW can help you collect and gather the details and information we

required and keep our monitoring system operating efficiently.

LabVIEW can do offline and online analysis process by gathering information

variables through internet, intranet or some dedicated hardware and can

display them.

Once the information or signals are send to LabVIEW, the end user can

accomplish plenty of tasks with that data in LabVIEW including data

monitoring, data transforming, data logging or data transporting.

Implementing a monitoring solution for a distributed control and distributed

segments containing system we have to deal with the processes functioning in

each segment of the system and had to generate the response which should be

reliable, reasonable and had a negligible amount or preferred to have no data

loss, so we have to implement proper collection mechanism at the back end.

Data in LabVIEW can be from a one and single source or multiple sources

also lab view is capable of providing a monitoring environment for the live

and stored sources. Dealing with one data transmitting point is relatively an

easier operation to perform, Where as dealing with multiple sources and data

transmitting point require more complex circuitry at the back end as well it

requires more systemic options involvement of the LabVIEW itself so as to

correctly multiplex the data from various live sources and manage them

accurately and further utilize it to produce visualization of the data set in a

proper manner so as the end user can observe the system information and

behavior accurately without any difficulty further more the source can be a

live web source transmitting with the help of internet from distance places or

any other live communicator from the site to the monitoring room . In addition

of the live data processing and its displaying options the data can be loaded

from the pre recorded sources or log which has been maintained separately

and that data then can be used to and can further presented in a very user

friendly environment

4.4) REQUIRMENT AND CHALLENGES FOR LABVIEW

4.4.1 REQUIREMENT

The FPGA based Hybrid Power and Monitoring System requires LabVIEW

for the monitoring of system parameters comprising the view of four live

parameters which are taken from the circuitry and then there calculations are

being made on the FPGA with the help of the formulas which are formed as a

result of the mathematical calculations made for the circuitry and are then

these mathematical calculations are utilized to form code on Verilog which

enables FPGA to perform calculations and the results of calculations are then

stored in the 32 bit registers which are then send to the LabVIEW serially( i.e.

via serial cable).

4.4.2 CHALLENGES

The challenges faced in developing the Monitoring Environment on the

LabVIEW were as follow

Receiving 32 bit information of a single parameter from 8 bit serial

cable.

Sorting out the four different set of data coming from single path

without mixing parts and identifying the correct packet for the correct

parameter and then placing it correctly to its destination.

Frequent updating of the data coming from the system continuously and

avoiding data loss at any instant.

Developing user friendly environment for monitoring of our selected

parameters.

4.5) BLOCK DIAGRAM ON LABVIEW

The development of the monitoring environment on LabVIEW required block

diagram programming on the software were the required set of functions were

performed by utilizing the capabilities of the tools and options provided by the

LabVIEW and all the above mentioned challenges were sorted out and

atmosphere was thus finally being built

Fig 4.1 Block Diagram Made on LabView

4.6) FRONT PANEL ON LABVIEW

The user friendly environment of the LabVIEW was built and the user

interacting screen named front panel was developed with the help of

LabVIEW tools so as the end user can monitor the changes and variation

occurring in real time in our desired and selected four parameters of The

FPGA based Hybrid Power and Monitoring System.

Fig 4.2 Front Panel Design on Labview

Multilevel Inverter

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