Subtractor /Multiplier

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Subtractor /Multiplier. Section 4.5 & 4.7. Outline. Delay Four Bit Subtractor Multiplier. Four Bit Adder. Erroneous Results When Delay is inserted in half_adder.v. Four-Bit Adder. C 4 is calculated last because it takes C 0 8 gates to reach C 4 . - PowerPoint PPT Presentation

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Subtractor/Multiplier

Section 4.5 & 4.7

Outline

• Delay • Four Bit Subtractor• Multiplier

Four Bit Adder

Erroneous Results When Delay is inserted in half_adder.v

Four-Bit Adder

C4 is calculated last because it takes C0 8 gates to reach C4.Each FA uses 2 XOR, 2 AND and 1 OR gate.A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.

Build a Full-Adder Circuit

w1

w2 w3

M1 M2

One gate-delay

Wait for the four bit adder circuit to compute the results

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Function EngineeringDiscipline Intern

Subtraction

Unsigned Number

Decimal b1 b0

0 0 0

1 0 1

2 1 0

3 1 1

(2-bit example)

Unsigned Addition

• 1+2=

Decimal b1 b0

0 0 0

1 0 1

2 1 0

3 1 1

Decimal b1 b0

1 0 1

+ 2 1 0

3 1 1

Unsigned Addition

• 1+3=

Decimal b1 b0

0 0 0

1 0 1

2 1 0

3 1 1

Decimal b1

b0

1 1

1 0 1

+ 3 1 1

4 1 0 0

(Carry Out)

(Indicates Overflow)

Overflow can be an issue in unsigned addition.

Unsigned Subtraction (1)

• 1-2=

Decimal b1 b0

0 0 0

1 0 1

2 1 0

3 1 1

Decimal b1

b0

1 0 1

+ -2 1 0

1 1

0 0

-1 0 1

(1’s complement)

(2’s complement)

Unsigned Subtraction (2)

• 2-1=

Decimal b1 b0

0 0 0

1 0 1

2 1 0

3 1 1

Decimal b1 b0

1

2 1 0

+ -1 1 1

3 1 0 1

Discarded

Summary for Unsigned Addition/Subtraction

• Overflow can be an issue in unsigned addition (An overflow is detected from the end carry out of the most significant position)

• Unsigned Subtraction (M-N)– If M≥N, and end carry will be produced.

The end carry is discarded.– If M<N, • Take the 2’s complement of the sum• Place a negative sign in front

Four-Bit Adder-Subtractor

For detecting overflow in addition/subtraction of signed numbers

For detecting overflow in unsigned numbers

The Mode Input (1)

B0

If M=0, = If M=1, =

The Mode Input (2)

If M=0, If M=1,

M=0 (Addition)

0

B3 B2 B1 B0

M=1 (Subtraction)

1

2’s complement is generated of B is generated!

Four-Bit Adder-Subtractor

FA0FA1FA2FA3

X0X1X2X3

X4

X_FA_0X_FA_1X_FA_2X_FA_3

Verilog Model of a 4 bit adder/subtractor

Sample output of adder/subtractor circuit

Ignore V if you are working with unsigned numbers.

Binary Multiplication

Two-Bit Binary Multiplier

(multiplicand)

(multiplier)

𝐴 0𝐵00 0 0

0 1 0

1 0 0

1 1 1

Use an AND gate to multiply A0 and B0

Hardware Correlation

Hardware Correlation

G0G1

G2G3

W0W1W2

W3

HA1 HA0