Post on 15-Apr-2017
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ISQED 2002 (C) Monterey Design Systems 1
ISQED 2002
Olivier CoudertMonterey Design System
Timing and Design Closure in Physical Design Flows
ISQED 2002 (C) Monterey Design Systems 2
Summary
Why a Need for Physical Flows?Some Physical FlowsA refinement based Physical FlowConclusion
ISQED 2002 (C) Monterey Design Systems 3
Design Flow
PhysicalFlow
RTL
Behavioral spec.
Behavioral synthesis
Logicsynthesis
Layout
Gate levelnetlist
while (x<a) do x1:= x + dx; u1:= u - (3*x*u*dx) - (3*y*dx); y1:= y + (u*dx); x:= x1; u:= u1; y:= y1;endwhile
RC: = ALU 1(RX, a, comp);wait until clock AND RC;RX1 := ALU1 (RX, RDX, ADD);RT1 := MULT1(RU, RX);RT2 := MULT 2(3, RDX);wait until clock;RT3 := MULT1(RT1, RT2);RT4:= MULT2(RT2, RY);
ISQED 2002 (C) Monterey Design Systems 4
Pre DSM Physical Flow
Clock
Global place
Global route
Layout
Gate levelnetlist
Detailedplace
Detailedroute
ISQED 2002 (C) Monterey Design Systems 5
Timing & Interconnect Wireload models were ALWAYS inaccurate
Good average but large variance Post-synthesis signoff was possible when
interconnect contributed ~20% of the total capacitance
But now the interconnect capacitance is dominating the total capacitance with each new process generation
Elmore delay model becomes inaccurate as resistance increases
ISQED 2002 (C) Monterey Design Systems 6
Gate vs. Net in Optimal Delay
0
0.2
0.4
0.6
0.8
1
1.2
0.5x 1.0x 2.0x 3.0x 4.0x 6.0x 8.0x 9.0x
Relative Driver Size
gate
del
ay/to
tal d
elay
0.25 um
0.18 um
optimal delay point
ISQED 2002 (C) Monterey Design Systems 7
Dominant coupling capacitance can produce a noise problem
Or a delay problem
Noise and Delay Coupling Effects
Switching
Noise Sensitive
CC
CL
increased delayCC
CL
ISQED 2002 (C) Monterey Design Systems 8
Decrease in supply voltage at the gates Due to current flow through the power resistive
network Effects of IR drop on circuit performance
IR drop
IR drop delay 0 V 0.114 ns 0.15 V 0.126 ns (+10%) 0.3 V 0.143 ns (+25%) 0.5 V 0.184 ns (+61%)
input1.41.21.00.80.60.40.20.0
ISQED 2002 (C) Monterey Design Systems 9
Electromigration & Self Heating Metal interconnect
disintegration due to high current density Can occur for power
network and also signal nets
Important DSM effect Higher current densities
due to increased currents and finer wire widths/thicknesses
Faster switching is increasing the di/dt’s
ISQED 2002 (C) Monterey Design Systems 10
Signal Integrity Xtalk
Can produce last minute timing problems at DR IR-drop
Can invalidate P/G routing Design rules, electromigration
Make DR more difficult Inductance
Need new analysis tools and avoidance techniques
ISQED 2002 (C) Monterey Design Systems 11
Physical Flow Take a gate-level netlist and a library Take constraints (place, route, timing, power, design
rules, etc) Produce production worthy layout
Meet timing P/G and clock Satisfy design rules Signal integrity aware (xtalk, IR-drop, EM) Predictable Fast TAT
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Summary
Why a Need for Physical Flows?Some Physical FlowsA refinement based Physical FlowConclusion
ISQED 2002 (C) Monterey Design Systems 14
Block Based Flow Procedure:
Partition the design in small blocks (~50k gates) Implement each block Assemble the blocks
Assumptions: Shield timing from the interconnect because:
small blocks strong drivers
Interconnect becomes a local property of a block Budgeting can be done on every blocks
Benefit: Reuse existing classical physical flow on blocks
ISQED 2002 (C) Monterey Design Systems 15
Block Based Flow Problem:
Strong driver leads to suboptimal solutions Interconnect is NOT a local property of a block
because of congestion Does not capture large nets interconnecting
several blocks Budgeting is non-trivial, and can lead to
suboptimal solutions Assembly is complex if conditions at the
boundaries of the blocks (capacitance & driver strength) is not fixed
ISQED 2002 (C) Monterey Design Systems 16
Constant Delay Based Flow Procedure:
Allocate delays on logical stage Translate the delays into gains (Co/Ci) Keep the gains constant as the gates are placed
Assumptions: Delays is a linear function of the gain Convex libraries
Benefit: Fix timing upfront Fast
ISQED 2002 (C) Monterey Design Systems 17
Constant Delay Based Flow Problem:
Gain cannot be preserved, needs buffer insertion Consequently, allocation need to be revisited Non-convex libraries Mapping onto discrete libraries Still will need DR information, e.g., for Xtalk effect
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Summary
Why a Need for Physical Flows?Some Physical FlowsA refinement based Physical FlowConclusion
ISQED 2002 (C) Monterey Design Systems 19
One cannot optimize what one cannot measure accurately enough
Data is measured with a distribution (x, ) Need to know --noise Need to know how the optimization affect the
distribution --correlation
Principle
ISQED 2002 (C) Monterey Design Systems 27
Reduce the Spread
0
50
100
150
200
250
300
00.
15 0.3
0.46
0.61
0.76
0.91
1.06
1.22
1.37
1.52
1.67
Normalized Wire-length ProfileN
umbe
r of n
ets
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Reduce the Spread
050
100150200250300350400
00.
170.
340.
510.
680.
851.
011.
181.
351.
521.
69
Normalized Wire-length ProfileN
umbe
r of n
ets
ISQED 2002 (C) Monterey Design Systems 29
Reduce the Spread
050
100150200250300350400
00.
170.
34 0.5
0.67
0.84
1.01
1.18
1.34
1.51
1.68
Normalized Wire-length ProfileN
umbe
r of n
ets
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Physical prototype Earliest stage of the design when interconnect is
predictable Physical logic optimization can start at this level
only Timing signoff can be done at this level only
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Physical Logic Optimization Load and driver strength adaptation
Place Sizing Buffering Pin swapping Cloning
Timing boundary shifting Transparent latch Retiming Useful skew
Area/Power recovery Technology remapping Re-synthesis Redundancies based optimization
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How Different Is Phy. Logic Opt.? Need to work with accurate models
timing, power, design rules aware, etc mostly non-convex often CPU time costly
Need to place gates tight communication with placer
Need to generate routes New techniques
size & buffer & route & place resynthesize & remap & place logic optimization for congestion relief
ISQED 2002 (C) Monterey Design Systems 35
Placement/Synthesis/Routing The flexibility of the placement and the continuous
refinement allows logic optimization to continue throughout the flow Continual monitoring of “what is critical” From extensive to local logic optimization
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Clock Distribution Clock tree is created at the physical prototyping
level Distribution of latches and flip-flops is known A complete buffered/gated clock tree is
automatically synthesized Congestion and skew accounted for
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Power/Ground Distribution P/G network built at the physical prototype level
Built from user-provided power stripe/ring rules P/G network can have a huge impact on
congestion Can judge the quality and integrity of the
power/ground network (IR drop)
ISQED 2002 (C) Monterey Design Systems 41
Summary
Why a Need for Physical Flows?Some Physical FlowsA refinement based Physical FlowConclusion
ISQED 2002 (C) Monterey Design Systems 42
Conclusion Physical flows must consider logic, place, and route
simultaneously Physical flows need new solutions:
Logic synthesis & placement interaction Synthesize logic & route at the same time Early estimation of xtalk so that GR can allocate
routing resources to DR Logic optimization for congestion relief, for SI …
ISQED 2002 (C) Monterey Design Systems 43
The future Possible flow:
Fast behavioral synthesis together with floorplanning Evaluate area/performance tradeoff Timing driven block & port placement Evaluate top level routing of P/G integrity Budgeting Clock methodology
Fast RTL to gate synthesis of blocks Physical synthesis of block:
Logic optimization + placement + routing Block assembly & chip verification