TPTTDO (Daisy Chain b/w FPGAs)

TPTTDO

Probe for JTAG

TPTTMS

TPTDI

TPTCLK

Probe for SPI / I2C

TPMOSI

TPSCLK

TPMISO

TPSEL1

TPSEL0

TPSDA

TPSCL

NOTE :U35 is I2C Bus Isolator

Probe for IPM Bus

TPSDABTPSCLB

TPSDAA

TPSCLA

NOTE :U5 (bottom) is I2C Bus Isolator for IPMB AU6 (top) is I2C Bus Isolator for IMPB B

Probe for GND

TPG3

TPG5

TPG6

TPG2

TPG1

TPG4

Probe driven by FPGA

TP1_2

TP2_2

TP3_2

TP1_1

TP2_1

TP3_1

NOTE :TP1 , 2, and 3 are connected to AD3, AD4, and AD2, respectively.

Power distribution (1)

PIM In : 48VOut : 3.3V & -48V

Power ConverterIn : -48VOut: VCC12

U16In : VCC12Out : VCC3V3(20A)

U17 In : VCC12Out : VCC1V0(20A)

Power distribution (2)

U22In : VCC1V8Out : VDDR1 (1.5V)(3A, linear)

U32In : VCC1V8Out : VDDR2 (1.5V)(3A, linear)

U29In : VCC3V3Out : VCC2V5(3A, linear)

U18 In : VCC12Out : VCC1V8(10A)

U23 In : VCC12Out : MGTAVTT(10A)

U21 In : VCC12Out : MGTAVCC(10A)

U17U16

117

118

121

120

VCC12

VCC12

VCC12@U16, U17

VCC3V3@U29

U29

157

VCC3V3

MGTAVCC (1.0V)@U21

U21

8689 6576

MGTAVCC

MGTAVTT (1.2V)@U23

132

90

122105

MGTAVTT

U23

203.3V (management)

193.3V (management)

Management 3.3V @ PIM

66_1

68_1

67_1

67_2

66_2

68_2

VCC1V8

VCC1V8

VCC1V8@FPGA

VDDR1@U22VDDR2@U32

Pin5 or Pin4. Pin5 looks easier to avoid short with PIn3 of GND

U22

U32

55_2

75_2

155_2

115

53_2

60_2

53_1

55_1

54_1

75_1

54_259

_1

VCC3V3

VCC1V0

VCC3V3

56_1

56_2

156_

1

155_1

156_

2

60_2

59_2

VCC2V5

VCC1V0

VCC3V3

VCC3V3

Polarized Capacitors(330uF, Yellow big ones)

VCC1V8

Polarized Capacitorsaround PIM C40 (470uF), C35, C36 (120uF)They have to have bar on downside as shown below

Chip Orientation withTiny dot silkscreened on board (examples)

CLOCK setting

U27=GTXREFCLK

U11=SYSCLK

Typical Setting

125 MHz{1, 0, 1, 1, 0, “X”}

156.25 MHz{1, 0, 1, 1, 0, “X”}

0

10

1

200 MHz{1, 0, 0, 1, 0, “X”}