Date post: | 03-Jun-2018 |
Category: |
Documents |
Upload: | yuvraaj-kumar-singh |
View: | 218 times |
Download: | 0 times |
of 18
8/13/2019 08a Sample and Holds_Johns & Martin Slides
1/18
slide 1 of 18University of Toronto D.A. Johns, K. Martin, 1997
Sample-and-Holds
David Johns and Ken MartinUniversity of Toronto
8/13/2019 08a Sample and Holds_Johns & Martin Slides
2/18
slide 2 of 18University of Toronto D.A. Johns, K. Martin, 1997
Sample-and-Hold Circuits
Also called track-and-hold circuits
Often needed in A/D converters
Conversion may required held signal
Alsoreduces errors due to different delay times
Errors in Sample-and-Holds
Sampling pedestal or Hold Step
errors in going from track to hold should be signal independent for no distortion
Signal feedthrough should be small during hold
Speed due to bandwidth and slew-rate limitations Droop rate slow change during hold mode
Aperture (or sampling) jitter effective sampling timeerror in time; difficult in high-speed designs
8/13/2019 08a Sample and Holds_Johns & Martin Slides
3/18
slide 3 of 18University of Toronto D.A. Johns, K. Martin, 1997
Basic Concept
Basic circuit has some practical problems
Charge Injection
Causes hold stepAperature Jitter
Sampling time variation function of Vin
Vin Vout1
clk
Chld
Q1 V
8/13/2019 08a Sample and Holds_Johns & Martin Slides
4/18
slide 4 of 18University of Toronto D.A. Johns, K. Martin, 1997
Charge Injection
When goes low, channel charge on causes V to
have negative step.
If clock edge fast, 1/2 flows each way.
Channel charge
(1)
(2)
resulting in
(3)
clk Q1
QChld
QCH
2----------
CoxWLVeff-1
2-------------------------------= =
Veff-1 VGS1 Vtn VDD Vtn Vin= =
VQ
C-hldChld
-------------------C
oxWL V
DD V
tn V
in( )
2Chld-------------------------------------------------------------= =
8/13/2019 08a Sample and Holds_Johns & Martin Slides
5/18
slide 5 of 18University of Toronto D.A. Johns, K. Martin, 1997
Charge Injection
linearly related to gain error
also linearly related to , which is nonlinearly
related to distortion error
Often gain error can be tolerated but not distortion
Also change due to the overlap capacitances
(4)
Causes dc offset effect
V Vin
V VtnV
in
VCoxWLov VDD VSS( )
Chld
-----------------------------------------------------
8/13/2019 08a Sample and Holds_Johns & Martin Slides
6/18
slide 6 of 18University of Toronto D.A. Johns, K. Martin, 1997
Aperature Jitter
Q1 turns off when clock falls to within of
True sampling time depends on value of distortion
ts1-ideal t
s2-ideal
ts1-actual
ts2-actual
Vin clk
Sampling jitter
Vtn Vin
Vin
8/13/2019 08a Sample and Holds_Johns & Martin Slides
7/18
slide 7 of 18University of Toronto D.A. Johns, K. Martin, 1997
S/H Charge Reduction
Transmission gate difficult to make p and n transistorsmatch
Dummy switch Q2 is 1/2 size of Q1 to match charge injection difficult to make clocks fast enough so exactly 1/2charge is injected up to 5 times better than without dummy
Vin Vout1
Chld
Q1 V
clk
clk
Vin Vout1
Chld
Q1 VQ2
clk
clk
CMOS transmission gate Dummy switch
slightly delayed
8/13/2019 08a Sample and Holds_Johns & Martin Slides
8/18
slide 8 of 18University of Toronto D.A. Johns, K. Martin, 1997
High Input Impedance
dc offset of buffer divided by loop gainDisadvantages
Opamp output must have fast slew rate
Samp time, charge inject input signal dependent Speed reduced due to overall feedback
Vin
Chld
1
Q1
Vout
clk
buffer
8/13/2019 08a Sample and Holds_Johns & Martin Slides
9/18
slide 9 of 18University of Toronto D.A. Johns, K. Martin, 1997
Reduced Slew Rate Requirement
Samp time, charge injection - input signal dependent
Vin
V
out
Chld
1
clk
Q1
clk
clk
Q3
Q2
8/13/2019 08a Sample and Holds_Johns & Martin Slides
10/18
slide 10 of 18University of Toronto D.A. Johns, K. Martin, 1997
Input SignalIndependence
Q1 always at virtual ground
Samp time, charge injection - NOT dependent
Charge injection causes ONLY dc offset
Q2 used to clamp opamp1 output near ground
Slowerdue to two opamps in feedback
Vin Vout
Chld
clk
Q1
clk Q2
Opamp 1
Opamp 2
8/13/2019 08a Sample and Holds_Johns & Martin Slides
11/18
slide 11 of 18University of Toronto D.A. Johns, K. Martin, 1997
Reduced Offset (Single Ended)
Charge injected by Q1 matched by Q2 into
If fully differential design, matching occurs naturallyleading to lower offset.
Vin Vout
Chld
clk
Q1
clk Q3
clk
Q2
Chld
Chld
8/13/2019 08a Sample and Holds_Johns & Martin Slides
12/18
slide 12 of 18University of Toronto D.A. Johns, K. Martin, 1997
Reduced Offset (Differential)
Gnd is common mode voltage
Vin
Vout
Chld
clk
clk
Chld
clk
clk
8/13/2019 08a Sample and Holds_Johns & Martin Slides
13/18
slide 13 of 18University of Toronto D.A. Johns, K. Martin, 1997
Example #1 (BiCMOS)
Needs opamp capable of driving resistive loads
Good high-speed BiCMOS configuration when in track mode
Might add a small input capacitor
R
R
C
clk
clk
VinVoutQ1
Q2
3 dB 1 RC( )=
8/13/2019 08a Sample and Holds_Johns & Martin Slides
14/18
slide 14 of 18University of Toronto D.A. Johns, K. Martin, 1997
Example #2
Charge injection of transistors cancel
Clock signals are signal dependent
Good speed, moderate accuracy
Vin
Vout
clk
C1
C2
Q1
Q2
8/13/2019 08a Sample and Holds_Johns & Martin Slides
15/18
slide 15 of 18University of Toronto D.A. Johns, K. Martin, 1997
Example #3
Hold capacitor is large Miller capacitor
Can use smaller capacitors and switches good speed If Q2 turned off first, injection of Q1 small due to Miller
effect
Vin
Voutclk
C1C2Q1
Q2
8/13/2019 08a Sample and Holds_Johns & Martin Slides
16/18
slide 16 of 18University of Toronto D.A. Johns, K. Martin, 1997
Example #3 (contd)
Vin
Vout
C1C2
Vin
Vout
C1C2
Miller cap
Amp outputdoes not swingmuch
Higher speedamplifierpossible
1 A+( )C1C2
C1 C2+-------------------
Sample Mode
Hold Mode
8/13/2019 08a Sample and Holds_Johns & Martin Slides
17/18
slide 17 of 18University of Toronto D.A. Johns, K. Martin, 1997
Example #4
Accurate since offset cancellation performed
Slow since opamp swings from 0 to Vin every cycle
Vout
Vin
CH
1 2
1
8/13/2019 08a Sample and Holds_Johns & Martin Slides
18/18
slide 18 of 18University of Toronto D.A. Johns, K. Martin, 1997
Example #5
B1
C1C2
C3
B2
1
1
1a
1a
2
Vin VoutQ1 Q2
Q3
Q4
Q5
Improved accuracy
High input imped
-> advanced
Charge inj of Q4 andQ5 cancel (and issignal indep)
Charge inj of Q1 andQ2 - no effect
Charge inj of Q3reduced as before
1a