1 abk 000714 Futures for DSM Physical Implementation: Where is the Value, and Who Will Pay? Andrew...

1abk 000714

Futures for DSM Physical Implementation: Futures for DSM Physical Implementation: Where is the Value, and Who Will Pay?Where is the Value, and Who Will Pay?

Andrew B. KahngAndrew B. Kahng

[email protected] , http://[email protected] , http://vlsicad.cs.ucla.edu

UCLA Computer Science DepartmentUCLA Computer Science Department

12th DA Show, Tokyo12th DA Show, Tokyo

July 14, 2000July 14, 2000

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Subwavelength Gap since .35 mSubwavelength Optical LithographySubwavelength Optical Lithography

Numerical Technologies, Inc.

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““The Design Productivity Gap”The Design Productivity Gap”

Equivalent Added Complexity

68 %/Yr compoundedComplexity growth rate

21 %/Yr compoundProductivity growth rate

Year Technology Chip Complexity Frequency Staff Staff Cost* 3 Yr. Design

1997 250 nm 13 M Tr. 400 MHz 210 90 M

1998 250 nm 20 M Tr. 500 270 120 M

1999 180 nm 32 M Tr. 600 360 160 M

2002 130 nm 130 M Tr. 800 800 360 M

* @ $ 150 k / Staff Yr. (In 1997 Dollars)

Logic Tr./Chip Tr./S.M.

““How many gates How many gates can I get for $N?”can I get for $N?”

Source: SEMATECHSource: SEMATECH

$1$1

$3$3$10$10

Potential Design Complexity and Designer Productivity

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OutlineOutline

Future DSM physical implementation technologiesFuture DSM physical implementation technologiesdesign closuredesign closure

design-manufacturing interfacedesign-manufacturing interface

ValuationsValuationsthe significance of design productivity and design qualitythe significance of design productivity and design quality

structural aspects of the EDA industrystructural aspects of the EDA industry

ValuesValuestoward maturity and a design productivity renaissancetoward maturity and a design productivity renaissance

Conclusions: Who Will Pay ?Conclusions: Who Will Pay ?

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OutlineOutline







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What is design closure?What is design closure?

netlist

user constraints

layout

routing

placement

logicoptimization/timing verif

synthesis

RTL

“front end consistent with back end”

meet constraints here

meet constraints there

What is the problem ?What is the problem ? source: K. Keutzer, DAC 2000

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Design cl

osure

== pred

icting in

terco

nnect

Design cl

osure

== pred

icting in

terco

nnect

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Aristo, DAC-2000 panelAristo, DAC-2000 panel

Gate-Level Place & Route

Gate-Level Optimization

DesignConstraintsIP BlocksLibrary

Top-Level Routing

RC Extraction

Timing Analysis

Early Planning

Design Refinement

Chip Assembly

PREDICTABLE HIERARCHICAL DESIGN CONVERGENCE

ARISTO TYPICAL DESIGN FLOW

DesignNetlist

Gate-LevelVerilog

RTL Verilog

Hard Blocks

Concurrent Block Partitioning, Clustering & Placement

Block Shaping, Compaction &Concurrent Port Placement

ConcurrentBlock

Synthesis

““Olympic Flame”Olympic Flame”

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GDSII

Tim

ing

Rou

te

Pla

ce

log

ic

Physical PrototypingIncreas

ingModeli

ngDetail

Design Signoff

timing librarystatistical WLM

Behavioral / RTL synthesis

RTL

Monterey, DAC-2000 panelMonterey, DAC-2000 panel

““Recycle Bin”Recycle Bin”

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SequencePlace

&Route

PrepareDatabase

3D Extraction

True-3DParasitics

DelayCalculation

TimingAnalysis

TimingAnalysis

InterconnectDriven

Optimization

InterconnectDriven

Optimization

SynthesisRTL

Timing Sign-off

Driver sizing,topology-based

optimization

Sequence, DAC-2000 panelSequence, DAC-2000 panel

““Anakin Skywalker’s Pod Racer”Anakin Skywalker’s Pod Racer”

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Clear Thinking: Basics of Design ConvergenceClear Thinking: Basics of Design Convergence

What must converge ?What must converge ?logic, timing, and spatial embeddinglogic, timing, and spatial embeddingsupport front-end signoff, provide support front-end signoff, provide predictablepredictable back-end back-end

Ways to achieve Convergence through Ways to achieve Convergence through PredictabilityPredictabilitycorrect by construction (“assume, then enforce”)correct by construction (“assume, then enforce”)

constraints and assumptions passed downstream; not much goes upstreamconstraints and assumptions passed downstream; not much goes upstream ignores concerns via guardbandingignores concerns via guardbanding separates concerns as able (e.g., FE logic/timing vs. BE spatial embedding)separates concerns as able (e.g., FE logic/timing vs. BE spatial embedding)

construct by correction (“tight loops”)construct by correction (“tight loops”) logic-layout unification; synthesis-analysis unification, concurrent optimizationlogic-layout unification; synthesis-analysis unification, concurrent optimization

elimination of concernselimination of concerns reduced degrees of freedom, pre-emptive design techniquesreduced degrees of freedom, pre-emptive design techniques e.g., power distribution, layer assignment / repeater rules, GALS/LISe.g., power distribution, layer assignment / repeater rules, GALS/LIS

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What Must A Design Closure Tool Look Like ?What Must A Design Closure Tool Look Like ?InputInput

RT-level HDL + technology + constraintsRT-level HDL + technology + constraints

OutputOutput““go”: recipe for invocation and composition of “go”: recipe for invocation and composition of “commoditycommodity” SP&R” SP&R““no go”: diagnosis of RTL code problemsno go”: diagnosis of RTL code problems

Logical and physical hierarchies co-evolveLogical and physical hierarchies co-evolvespatial: top-down coarse placement spatial: top-down coarse placement physical hierarchy physical hierarchylogic/timing: implementable RTL logic/timing: implementable RTL logical hierarchy logical hierarchylimits of human fanout, organizations limits of human fanout, organizations always have hierarchy always have hierarchy

natural sequence of no-floorplanning, phys-floorplanning, RTL-floorplanning...natural sequence of no-floorplanning, phys-floorplanning, RTL-floorplanning...

Details (must construct, predict, ignore, eliminate, ...)Details (must construct, predict, ignore, eliminate, ...)pin optimizations, interconnect planning, hierarchy reconciliations, pin optimizations, interconnect planning, hierarchy reconciliations,

budgeting mechanisms, compatibility with downstream SP&R, ...budgeting mechanisms, compatibility with downstream SP&R, ...

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DON’T Develop This RTL Planning TechnologyDON’T Develop This RTL Planning Technology

Don’tDon’t spend too much time packing blocks that will change spend too much time packing blocks that will changegoal = early diagnosis, or handoff to commodity SP&Rgoal = early diagnosis, or handoff to commodity SP&Rpre-synthesis uncertainty = +/- 15% area, timingpre-synthesis uncertainty = +/- 15% area, timing

wirelength, path timing wirelength, path timing must be connectivity-centric, not packing-centric must be connectivity-centric, not packing-centric easier to work on direct realizations of the floorplan, not representationseasier to work on direct realizations of the floorplan, not representations

need relative coarse placement that adapts to incremental ECOsneed relative coarse placement that adapts to incremental ECOs

Don’tDon’t over-constrain block shaping (rectangles, L’s, T’s) over-constrain block shaping (rectangles, L’s, T’s)placers handle constraints w/ granularity = site spacing, row heightplacers handle constraints w/ granularity = site spacing, row heightconstructive pin assignment constructive pin assignment don’t need roundness don’t need roundnesspath timing optimization path timing optimization may even want disconnected shapes may even want disconnected shapes

Don’tDon’t under-constrain layout region under-constrain layout regionfixed-diefixed-die planning: simultaneous zero-whitespace, zero-overlap planning: simultaneous zero-whitespace, zero-overlap

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DoDo Allow the Following... Allow the Following...

1.0

1.0

0.5,0.5

Blk A Blk B

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It Is What the Cells Want Anyway !It Is What the Cells Want Anyway !

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DoDo Develop This RTL Planning Technology Develop This RTL Planning TechnologyRTL partitioning RTL partitioning

understand interaction b/w block definition and placement qualityunderstand interaction b/w block definition and placement qualityrecognize and cure a physically challenged logic hierarchyrecognize and cure a physically challenged logic hierarchy

Global interconnect planning and optimizationGlobal interconnect planning and optimizationsymbolic route representations to support block plan ECOssymbolic route representations to support block plan ECOs

Controllable SP&R back end (including power/clock/scan)Controllable SP&R back end (including power/clock/scan)Incremental / ECO optimizations, and optimizations that are Incremental / ECO optimizations, and optimizations that are

“robust” under partial or imperfect design knowledge“robust” under partial or imperfect design knowledgeBetter estimators (“initial WLMs”)Better estimators (“initial WLMs”)

to account for resource, topological heterogeneityto account for resource, topological heterogeneityto account for optimizations (placement, ripup/reroute, timing)to account for optimizations (placement, ripup/reroute, timing)

“ “earliest RTL signoff with detailed P&R knowledge”earliest RTL signoff with detailed P&R knowledge”

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ConclusionConclusion

RTL-to-GDSII will commoditize SP&R market sectorsRTL-to-GDSII will commoditize SP&R market sectorsMany solutions are reasonable and will survive in the marketplace Many solutions are reasonable and will survive in the marketplace

RTL-down SP&R becomes a “commodity” RTL-down SP&R becomes a “commodity”

No solution is completeNo solution is complete

Key missing pieces include RTL partitioning; hierarchy and block Key missing pieces include RTL partitioning; hierarchy and block management; real working RTL diagnosis and signoffmanagement; real working RTL diagnosis and signoff

Individual point technologies (e.g., global placement or detailed Individual point technologies (e.g., global placement or detailed routing) become less valuable routing) become less valuable integration is most important integration is most important

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OutlineOutline







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Subwavelength Gap since .35 mSubwavelength Optical LithographySubwavelength Optical Lithography

Numerical Technologies, Inc.

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Optical Proximity Correction (OPC)Optical Proximity Correction (OPC)

Corrective modifications to improve process controlCorrective modifications to improve process controlimprove yield (process window)improve yield (process window)

improve device performanceimprove device performance

With OPCNo OPC

Original Layout

OPC Corrections

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Future OPC-Related TechnologiesFuture OPC-Related Technologies

WYSIWYG broken WYSIWYG broken (mask) verification bottleneck (mask) verification bottleneckFunction-aware OPC insertionFunction-aware OPC insertion

OPC insertion is for predictable circuit performance, functionOPC insertion is for predictable circuit performance, functiontool understands functional intent, makes only the corrections that tool understands functional intent, makes only the corrections that

win $$$, reduce performance variationwin $$$, reduce performance variationapplies to mask inspection as wellapplies to mask inspection as well

OPC- and manufacturing-aware layoutOPC- and manufacturing-aware layoutdon’t make corrections that can’t be manufactured or verifieddon’t make corrections that can’t be manufactured or verifiedmodel effects of geometry on OPC cost needed to yield functionmodel effects of geometry on OPC cost needed to yield functionunderstand (data volume, verification) costs of breaking hierarchyunderstand (data volume, verification) costs of breaking hierarchy

Difficult solutions to flow issuesDifficult solutions to flow issuese.g., how to avoid making same corrections 3x (library, router, PV)e.g., how to avoid making same corrections 3x (library, router, PV)

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Phase Shifting Masks (PSM)Phase Shifting Masks (PSM)

conventional maskglass

Chrome

phase shifting mask

Phase shifter

0 E at mask 0

0 E at wafer 0

0 I at wafer 0

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Double-Exposure Bright-Field Alternating PSMDouble-Exposure Bright-Field Alternating PSM

0

180180 + =

Positive photoresists for poly, metal Positive photoresists for poly, metal unexposed areas = printed features unexposed areas = printed features

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Why is Alternating PSM Valuable and Essential ?Why is Alternating PSM Valuable and Essential ?PSM enables smaller transistor gate lengths LPSM enables smaller transistor gate lengths Leffeff

““critical” polysilicon features only (gate Lcritical” polysilicon features only (gate Leffeff))

faster device switching faster device switching faster circuits faster circuits better critical dimension (CD) control better critical dimension (CD) control better parametric yield, $/wafer better parametric yield, $/wafer

Full-chip PSM (poly, local interconnect) Full-chip PSM (poly, local interconnect) denser layouts denser layoutssmaller die area smaller die area more $/wafer more $/wafer

achieving Roadmap for device density depends on PSM achieving Roadmap for device density depends on PSM Data pointsData points

25 nm gates manufactured with 248nm DUV steppers (NTI + MIT 25 nm gates manufactured with 248nm DUV steppers (NTI + MIT Lincoln Labs, June 2000)Lincoln Labs, June 2000)

90nm gates in production at Motorola, Lucent since 199990nm gates in production at Motorola, Lucent since 1999

Alternative: $5 B fab with equipment that doesn’t exist yetAlternative: $5 B fab with equipment that doesn’t exist yet

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The Phase Assignment ProblemThe Phase Assignment Problem

Assign 0, 180 phase regions such that critical features Assign 0, 180 phase regions such that critical features

with width < B are induced by adjacent phase regions with width < B are induced by adjacent phase regions

with opposite phaseswith opposite phases

0 180

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Key: Global 2-ColorabilityKey: Global 2-Colorability

?180 0

0180 180

180

Odd cycle of “phase implications” Odd cycle of “phase implications” layout cannot be layout cannot be

manufacturedmanufacturedlayout verification becomes a global, not local, issuelayout verification becomes a global, not local, issue

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F4

F2

F3

F1

Critical features: F1,F2,F3,F4

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F4

F2

F3

F1

Opposite-Phase Shifters (0,180)

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F4

F2

F3

F1

S1

S2

S3

S5

S4

S6

S7S8

Shifters: S1-S8

PROPER Phase Assignment:PROPER Phase Assignment: OppositeOpposite phases for opposite shifters phases for opposite shifters Same Same phase for overlapping shiftersphase for overlapping shifters

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F4

F2

F3

F1

S1

S2

S3

S5

S4

S6

S7S8

Phase Conflict

Proper Phase Assignment is IMPOSSIBLE

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F4

F2

F3

F1

S1

S2

S3

S5

S4

S6

S7S8

Phase Conflictfeature shiftingto remove overlap

Phase Conflict ResolutionPhase Conflict Resolution

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F4

F2

F1

S1

S2

S3 S4

S7S8

Phase Conflictfeature widening to turnconflict into non-conflict

Phase Conflict ResolutionPhase Conflict Resolution

F3

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Future PSM-Related TechnologiesFuture PSM-Related TechnologiesUCLA-Cadence: first comprehensive methodology for UCLA-Cadence: first comprehensive methodology for

AltPSM layout designAltPSM layout design3-way 3-way sharedshared responsibility for phase-assignability responsibility for phase-assignability

good layout practicesgood layout practices (local geometry) (local geometry) no T shapes, no doglegs, even-length transistor fingers, ...no T shapes, no doglegs, even-length transistor fingers, ... but no complete set of “rules” existsbut no complete set of “rules” exists

automatic phase conflict resolutionautomatic phase conflict resolution (global 2-colorability) (global 2-colorability) latest technology: optimal conflict resolution for 50K polygons in 6 seclatest technology: optimal conflict resolution for 50K polygons in 6 sec

reuse of layoutreuse of layout (free composability) (free composability) problem: guarantee reusability of phase-assigned layouts, such that no odd problem: guarantee reusability of phase-assigned layouts, such that no odd

cycles can occur when the layouts are composed together in a larger layoutcycles can occur when the layouts are composed together in a larger layout

Changes all flows: library design, custom design, SP&RChanges all flows: library design, custom design, SP&R

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Macroscopic Process EffectsMacroscopic Process Effects

Large topograph ica l v a ria tion caused by so ftpad and m echan ica l p rope rties

D enseA rray

C ontact O veretchcauses leakage

Isolated T ransistor D ense Array

CMP, SOG

RIE

CVD

Dummy Fill controls several types of process distortions :

R. Pack, Cadence

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Field-Dependent AberrationField-Dependent Aberration

Cell A

Cell A

Cell A

(X 1 , Y 1)

(X 0 , Y 0)

(X 2 , Y 2)

F ie ld-dependentaberrationsaffect the fide lityand p lacem entof critica l c ircu itfeatures.

Big C hip

Field-dependent aberrations cause placement errors and Field-dependent aberrations cause placement errors and

distortionsdistortions ),(A_CELL),(A_CELL),(A_CELL 220011 YXYXYX

Center: Minimal Aberrations

Edge: High Aberrations

Tow

ard

s Le

ns

Wafer Plane

Lens

R. Pack, Cadence

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ConclusionsConclusions

RTL-to-GDSII commoditizes existing SP&R market sectors RTL-to-GDSII commoditizes existing SP&R market sectors

Design-manufacturing interface Design-manufacturing interface willwill change EDA change EDAClosely related to foundry capital expenditureClosely related to foundry capital expenditure

Unites EDA with much of mask industry, even process developmentUnites EDA with much of mask industry, even process development

Expands scope of physical “verifications”, moves awareness Expands scope of physical “verifications”, moves awareness upstream into “syntheses” (logic, layout)upstream into “syntheses” (logic, layout)

Very comprehensive changes to data model, infrastructure, flowsVery comprehensive changes to data model, infrastructure, flows

Unified, front-to-back solutions will winUnified, front-to-back solutions will win

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OutlineOutline







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The Productivity GapThe Productivity Gap

Equivalent Added Complexity

68 %/Yr compoundedComplexity growth rate

21 %/Yr compoundProductivity growth rate

Year Technology Chip Complexity Frequency Staff Staff Cost* 3 Yr. Design

1997 250 nm 13 M Tr. 400 MHz 210 90 M

1998 250 nm 20 M Tr. 500 270 120 M

1999 180 nm 32 M Tr. 600 360 160 M

2002 130 nm 130 M Tr. 800 800 360 M

* @ $ 150 k / Staff Yr. (In 1997 Dollars)

Logic Tr./Chip Tr./S.M.

““How many gates How many gates can I get for $N?”can I get for $N?”

Source: SEMATECHSource: SEMATECH

$1$1

$3$3$10$10

Potential Design Complexity and Designer Productivity

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Mask CostMask Cost

O(25 mask levels) ~ “$1M mask set” in 130nmBut: average only 500 wafers per mask set !

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““Keep the Fabs Full”Keep the Fabs Full”

Design technology must keep manufacturing facilities fully Design technology must keep manufacturing facilities fully

utilized with:utilized with:high-volume partshigh-volume parts

high-high-marginmargin parts parts

Foundry capital cost > $2BFoundry capital cost > $2BHow much value of new designs is needed to fill the fab ???How much value of new designs is needed to fill the fab ???

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Design Productivity Need + DSM Design Productivity Need + DSM = 2 EDA Trends= 2 EDA Trends

Effort/Value

Leve

l of A

bstr

actio

n

RTL

Mask

Application /Behavior

SW/HW

Gate-level “platform”Gate-level “platform”

ImplementationImplementationGapGap

Design Entry LevelDesign Entry Level

Today Tomorrow

source: MARCO GSRC

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Fab Amortization Fab Amortization Close the Implementation Gap Close the Implementation Gap

Effort/Value

Leve

l of A

bstr

actio

n

RTL

Mask

Application

SW/HWHand-off “platform”Hand-off “platform”

Design Entry LevelDesign Entry Level

source: MARCO GSRC

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0%

20%

40%

60%

80%

100%

1999

2002

2005

2008

2011

2014

% Area Memory

% Area ReusedLogic

% Area New Logic

Percent of die area that must be occupied by memory to maintain SOC design productivity

Design Productivity Gap Design Productivity Gap Low-Value Designs? Low-Value Designs?

Source = Japanese system-LSI industry

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Reduce Back-End Effort ?Reduce Back-End Effort ?

Example: repeating Example: repeating dense wiring fabricdense wiring fabricpattern at minimum pitchpattern at minimum pitch

S SV V SG

SG

SSV

V

SS SSVV VV SSGG

- Eliminates signal integrity, delay uncertainty concerns- Eliminates signal integrity, delay uncertainty concerns- But has at least 60% - 80% density cost- But has at least 60% - 80% density cost

source: MARCO GSRC

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Improve IP Reuse Productivity ?Improve IP Reuse Productivity ?

MacroShells (the Protocol Interface)Communication Channels

MicroShells (the IP Requirements)

P1

P2

P3

P4

P5

P6

P7

Pearls (the IP Processes)

source: MARCO GSRC

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Embedded ProcessorsLP ARM0.5-2 MIPS/mW

ASIPsDSPs

1 V DSP 3 MOPS/mW

QUALITY Problem : > 1000x Energy-Flexibility GapQUALITY Problem : > 1000x Energy-Flexibility Gap

DedicatedHW

Flexibility (Coverage)

En

ergy

Eff

icie

ncy

MO

PS

/mW

(or

MIP

S/m

W)

0.1

1

10

100

1000

ReconfigurableProcessor/Logic

10-50 MOPS/mW

100-200 MOPS/mW

Source: Prof. Jan Rabaey, UC Berkeley

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““Keep the Fabs Full”Keep the Fabs Full”

Design technology must keep manufacturing facilities fully Design technology must keep manufacturing facilities fully

utilized with:utilized with:high-volume partshigh-volume parts

high-high-marginmargin parts parts

What happens when design technology “fails” ?What happens when design technology “fails” ?not enough high-value designsnot enough high-value designs the semiconductor industry will find a “workaround”the semiconductor industry will find a “workaround”

reconfigurable logicreconfigurable logic

platform-based designplatform-based design

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Platform-Based DesignPlatform-Based Design

System ApplicationSystem Application

Silicon ProcessSilicon Process

PlatformPlatformCompilationCompilation

StructuredStructuredCustomCustom

RTLRTLFlowFlow

FPGAFPGA FPGA &FPGA &GPPGPP

Config.Config.ProcessorProcessor

DSPDSP GPPGPP

ApplicationApplicationCompilationCompilation

Once perOnce perApplicationApplication

Simple &Simple &DirectDirect

Once perOnce perFamilyFamily

SophisticatedSophisticatedCompilerCompiler

ArchitectureArchitecture

MicroarchitectureMicroarchitecture

source: MARCO GSRC

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Design-manufacturing interface Design-manufacturing interface willwill change EDA change EDA

Design productivity gap threatens design Design productivity gap threatens design quality quality

ASIC business model is at risk ASIC business model is at riskTAT achieved at cost of QORTAT achieved at cost of QOR

low QOR low QOR low silicon value low silicon value

electronics industry chooses reprogrammable, platform-based electronics industry chooses reprogrammable, platform-based “workarounds”“workarounds”

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OutlineOutline







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EDA Industry Structure: Vendor SideEDA Industry Structure: Vendor Side

Tool usage focus still the core of the business modelTool usage focus still the core of the business modelslows down the move to open systems, open infrastructure slows down the move to open systems, open infrastructure

Some indicators of “immaturity”Some indicators of “immaturity”lack of metrics and other common infrastructurelack of metrics and other common infrastructure

LEF/DEF, SPEF, *SPF, OLA, .lib, ... are a minimal start, were slow to LEF/DEF, SPEF, *SPF, OLA, .lib, ... are a minimal start, were slow to developdevelop

no differentiation between strategic, commodity technologyno differentiation between strategic, commodity technology

Some indicators of “poor health”Some indicators of “poor health”customer integration investment is 2.5x - 4x times tool investmentcustomer integration investment is 2.5x - 4x times tool investment

EDA R&D EDA R&D 20% of revenue, but 80+% of R&D = support, infrax 20% of revenue, but 80+% of R&D = support, infrax

R&D often provided by customers (designers), outsourced (M&A)R&D often provided by customers (designers), outsourced (M&A)

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Collectively, insist that EDA be “everything to everyone”Collectively, insist that EDA be “everything to everyone” fragmentation of vendor R&D resource, lots of secret options, ...fragmentation of vendor R&D resource, lots of secret options, ... tools attempt to fit in all methodologies tools attempt to fit in all methodologies fit in none fit in none

Won’t let EDA vendors evolve to a more sustainable modelWon’t let EDA vendors evolve to a more sustainable modelpush for low ASPs while spending 4x on integration push for low ASPs while spending 4x on integration low R&D low R&D

levelslevelssometimes invest in fragmentation of R&D talent (20 SP&R, 70 sometimes invest in fragmentation of R&D talent (20 SP&R, 70

verif startups)verif startups)

No differentiation between strategic, commodity technologyNo differentiation between strategic, commodity technologyone-offs, hidden optionsone-offs, hidden optionsvery little cooperative foundation: e.g., data model + API, silicon very little cooperative foundation: e.g., data model + API, silicon

calibration, library char, RLC extraction, gate/int delay calc, STA, calibration, library char, RLC extraction, gate/int delay calc, STA, physical verificationphysical verification

EDA Industry Structure: Customer SideEDA Industry Structure: Customer Side

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““Failure of EDA”Failure of EDA” why pay for itwhy pay for it why invest in itwhy invest in it why work on itwhy work on it ......

Must stop wasting scarcest of all resources: brainsMust stop wasting scarcest of all resources: brainshow many GDSII parsers do we need ? how many interconnect how many GDSII parsers do we need ? how many interconnect

delay calculators ? how many netlist connectivity data models ?delay calculators ? how many netlist connectivity data models ?acknowledge de facto commodity technologyacknowledge de facto commodity technologyturn these technologies into common infrastructureturn these technologies into common infrastructure

Mature behavior is requiredMature behavior is requiredwith respect to “strategic vs. commodity” distinctionwith respect to “strategic vs. commodity” distinctionwith respect to “control”with respect to “control”

Must Escape “Death Spiral”Must Escape “Death Spiral”

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Design productivity gap threatens design Design productivity gap threatens design qualityquality

EDA industry must evolve and mature to achieve EDA industry must evolve and mature to achieve EDA EDA

industry productivityindustry productivityeliminate wastage on duplicated commodity infrastructureeliminate wastage on duplicated commodity infrastructure

acknowledge and share de facto commodity technologiesacknowledge and share de facto commodity technologies

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OutlineOutline







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CAD Life Cycle QuestionsCAD Life Cycle Questions

What will the design problem look like?What will the design problem look like?

How can we quickly develop the right design technology?How can we quickly develop the right design technology?

Did I really solve the problem? Did I really solve the problem? Did the design process improve?Did the design process improve?

Did achievable design envelope get bigger? Did achievable design envelope get bigger?

Proposal: We MUST develop shared infrastructure to answer Proposal: We MUST develop shared infrastructure to answer

all three questionsall three questions

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1. Technology Extrapolation1. Technology Extrapolation

Evaluates impact Evaluates impact ofofdesign technologydesign technologyprocess technologyprocess technology

Evaluates impact Evaluates impact ononachievable designachievable designassociated design problemsassociated design problems

Questions to be addressed:Questions to be addressed:

What will the design problem look like ?What will the design problem look like ?

Sets requirements for CAD tools, methodologies, investmentSets requirements for CAD tools, methodologies, investment

Familiar example: ROADMAPSFamiliar example: ROADMAPS

How and when do L, SOI, How and when do L, SOI, SER, etc. matter?SER, etc. matter?

What is the most power-efficient noise What is the most power-efficient noise management strategy?management strategy?

Will layout tools need to perform Will layout tools need to perform process simulation to effectively model process simulation to effectively model

cross-die and cross-wafer cross-die and cross-wafer manufacturing variation?manufacturing variation?

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Most commonly used optimal repeater sizing expression Most commonly used optimal repeater sizing expression

(Bakoglu)(Bakoglu)

New study:New study:Sweep repeater size for single stage in the chain Sweep repeater size for single stage in the chain Examine both delay and energy-delay productExamine both delay and energy-delay product

Optimal Repeater SizingOptimal Repeater Sizing

in

D

CRCRS

int

int

0 100 200 300 400 500

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

Bakogluoptimal sizing

Lseg = 2.14 mm W=S=1m W=S=0.5m

Cri

tic

al

Pa

th D

ela

y (

ns

)

Repeater Size (X min size)

1

2

3

4

5

6

No

rma

lized

En

erg

y-D

ela

y P

rod

uc

t

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Elastic scattering

Diffuse scattering

Cu Resistivity: Effect of Line Width ScalingCu Resistivity: Effect of Line Width Scaling

Effect of Electron ScatteringEffect of 5 nm Barrier

• Conformal 5 nm barrier assumed• Even a 5 nm barrier will increase resistivity drastically

• No barrier assumed• Electron scattering increases resistivity• Lowering temperature has a big effect

525320250

95 58 48

280170133

ITRS 1999 Line width (nm)GlobalSemiglobalLocal

source: MARCO IFRC

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Cu Resistivity: Barriers Deposition TechnologyCu Resistivity: Barriers Deposition Technology

Atomic Layer Deposition (ALD)

Ionized PVD

Collimated PVD

• 5 nm barrier assumed at the thinnest spot• No scattering assumed, I.e., bulk resistivity

Interconnect dimensions scaled according to ITRS 1999

source: MARCO IFRC

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What Technology Extrapolation is Available Today?What Technology Extrapolation is Available Today?

Too many RoadmapsToo many Roadmaps ITRS, JISSO, STARC, … RoadmapsITRS, JISSO, STARC, … Roadmapssome university tools: SUSPENS, GENESYS, RIPE, BACPAC, …some university tools: SUSPENS, GENESYS, RIPE, BACPAC, …numerous tools in industrynumerous tools in industry

ObservationsObservationseveryone predicts “same” parameters but different assumptions, inputs: everyone predicts “same” parameters but different assumptions, inputs:

near-total duplication of effort !!! near-total duplication of effort !!!no documentation or visibility into internal calculationsno documentation or visibility into internal calculations““hard-wired” hard-wired” cannot easily test other modeling choices cannot easily test other modeling choicesmissing: models of CAD tools and optimizations (what is really missing: models of CAD tools and optimizations (what is really

“achievable”?)“achievable”?)missing: scope, comprehensive coveragemissing: scope, comprehensive coverage

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FlexibilityFlexibilityedit or define new parameters and relations between themedit or define new parameters and relations between themperform specific studies (but different studies at different times)perform specific studies (but different studies at different times)

QualityQualitycontinuous improvementscontinuous improvementsworld-wide participation of expertsworld-wide participation of experts

TransparencyTransparencyopen-source mechanismopen-source mechanismmodels visible to the usermodels visible to the user

No more redundant effortNo more redundant effortpermanent repository of first choicepermanent repository of first choiceadoptability and maintainabilityadoptability and maintainability

Shared, Worldwide Technology Extrapolation SystemShared, Worldwide Technology Extrapolation System

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GTX: GSRC Technology Extrapolation SystemGTX: GSRC Technology Extrapolation System

GTX is set up as a GTX is set up as a frameworkframework for technology extrapolation for technology extrapolation

““Living Roadmap”Living Roadmap”

Open-source: http://vlsicad.cs.ucla.edu/GSRC/GTX/Open-source: http://vlsicad.cs.ucla.edu/GSRC/GTX/

Parameters (data)

Rules (models)

Rule chain (study)

Knowledge

Engine (derivation)

GUI (presentation)

ImplementationUser inputs

Pre-packaged

GTX

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2. CAD-IP Reuse2. CAD-IP ReuseHow can we quickly develop the right design technology?How can we quickly develop the right design technology?Problem: Currently takes 5-7 years to get a leading-edge Problem: Currently takes 5-7 years to get a leading-edge

algorithm into production toolsalgorithm into production toolsResult: Must solve today’s design problems with yesterday’s CAD Result: Must solve today’s design problems with yesterday’s CAD

technologytechnologyProblem: Published descriptions insufficient for replication Problem: Published descriptions insufficient for replication

or even comparison of algorithmsor even comparison of algorithmsResult: Cannot identify, evaluate or advance the CAD technology Result: Cannot identify, evaluate or advance the CAD technology

leading edgeleading edgeIF WE DO NOT KNOW WHERE THE LEADING EDGE OF CAD IF WE DO NOT KNOW WHERE THE LEADING EDGE OF CAD

TECHNOLOGY IS, WE HAVE A REAL PROBLEM !!!TECHNOLOGY IS, WE HAVE A REAL PROBLEM !!!

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Unclear Leading Edge of CAD: A Real ProblemUnclear Leading Edge of CAD: A Real ProblemComparison of two Comparison of two LIFO-FMLIFO-FM partitioner implementations partitioner implementations

Min and Ave cut sizes from 100 single-start trialsMin and Ave cut sizes from 100 single-start trials

Papers 1, 2 both published since mid-1998Papers 1, 2 both published since mid-1998This is a crisis !This is a crisis !

Tolerance LIFO-FM Ibm01 Ibm02 Ibm03 Ibm04 Ibm05 Ibm06

Min 450 648 2459 3201 2397 1436Paper1 Ave 2701 12253 16944 20281 3420 16578

Min 366 301 1588 1014 2640 10082%

Paper2 Ave 594 542 2688 1802 3382 1746Min 270 313 1624 544 1874 1479

Paper1Ave 486 3872 12348 2383 3063 14007Min 244 266 1057 561 2347 821

10%

Paper2Ave 445 405 1993 1290 3222 1640

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2. CAD-IP Reuse2. CAD-IP ReuseHow can we quickly develop the right design technology?How can we quickly develop the right design technology?Problem: Currently takes 5-7 years to get a leading-edge Problem: Currently takes 5-7 years to get a leading-edge

algorithm into production toolsalgorithm into production toolsResult: Must solve today’s design problems with yesterday’s CAD Result: Must solve today’s design problems with yesterday’s CAD

technologytechnologyProblem: Published descriptions insufficient to enable Problem: Published descriptions insufficient to enable

replication or even comparison of algorithmsreplication or even comparison of algorithmsResult: Cannot identify, evaluate or advance the CAD technology Result: Cannot identify, evaluate or advance the CAD technology

leading edgeleading edgeThe TAT and QOR problems are not only for CAD The TAT and QOR problems are not only for CAD

customers, but for CAD itself !!!customers, but for CAD itself !!!productivityproductivity of CAD tool development (time-to-market) of CAD tool development (time-to-market)qualityquality of resulting CAD tools (quality-of-result) of resulting CAD tools (quality-of-result)

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Analogy: Hardware Design :: CAD Tool DesignAnalogy: Hardware Design :: CAD Tool Design

Hardware design is difficultHardware design is difficultcomplex electrical engineering and optimization problemscomplex electrical engineering and optimization problemsmistakes are costlymistakes are costlyverification and test not trivialverification and test not trivialfew can afford to truly exploit the limits of technology few can afford to truly exploit the limits of technology A Winning Approach: A Winning Approach: Hardware IP reuseHardware IP reuse

CAD tools design is difficultCAD tools design is difficultcomplex software engineering and optimization problemscomplex software engineering and optimization problemsmistakes can be showstoppersmistakes can be showstoppersverification and test not trivial verification and test not trivial few can manage complexity of leading-edge approachesfew can manage complexity of leading-edge approachesA "Surprising Proposal”: A "Surprising Proposal”: CAD-IP reuseCAD-IP reuse

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What is CAD-IP?What is CAD-IP?

Data models and benchmarksData models and benchmarkscontext descriptions and use modelscontext descriptions and use modelstestcases and good solutionstestcases and good solutions

Algorithms and algorithm analysesAlgorithms and algorithm analysesmathematical formulationsmathematical formulationscomparison and evaluation methodologies for algorithms comparison and evaluation methodologies for algorithms executables and source code of implementationsexecutables and source code of implementationsleading-edge performance resultsleading-edge performance results

Traditional (paper-based) publicationsTraditional (paper-based) publications

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The Bookshelf: A Repository for CAD-IPThe Bookshelf: A Repository for CAD-IP““Community memory” for CAD-IPCommunity memory” for CAD-IP

data models data models algorithmsalgorithmsimplementationsimplementations

Publication medium Publication medium that enables efficient CAD R&Dthat enables efficient CAD R&Dbenchmarks, performance resultsbenchmarks, performance resultsalgorithm descriptions and analysesalgorithm descriptions and analysesquality implementations (e.g., quality implementations (e.g., open-sourceopen-source UCLA PDTools) UCLA PDTools)

Simplified comparisons to identify best approachesSimplified comparisons to identify best approaches

Easier for industry to communicate new use modelsEasier for industry to communicate new use models

http://vlsicad.cs.ucla.edu/GSRC/bookshelfhttp://vlsicad.cs.ucla.edu/GSRC/bookshelf

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Proposed Change for Entire EDA CommunityProposed Change for Entire EDA Community

Proposal: Data model and API are Proposal: Data model and API are non-competitivenon-competitive and and non-differentiatingnon-differentiatingGenesis, MilkyWay, CHDStd-IDM, UDM-Nike, … all very similar !Genesis, MilkyWay, CHDStd-IDM, UDM-Nike, … all very similar !should be should be commoditized and shared by the communitycommoditized and shared by the community““coopetition” coopetition” distributes infrastructure burden, frees R&D resourcesdistributes infrastructure burden, frees R&D resources

coopetition = cooperation + competitioncoopetition = cooperation + competition

Common data model across multiple vendors, users Common data model across multiple vendors, users common API common API isis necessary; common database necessary; common database is notis not necessary necessary““control” issues solved by open-source model (control” issues solved by open-source model (www.openeda.orgwww.openeda.org))issues of integration and adoption costs still to be overcomeissues of integration and adoption costs still to be overcome

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3. METRICS3. METRICS

Did I really solve the problem?Did I really solve the problem?Foundation of design optimization: Foundation of design optimization:

understanding of what should be optimized by which heuristicunderstanding of what should be optimized by which heuristicunderstanding of design as a understanding of design as a processprocess

There are no standards or infrastructure for measuring and There are no standards or infrastructure for measuring and optimizing the semiconductor design processoptimizing the semiconductor design process

““METRICS” = “measure, then improve”METRICS” = “measure, then improve”design becomes less of an art and more of a formal disciplinedesign becomes less of an art and more of a formal discipline

InfrastructureInfrastructuredesign process data collection infrastructuredesign process data collection infrastructuredata mining / visualization / diagnosis infrastructuredata mining / visualization / diagnosis infrastructure

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METRICS System ArchitectureMETRICS System Architecture

Inter/Intra-net

DBMetrics Data Warehouse

WebServer

JavaApplets

DataMining

Reporting

Transmitter Transmitterwrapper

Tool Tool Tool

TransmitterAPI

XML

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Benefits of METRICSBenefits of METRICS

Benefits for project managementBenefits for project managementaccurate resource prediction at any point in design cycleaccurate resource prediction at any point in design cycle

up front estimates for people, time, technology, EDA licenses, IP re-use...up front estimates for people, time, technology, EDA licenses, IP re-use...

accurate project post-mortemsaccurate project post-mortems everything tracked - tools, flows, users, noteseverything tracked - tools, flows, users, notes no “loose”, random data left at project end no “loose”, random data left at project end

management consolemanagement console web-based, status-at-a-glance of tools, designs and systems at any point in web-based, status-at-a-glance of tools, designs and systems at any point in

project; correct go / no-go decisions as early as possibleproject; correct go / no-go decisions as early as possible

Benefits for tool R&DBenefits for tool R&Dfeedback on tool usage and parameters usedfeedback on tool usage and parameters used

real benchmarkingreal benchmarking

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Example DiagnosesExample DiagnosesPlacer runtime is linear in number of cells Placer runtime is linear in number of cells GOOD ! GOOD !

CPU_TIME = 12 + 0.027 NUM_CELLS (corr = 0.93)CPU_TIME = 12 + 0.027 NUM_CELLS (corr = 0.93)Placer runtime becomes Placer runtime becomes unpredictableunpredictable at two particular at two particular

utilization thresholds utilization thresholds BAD ! BAD !80%, 95%80%, 95%

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The Industry Needs METRICS The Industry Needs METRICS StandardsStandards

Standard metrics naming across toolsStandard metrics naming across toolssame name same name same meaning, independent of tool suppliersame meaning, independent of tool supplier

generic metrics and tool-specific metricsgeneric metrics and tool-specific metrics

no more ad hoc, incomparable log filesno more ad hoc, incomparable log files

Standard schema for metrics databaseStandard schema for metrics database

Standard middleware for database interfaceStandard middleware for database interface

See: See:

http://vlsicad.cs.ucla.edu/GSRC/METRICShttp://vlsicad.cs.ucla.edu/GSRC/METRICS

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CAD Life Cycle QuestionsCAD Life Cycle Questions

What will the design problem look like?What will the design problem look like?answer: technology extrapolationanswer: technology extrapolation

How can we quickly develop the right design technology?How can we quickly develop the right design technology?answer: CAD-IP reuseanswer: CAD-IP reuse

Did I really solve the problem? Did I really solve the problem? Did the design process improve?Did the design process improve?

Did achievable design envelope get bigger? Did achievable design envelope get bigger?

answer: Metricsanswer: Metrics

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Design productivity gap threatens design Design productivity gap threatens design qualityquality

EDA industry must evolve and mature to achieve EDA industry must evolve and mature to achieve EDA EDA industry productivityindustry productivity

Open, shared infrastructure can restore Open, shared infrastructure can restore TAT, QOR of design TAT, QOR of design technologytechnology3 initiatives: Technology Extrapolation, CAD-IP Reuse, and 3 initiatives: Technology Extrapolation, CAD-IP Reuse, and

METRICSMETRICS

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OutlineOutline







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““We We MustMust Solve the Solve the CADCAD Productivity Challenges” Productivity Challenges”

““Death Spiral” is a bad local optimum configurationDeath Spiral” is a bad local optimum configurationnot enough value, not enough R&D, fragmentation of R&Dnot enough value, not enough R&D, fragmentation of R&D

The design The design qualityquality gap is just as dangerous as the design gap is just as dangerous as the design productivityproductivity gap gapASIC business model is at risk !ASIC business model is at risk !

Solution lies in maturity of the EDA industrySolution lies in maturity of the EDA industry““coopetitive” behavior of vendors and customers, togethercoopetitive” behavior of vendors and customers, together

Happiness

Future

Today

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Build the non-differentiating, open-source EDA foundationBuild the non-differentiating, open-source EDA foundation Bottom Up: data model (+API), concrete syntax (e.g., .lib + XML), tech Bottom Up: data model (+API), concrete syntax (e.g., .lib + XML), tech

extrapolation, silicon calibration/characterization, performance analyses, ...extrapolation, silicon calibration/characterization, performance analyses, ... EDPS, CHDStd, DAPIC experiences = useful foundationEDPS, CHDStd, DAPIC experiences = useful foundation world-wide cooperation needed (Japan/Asia, North America, Europe)world-wide cooperation needed (Japan/Asia, North America, Europe)

Understand that bottom-up commoditization of tools and Understand that bottom-up commoditization of tools and adapters is inevitableadapters is inevitable

Bottom Up: Analyses first (RCX, DC, STA), then Syntheses (S, P & R)Bottom Up: Analyses first (RCX, DC, STA), then Syntheses (S, P & R) pure tools $ static (?), but value remains in being best at leading edgepure tools $ static (?), but value remains in being best at leading edge enormous resource savings in duplicated R&D, maintenanceenormous resource savings in duplicated R&D, maintenance more value from integrations, methodologies, faster technology deliverymore value from integrations, methodologies, faster technology delivery

Long-term: EDA moves upward in value chainLong-term: EDA moves upward in value chain escapes “service” roleescapes “service” role becomes more aware, specific to markets, manufacturing processbecomes more aware, specific to markets, manufacturing process

““We We WillWill Solve the Solve the CADCAD Productivity Challenges” Productivity Challenges”

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““Who Will Pay?”Who Will Pay?”

Costs of cooperating are less than costs of Costs of cooperating are less than costs of notnot cooperating cooperating

Benefits of cooperation are immenseBenefits of cooperation are immensefree up brains to improve Design Technology TAT and QORfree up brains to improve Design Technology TAT and QOR

technology extrapolation + CAD-IP reuse + Metrics technology extrapolation + CAD-IP reuse + Metrics = delivery of solutions the right problems, at the right time, with = delivery of solutions the right problems, at the right time, with measurable impactmeasurable impact

We should We should welcomewelcome costs of openness, shared infrastructure costs of openness, shared infrastructureacademia, vendor + internal EDA, designer communities academia, vendor + internal EDA, designer communities togethertogether

It is a great future, if we make it happen !It is a great future, if we make it happen !

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THANK YOU !

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EXTRA SLIDES

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SynergiesSynergies

CAD-IPReuse

GTX

Metrics

Objective functions,tool QOR metrics

Estimates of best-optimized design, optimal

tradeoffs

Models, measuresof algorithmicactivity

Which problems are critical? What will

instances look like?

Optimized designprocesses,calibration data for modeling CADoptimization

Feasibility / sanitycheckers to embedwithin a tool flow

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GTX EngineGTX Engine

Contains no domain-specific knowledgeContains no domain-specific knowledge

Evaluates rules in topological orderEvaluates rules in topological order

Performs studiesPerforms studies

Multiple values through “sweeping”Multiple values through “sweeping”

Runs on three platforms (Solaris, Windows and Linux)Runs on three platforms (Solaris, Windows and Linux)

Parameters (data)

Rules (models)

Rule chain (study)

Knowledge

Engine (derivation)

GUI (presentation)

ImplementationUser inputs

Pre-packaged

GTX

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GTX Graphical User Interface (GUI)GTX Graphical User Interface (GUI)

Provides user interactionProvides user interaction

Visualization (plotting, printing, saving to file)Visualization (plotting, printing, saving to file)

4 views:4 views:ParametersParametersRulesRulesRule chainRule chainValues in chainValues in chain

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TheInternet

Sematech, GSRC

“The Golden Copy”

The World of the Living RoadmapThe World of the Living Roadmap

TechnologyModels

UniversityResearchers

ProprietaryModels

Firewall

Richard Newton

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Research in mature areas can stallResearch in mature areas can stallincremental research - difficult and risky incremental research - difficult and risky

implementations not available implementations not available duplicated effortduplicated effort

too much trust too much trust which approach is which approach is reallyreally the best the best??

some results some results may not may not bebe replicable replicable

‘‘not novel’ is common reason for paper rejectionnot novel’ is common reason for paper rejection

exploratory research - paradoxically, lower-riskexploratory research - paradoxically, lower-risk novelty for the sake of noveltynovelty for the sake of novelty

yet, novel approaches must be well-substantiatedyet, novel approaches must be well-substantiated

Pitfalls: questionable value, roadblocks, obsolete contextsPitfalls: questionable value, roadblocks, obsolete contexts

Challenges for Applied AlgorithmicsChallenges for Applied Algorithmics

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““What Are Some Concrete, Industry-Wide Steps?”What Are Some Concrete, Industry-Wide Steps?”First step: open mindsFirst step: open minds

Second step: agreements on scope of design activitySecond step: agreements on scope of design activitybound the interoperability problem by defining canonical design states, e.g.:bound the interoperability problem by defining canonical design states, e.g.:

cycle-accurate microarchitecturecycle-accurate microarchitecture gate-level placementgate-level placement global-routed but not detailed-routedglobal-routed but not detailed-routed

Third step: proofs that coopetition is feasibleThird step: proofs that coopetition is feasiblehow different or similar are (for example):how different or similar are (for example):

foundry process/rule description formats? library model generators?foundry process/rule description formats? library model generators? IDM/CHDStd, UDM, Genesis, MilkyWay, ...? IDM/CHDStd, UDM, Genesis, MilkyWay, ...? AWE, ramp-Elmore, etc. interconnect delay calculations?AWE, ramp-Elmore, etc. interconnect delay calculations?

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Where is the Solution ? (DAC-2000 Panel)Where is the Solution ? (DAC-2000 Panel)

Company A B C D E F G H

Cadence 25 10 5 10 10 25 15 0Synopsys 0 30 0 20 10 25 15 0Avant! 5 20 0 20 35 20 25 0Magma 0 10 0 0 50 0 40 0Aristo 5 10 20 30 10 0Sequence 0 0 0 20 50 15 15 0Monterey 7.5 10 7.5 50

25

15 10

A: RTL estimationB: RTL synthesis + optimizationC: gate-level estimationD: gate-level logic optimizationE: cell + wire sizing + physical support (e.g., P&R)F: block placement, floorplanning + wireplanning + budgetingG: gate-level place and routeH: other

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Perfect Rectilinear FloorplanningPerfect Rectilinear Floorplanning

Fixed-die planningFixed-die planning: find a coarse global floorplan, then : find a coarse global floorplan, then migrate whitespace migrate whitespace overlap such that both disappear overlap such that both disappear

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See, for example: http://vlsicad.cs.ucla.edu/SLIP2000/See, for example: http://vlsicad.cs.ucla.edu/SLIP2000/

KnMn

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What Does Process Variability Imply for EDA ?What Does Process Variability Imply for EDA ?

VERY DIFFICULT PROBLEMS !VERY DIFFICULT PROBLEMS !We require much deeper understanding of processWe require much deeper understanding of process

coma effects (lens aberration)coma effects (lens aberration)halation (iso-dense effects on etch dynamics)halation (iso-dense effects on etch dynamics)statistical variation in ion implantstatistical variation in ion implant

Performance verification infrastructure may changePerformance verification infrastructure may changeE.g., “delay” is no longer a number – it is a distributionE.g., “delay” is no longer a number – it is a distribution

Must have complete, integrated, front-to-back solutionsMust have complete, integrated, front-to-back solutionsAll three examples: OPC, PSM, Area FillAll three examples: OPC, PSM, Area Fill

Long-term: must drive process requirements from system Long-term: must drive process requirements from system architecture and design technology roadmapsarchitecture and design technology roadmaps

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Five different interconnect modelsFive different interconnect modelsBakoglu’s model (RC)Bakoglu’s model (RC) [Alpert, Devgan and Kashyap, ISPD 2000] (RC)[Alpert, Devgan and Kashyap, ISPD 2000] (RC) [Ismail, Friedman and Neves, TCAD 19(1), 2000] (RLC)[Ismail, Friedman and Neves, TCAD 19(1), 2000] (RLC) [Kahng and Muddu, TCAD 1997] (RLC)[Kahng and Muddu, TCAD 1997] (RLC)Extension of [Alpert, Devgan and Kashyap, ISPD 2000] (RLC)Extension of [Alpert, Devgan and Kashyap, ISPD 2000] (RLC)

RC and RLC Interconnect Delay ModelsRC and RLC Interconnect Delay Models

25

75

125

175

225

3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Wire Length (mm)

Wir

e D

elay

(p

s)

RC_ADK

RC_B

RLC_ADK

RLC_IFN

RLC_KM

HSPICE

25

45

65

85

105

125

145

0.4 0.6 0.8 1.0 1.2 1.4

Wire Width (µm)

Wir

e D

elay

(p

s)

RC_ADK

RC_B

RLC_ADK

RLC_IFN

RLC_KM

HSPICE

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Generic and Specific Tool MetricsGeneric and Specific Tool Metrics

tool_name stringtool_version stringtool_vendor stringcompiled_date mm/dd/yyyystart_time hh:mm:ssend_time hh:mm:sstool_user stringhost_name stringhost_id stringcpu_type stringos_name stringos_version stringcpu_time hh:mm:ss

Generic Tool Metricsnum_cells integernum_nets integerlayout_size doublerow_utilization doublewirelength doubleweighted_wl double

num_layers integernum_violations integernum_vias integerwirelength doublewrong-way_wl doublemax_congestion double

Placement Tool Metrics

Routing Tool Metrics

Partial list of metrics now being collected in Oracle8i

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Example Testbed: Cadence SLC FlowExample Testbed: Cadence SLC Flow

DEF

Placed DEF

QP

Pearl

METRICS

QP Opt

CTGen

Incr.

Routed DEF

WRoute

Optimized DEF

LEFGCF,TLF

Clocked DEFConstraints

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Current Status of METRICS InitiativeCurrent Status of METRICS Initiative

Current statusCurrent statuscomplete prototype of METRICS system with Oracle8i, Java Servlet, complete prototype of METRICS system with Oracle8i, Java Servlet,

XML parser, and transmittal API library in C++XML parser, and transmittal API library in C++METRICS wrapper for Cadence and Cadence-UCLA flows, front-end METRICS wrapper for Cadence and Cadence-UCLA flows, front-end

tools (Ambit BuildGates and NCSim)tools (Ambit BuildGates and NCSim)easiest proof of value: via use of regression suiteseasiest proof of value: via use of regression suites

Issues for METRICS constituencies to solveIssues for METRICS constituencies to solvesecurity: proprietary and confidential informationsecurity: proprietary and confidential informationstandardization: flow, terminology, data management, etc. standardization: flow, terminology, data management, etc. social: “big brother”, collection of social metrics, etc.social: “big brother”, collection of social metrics, etc.

Ongoing work with EDA, designer communities to identify tool Ongoing work with EDA, designer communities to identify tool metrics of interestmetrics of interestusers:users: metrics needed for design process insight, optimization metrics needed for design process insight, optimizationvendors: vendors: implementation of the metrics requested, with standardized implementation of the metrics requested, with standardized

naming / semanticsnaming / semantics

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GTX Current StatusGTX Current StatusModels implementedModels implemented

cycle-time models of SUSPENS (with extension by Takahashi), BACPAC cycle-time models of SUSPENS (with extension by Takahashi), BACPAC (Sylvester, Berkeley), Fisher (ITRS)(Sylvester, Berkeley), Fisher (ITRS)

currently addingcurrently adding GENESYS (with help from Georgia Inst. Tech.)GENESYS (with help from Georgia Inst. Tech.) RIPE (with help from Rensselaer Univ.)RIPE (with help from Rensselaer Univ.)

new device and power modules (Synopsys / Berkeley)new device and power modules (Synopsys / Berkeley)new SOI device model (Synopsys / Berkeley)new SOI device model (Synopsys / Berkeley) inductance models (Silicon Graphics / Berkeley / Synopsys)inductance models (Silicon Graphics / Berkeley / Synopsys)yield and die cost models (CMU)yield and die cost models (CMU)

Studies performed in GTXStudies performed in GTXmodel and parameter sensitivity analysesmodel and parameter sensitivity analysesdesign optimization studiesdesign optimization studies

Seeking contributions, suggestions of new models, studiesSeeking contributions, suggestions of new models, studies

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