1 COMP541 State Machines - II Montek Singh Feb 13, 2012 Todays Topics Lab preview: Debouncing a switch Debouncing a switch Verilog styles for FSM Dont forget to check synthesis output and console msgs. Dont forget to check synthesis output and console msgs. State machine styles Moore vs. Mealy Moore vs. Mealy 2 Lab Preview: Buttons and Debouncing Mechanical switches bounce vibrations cause them to go to 1 and 0 a number of times vibrations cause them to go to 1 and 0 a number of times called chatter hundreds of times! hundreds of times! We want to do 2 things: Debounce: Any ideas? Debounce: Any ideas? Synchronize with clock Synchronize with clock i.e., only need to look at it at the next +ve edge of clock Think about (for Wed class): What does it mean to press the button? Think carefully!! What does it mean to press the button? Think carefully!! What if button is held down for a long time? What if button is held down for a long time? 3 Beware the unintended latch! Very easy to unintentionally specify a latch/register in Verilog! one of the most common mistakes! one of the most common mistakes! one of the biggest sources of headache! one of the biggest sources of headache! you will do it a gazillion times you will do it a gazillion times this is yet another result of the the hangover of software programming this is yet another result of the the hangover of software programming forgetting everything in hardware runs in parallel, and time is continuous Solution good programming practice good programming practice 4 Beware the unintended latch! Example: multiplexer out is output of combinational block out is output of combinational block no latch/register is intended in this circuit no latch/register is intended in this circuit recommended Verilog: recommended Verilog: assign out = select? A : B; But, an if statement (inside an always block) will incorrectly introduce a reg: if (select) out