© 2012
Copyrights © Yole Developpement SA. All rights reserved.
2.5D interposer, 3DIC and TSV Interconnects Applications, market trends and supply chain evolutions
Dr Lionel Cadix [email protected]
Infineon
Micron
Synopsys VTI
CEA LETI
Xilinx
© 2012 • 2
Copyrights © Yole Developpement SA. All rights reserved.
Outline
• Introduction
• Global 3D TSV market forecast
• Infrastructure & Supply Chain
• Market & application focus
• Conclusions and perspectives
© 2012 • 3
Copyrights © Yole Developpement SA. All rights reserved.
Introduction
© 2012 • 4
Copyrights © Yole Developpement SA. All rights reserved.
Moore is less… Transition to 3D
Cost ?
Performance ?
Size ?
Despite “no more Moore” the quest remains
The rapid evolution of 3D thinking in the IC community is astonishing
– Two years ago, the big question was “Why 3D?”
– One year ago, the questions were “When 3D?” and “How 3D?”
– In less than a decade from now, we will wonder “Why 2D?”
Which will determine “when” and “how” 3D happens
© 2012 • 5
Copyrights © Yole Developpement SA. All rights reserved.
« 3 kinds of 3D »
Advanced Packaging Platforms
RDL
Bumping Balling
Wafer Bonding
TSV
WL-Optics
WL-Capping
2.5D Interposer
3DIC
Balling
WLCSP FO
WLP Embedded
IC Flip Chip
MEMS IC
Capping
IC
Sensor
Memory
Logic
3D WLCSP
Die 1 Die 2 Die 3 Die 4
Middle-End Process Steps
© 2012 • 6
Copyrights © Yole Developpement SA. All rights reserved.
Global 3DIC
Market forecast
© 2012 • 7
Copyrights © Yole Developpement SA. All rights reserved.
-
2,000,000
4,000,000
6,000,000
8,000,000
10,000,000
2010 2011 2012 2013 2014 2015 2016 2017
Waf
er c
ou
nt
(12
’’e
q.)
Global TSV Chip Wafer Forecast (All 3D Platforms) Breakdown by Segment (12''eq wafers)
3D Stacked NAND Flash
3D Wide IO Memory
Logic 3D SiP / SoC
3D Stacked DRAM
MEMS / Sensors
LED
RF, Power, Analog &Mixed signal
Imaging &Optoelectronics
Yole Developpement © July 2012
Global TSV Chip Wafer Forecast Breakdown by segment (12’’eq. Wafers)
© 2012 • 8
Copyrights © Yole Développement SA. All rights reserved.
0
20
40
60
80
100
120
140
Rev
enu
es (
M$
)
2011 global 3D TSV revenues* - Including internal production lines -
Breakdown by top players (M$)
3DIC
2.5D Interposer
3D WLCSP
*Other Nemotek, Q-Tech, ITRI, Toyota, Honda Research Institute, Sematech, UMC, Toshiba, TI
2011 Global 3D TSV Revenues Breakdown by top players
• As of 2011, the top three players for 3D TSV revenues were involved in 3D WLCSP activity
– Xintec is the top player by far, with $130M
– However, this picture will change soon as important revenues are generated over the next few years with 3DIC and
2.5D Interposer products
* Middle-end activity revenues including
TSV etching, Filling, RDL, Bumping,
wafer test & wafer level assembly
2011 total 3D TSV activity
revenues ~ $344 Million
© 2012 • 9
Copyrights © Yole Développement SA. All rights reserved.
3D WLCSP: the Most Mature 3D TSV Platform
• 3D WLCSP is the preferred solution today for the efficient assembly of small-size optoelectronic
chip like CMOS image sensors. At the moment, it is also the most mature 3D TSV platform, as we
estimate the market to be ~ $272M in 2011 for the “middle-end” processing factories serving this
specific market.
• More than 90% of the revenues in this area
come from low-end and low-resolution
CMOS image sensors manufacturing
(typically CIF, VGA, 1MPx and 2MPx
sensors). Xintec in Taiwan is the leader for
3D WLCSP packaging today, followed by
China WLCSP, Toshiba and JCAP.
• Main features
– Mostly 200mm wafer-level packaging
industrial infrastructure
– Important investments are still expected
from major companies moving to 300mm.
Indeed, this move to 12” is necessary to
move to the high-end CMOS image sensors
market (> 8MPx resolution) where sensors
are today on the transition from backside
illumination to real 3DIC packaging
architecture which we will soon call « 3D
BSI », where photodiodes are vertically
stacked directly onto the DSP / ROIC wafer
and connected by means of TSVs.
Xintec $130.0M
48%
China WLCSP $66.0M
24%
Toshiba $26.7M
10%
JCET/JCAP $21.6M
8%
Samsung $18.2M
7%
STMicroelectronics $2.3M
1% Others* $5.3M
2%
2011 3D WLCSP platform Middle-End revenues* Including internal production lines
Breakdown by top players (M$)
Yole Developpement © July 2012
* Middle End activity revenues including TSV
etching, Filling, RDL, Bumping, wafer test & wafer level assembly
Total =
$272M
*Others = Oki, G-MEMS,
Nemotek, Q-Tech
© 2012 • 10
Copyrights © Yole Développement SA. All rights reserved.
2.5D interposer 2010-2017 wafer forecasts breakdown by component/IC type
-
500,000
1,000,000
1,500,000
2,000,000
2,500,000
3,000,000
2010 2011 2012 2013 2014 2015 2016 2017
APE/BB (Smartphone) - - - - - - - 59,641
CIS & Camera Module - - - - - - 19,585 41,889
CPU - - - - 34,184 62,089 98,244 146,623
APE (Tablet) - - - 17,274 59,865 117,049 202,125 308,461
GPU - - - 54,435 171,382 284,538 464,144 662,037
Other Logic (ASIC, FPGA, ASSP …) - - 9,734 89,273 223,832 438,331 670,290 970,722
MEMS (3D Capping) - 1,241 1,899 8,048 31,411 59,825 92,521 127,943
High Power LED (3D Silicon Substrate) 4,395 8,759 18,890 45,188 91,101 159,569 232,887 237,715
RF Devices (Filtering, IPD etc.) 10,952 13,863 18,869 26,534 35,753 46,422 58,540 77,706
Waf
er c
ou
nt
(12
''eq
. waf
ers)
2.5D Interposer platform wafer forecast
breakdown by IC type (12''eq.wafers)
Yole Developpement © July 2012
TOTAL (12''eq. Wafers) 15 347 23 863 49 392 240 753 647 527 1 167 823 1 838 337 2 632 736
• 2.5D Interposer with system partitioning applications are expected to be the
biggest drivers for the volume adoption of 3DIC technology in the next five
years
• The motivations to adopt the “partitioning approach” using 2.5D Interposers
are: – Better electrical performance
– Better yield
– Reduced cost
© 2012 • 11
Copyrights © Yole Développement SA. All rights reserved.
The Future 3DIC Market is Driven
by Stacked Memories & Logic SOC Applications
• 3DIC technology is seen today as a new paradigm for the future of the semiconductor
industry, as it will enable several more decades of chip evolution at ever lower cost, higher
performance and smaller-size features
– 3D stacked DRAM and 3D Logic SOC applications are expected to be the biggest drivers for the
volume adoption of 3DIC technology followed by CMOS image sensors, power devices and MEMS
DRAM $363 M
22%
Wide IO Memory $325 M
19%
Logic SoC (APE, BB/APE) $404 M
24%
NAND Flash Memory $66 M
4%
CIS $63 M
4%
Low-End ASIC $110 M
7%
Power Devices (IGBT, PA, PMU)
$172 M 10%
Other Logic (ASIC, FPGA, ASSP …) $76 M
5%
MEMS/Sensor $87 M
5%
3DIC Platform Middle-End Revenues by 2017 (M. US$) Breakdown by IC type
* Middle-end activity revenues including TSV,
Filling, RDL, Bumping, wafer test & wafer level
assembly
Yole Developpement © July 2012
Total =
$1.7B
© 2012 • 12
Copyrights © Yole Developpement SA. All rights reserved.
Infrastructure
&
Supply Chain Analysis
© 2012 • 13
Copyrights © Yole Developpement SA. All rights reserved.
Traditional IC Packaging Supply Chain*
System /
Product
Sub-Module /
Sub-systems Design & Assembly
Design of chip & package
Wafer Level
Packaging « Middle -end »
Silicon Manufacturing
« Front-end »
Package Assembly
& Final test « Back-end »
Front-end related
materials suppliers
OEMs (Original
Equipment
Makers)
FE related
equipment suppliers
BE Packaging
materials suppliers
BE Packaging
equipment suppliers
Fab-less
IC players
IDMs (Integrated Device Manufacturers)
Wafer foundries
OSATs (Open Source Assembly & Test houses)
Wafer Bumping
houses
BE assembly & Test houses
PWB suppliers (motherboard)
ODM / EMS / DMS
(electronic design &
manufacturing services)
SiP module houses
Passive comp. & SMT materials
SMT equipment
suppliers
SiP design
houses
Test houses
Package substrate
laminate suppliers
Substrate material suppliers (FR4, BT resin, Cu clad, etc…)
* Main business models
represented in red
WLP houses (no need for traditional substrate)
© 2012 • 14
Copyrights © Yole Developpement SA. All rights reserved.
Transforming IC Packaging Supply Chain*
System /
Product
Sub-Module /
Sub-systems Design & Assembly
Design of chip & package
Wafer Level
Packaging « Middle -end »
Silicon Manufacturing
« Front-end »
Package Assembly
& Final test « Back-end »
Front-end related
materials suppliers
OEMs (Original
Equipment
Makers)
FE related
equipment suppliers
BE Packaging
materials suppliers
BE Packaging
equipment suppliers
Fab-less
IC players
IDMs (Integrated Device Manufacturers)
Integrated wafer / package manufacturing foundries
OSATs (Open Source Assembly & Test houses)
WLP houses (no need for traditional substrate)
PWB suppliers (motherboard)
ODM / EMS / DMS
(electronic design &
manufacturing services)
Passive comp. & SMT materials
SMT equipment
suppliers
SiP design
houses
Package substrate
laminate suppliers
Substrate material suppliers (FR4, BT resin, Cu clad, etc…)
* Existing business models represented in red, new
business models in orange
Wafer
foundries
Fab-smart players (foundry services + focused internal investment in manufacturing & critical IP)
Wafer Bumping houses PCB / PWB houses with Embedded die capability
© 2012 • 15
Copyrights © Yole Developpement SA. All rights reserved.
Transforming IC Packaging Supply Chain*
System /
Product
Sub-Module /
Sub-systems Design & Assembly
Design of chip & package
Wafer Level
Packaging « Middle -end »
Silicon Manufacturing
« Front-end »
Package Assembly
& Final test « Back-end »
Front-end related
materials suppliers
OEMs (Original
Equipment
Makers)
FE related
equipment suppliers
BE Packaging
materials suppliers
BE Packaging
equipment suppliers
Fab-less
IC players
IDMs (Integrated Device Manufacturers)
Integrated wafer / package manufacturing foundries
OSATs (Open Source Assembly & Test houses)
WLP houses (no need for traditional substrate)
PWB suppliers (motherboard)
ODM / EMS / DMS
(electronic design &
manufacturing services)
Passive comp. & SMT materials
SMT equipment
suppliers
SiP design
houses
Package substrate
laminate suppliers
Substrate material suppliers (FR4, BT resin, Cu clad, etc…)
* Existing business models represented in red, new
business models in orange
Wafer
foundries
Fab-light players (outsourcing + focused investment in manufacturing & critical IP)
Wafer Bumping houses PCB / PWB houses with Embedded die capability
© 2012 • 16
Copyrights © Yole Developpement SA. All rights reserved.
3D IC & TSV
Market & Application Focus
© 2012 • 17
Copyrights © Yole Developpement SA. All rights reserved.
What are the Markets for 3D ICs?
• 3D integrated ICs will be introduced in a variety of applications, all with their own
specifications, challenges and individual roadmaps!
High Volumes
Lower Volumes
3D IC opportunities
High-end Multimedia
Smart-phones / PMP
High-density
Solid State
Storage & µ-Cards
Notebooks / MID
‘connectivity’ devices
Gaming / Graphic
application engines
High-performance
computers / Network &
Storage components /
Green Data servers
High-performance
Digital Video
Wireless
Connectivity /
Network Center
Automotive Medical
© 2012 • 18
Copyrights © Yole Développement SA. All rights reserved.
3D TSV Application Segmentation
Imaging
LED
MEMS &
Sensors HB-LED Stacked
memories
RF, Power,
Analog &
Mixed Signal
Logic 3D-
SiP/SoC
3D TSV Applications
WLP CIS
BSI CIS
Wafer level
auto-focus
3D integrated
CIS
Gyros
Acceleros
Pressure sensors
Si-micro
FBAR filters
Oscillators
µProbes
µFluidic / IJ
µValves
Fingerprint
sensors
Micro-mirrors
IR-bolometer
Opto (laser, VCSEL)
Mobile µ-Flash
Automotive
General Lighting
Projection engine
PA
MOSFET
IGBT
IPD
DC-DC
converters
Stacked DRAM
StackedNAND
Flash
StackedNOR /
PCRAM
3D SoC
Baseband / DSP
MCU / Processors
Touchscreen
controller
Low-end ASICs
PMIC
3D SiP
Wide IO BB
CPU / GPU
FPGA
High. Perf ASICs
© 2012 • 19
Copyrights © Yole Developpement SA. All rights reserved.
PA
Capping IPD Sapphire or
Silicon 3D IPD MOSFET
IGBT & Power MOSFET Power GaN
2012 2014 2016 2018
CIS DSP SOC CIS
BSI CIS
DSP + mem DSP
mem
CIS
SOC CIS
2010 2011 2013 2015 2017 2019
3D
WLCSP
FSI
BSI
< 2009 2009
MEMS
ASIC MEMS
Capping
MEMS
ASIC Analog/RF
MEMS Logic
MEMS
Capping
FBAR
Capping
DDR3 stack Hybrid Memory Cube
NAND Flash stack Wide IO stack
LED
Driver
LED
Driver
LED LED
LED LED LED IPD
FPGA FPGA FPGA FPGA
Analog Digital RF Mem. Analog
Digital
ASIC MEMS
Analog
Digital
RF
Mem.
Wide IO FPGA
Wide IO APE
Wide IO
APE
CPU
DDR3 stack
GPU DDR3
Logic
Logic
Logic 3D
SiP/SoC
Global 3DIC & TSV roadmap
MEMS & Sensors
Imaging & Opto
Power,
Analog
& RF
Stacked
Memories
HB-LED
modules
3D SoC
3D SiP Ultimate
Heterogeneous
3DIC
SOC CIS
SOC CIS
© 2012 • 20
Copyrights © Yole Développement SA. All rights reserved.
Silicon/Glass 3D Interposer Technology Segments
• We identified the following technology
segments for 3D interposers:
– MEMS and sensors 3D capping interposers
– “System partitioning” interposers
– Interposers for CMOS image sensors
– 3D LED silicon substrates
– 3D Integrated Passive Devices (IPDs)
– Miscellaneous interposers
« System partitioning » interposers
MEMS & sensor 3D
capping inteposers 3D LED silicon submounts
3D integrated passive devices
Interposers for CMOS image sensors
Miscellaneous interposers
© 2012 • 21
Copyrights © Yole Développement SA. All rights reserved.
2012 hottest topic: « System-Partitioning » Interposers Definition and drivers
• « System-partitioning » Interposers enable the integration of at least one logic IC with one or
several memory Ics, and possible even mixed signal or analog ICs
• They will progressively replace monolithic SoC, or SiP
• Adoption of « system-partitioning » Interposers is driven by – Performance
• Electrical performance is enhanced by placing the various ICs close to one another and by interconnecting them with very high-density
and large IO buses, thus enabling high bandwidth between the neighboring ICs on the interposer
• From a thermal standpoint, 2.5D integration enables similar benefits to those of 3D integration, without the thermal drawbacks of
overheating of 3D integration
• In addition, « system-partitioning » Interposers can act as heat spreaders across the package surface area
– Cost
• Each stacked circuit is built using a
specific technology tailored to its
function (memory, logic, etc.)
– Yield
• Some large logic chips can be cut down into several
circuits with higher front-end
manufacturing yields
• Lead applications for
« system-partitioning » are GPUs,
FPGAs, large ASICs and
APE+memory for tablets
• « System-partitioning » Interposers are generally large (exceeding 20x20mm²)
PCB
Memory Logic Analogue Silicon
interposer
BGA Laminate
© 2012 • 22
Copyrights © Yole Développement SA. All rights reserved.
Interposers for FPGA Focus on Xilinx Virtex 7 HT
• Last fall, Xilinx announced a single-layer, multi-chip silicon interposer for its 28nm 7 series
FPGAs
• Key features
– Two million logic cells for a high level of computational performance ,and high bandwidth
– Four slice processed in 28 nm
– 25 x 31mm, 100 µm thick silicon Interposer
– 45 um pitch microbumps and 10 µm TSV
– 35 x 35 mm BGA with 180 µm pitch C4 bumps
• Even if the infrastructure
had been ready for full 3D
stacking, the 2.5D
Interposer would still have
been the right choice for
FPGAs since the “10,000
routing connections” would
have used up valuable chip
area, making the chip slices
larger and more costly than
they are now
• Virtex 7 HT will consist of three FPGA slices and two 28 gbps SerDes chips on an Interposer
capable of operating at 2.8 Tb/sec!
Source: Yole Developpement & Phil Garrou for iMicronews
Courtesy of Xilinx
© 2012 • 23
Copyrights © Yole Développement SA. All rights reserved.
Interposers for Large CPUs and GPUs
• Limitation/Bottleneck in conventional 2D architecture – Beyond eight cores, processors will lose performance benefits in a 2D configuration. This is a
fundamental bottleneck that IBM and Intel are working on
2D SoC partitioning and use of 2.5D Interposers will be soon be mandatory for increasing the
performance of high-performance computers!
• Power 8 by IBM will be based on 2.5D Interposers
• Haswel, Intel GPU on 2.5D Interposers for laptops, with lots of on-board memory
and an ultra-large data bus
IBM Power 7+: four 32nm CMOS
multi-core CPU dies are placed
side by side on a silicon
Interposer. (Courtesy of
SemiAccurate.com)
Cross-section pictures of an IBM 3D stacked module demonstrator with TSVs in the thinner die
(courtesy of Chipworks)
© 2012 • 24
Copyrights © Yole Développement SA. All rights reserved.
Networking Applications Cisco seriously considering silicon Interposers
• Because higher memory bandwidth is needed
for networking applications, and because
steppers limit the size of silicon Interposers to
a max. of 26x32mm (as estimated by Cisco),
Cisco proposes a new architecture: the 3D SiP,
with naked dies mounted on both sides of the
Interposer
• As of Q2/2012, Cisco is still building test
vehicles with ITRI, and is still concerned with
thermal management issues
•
The 3D SiP architecture hosts bare dice on both sides of the Interposer
(cross-section drawing and top view) , Source: Cisco and ITRI, ECTC 2012
© 2012 • 25
Copyrights © Yole Développement SA. All rights reserved.
GPU for Gaming • Sony’s PS4 (2013) will have its GPU and memory stacked on a 2.5D Silicon Interposer with a
512-wide data bus. This will likely be an AMD chip
• Future gaming platforms will offer 3D imagery, which requires fast & high bandwidth
computing power
• 2.5D is unanimously praised as the solution for this purpose
• “GPU-RAM bandwidth is the key factor
for rendering performance” – Sept 2011,
Teiji Yutaka , SVP Technology Platform,
Sony Computer Entertainment
An Interposer module for (Yole’s assumption) an AMD GPU
demonstrator, Courtesy of Global Foundries, 2012
© 2012 • 26
Copyrights © Yole Developpement SA. All rights reserved.
Interposers technical and marketing segmentation and status
Technical segments
“System
partitioning”
interposers
MEMS and sensor
3D capping
interposers
Interposers for
CMOS image
sensors
3D LED silicon
substrates
3D Integrated
Passive Devices
(IPDs)
Miscellaneous
interposers
Mobile/wireless Application processor +
memory for tablets in
2013
HVM since 2011 BSI with interposer
in 2012
Emerging Emerging for RF
front-end and
DC/DC converters
Silicon PoP?
Gaming GPUs in 2014. CPUs in
2015
HVM since 2011
Industrial and
medical
FPGA in 2012, High perf
processors in 2014
Silicon substrates & IPDs for medical?
PCs GPUs in 2013, CPUs in
2015
Voltage regulators.
In research phase
Data centers &
servers
CPUs in 2014 Voltage regulators.
In research phase
Wired telecom
infrastructure
FPGA in 2012, ASICs in
2015
Wireless telecom
infrastructure
? ?
Home consumer (DSC, MP3, TV, white
goods)
FPGA 2012 in smart TV BSI with interposer
in 2012
Aerospace/mil/hi
reliability
ASICs in 2017 Silicon substrates
for high temp
operation?
Automotive FPGA and ASICs in 2018 Emerging ?
General lighting Emerging
En
d A
pp
licati
on
© 2012 • 27
Copyrights © Yole Developpement SA. All rights reserved.
Summary: Interposers expected applications production roadmap
2010 2011 2012 2013 2014 2015 2016 2017 2018
BAW filters, RF devices
LED silicon substrates
FPGAs, networking,
& storage & HDTV ASICs
GPUs
APEs (in tablets)
CPUs
CMOS
image sensors
APEs
(smartphones)
?
© 2012 • 28
Copyrights © Yole Developpement SA. All rights reserved.
Conclusion & Perspectives
© 2012 • 29
Copyrights © Yole Developpement SA. All rights reserved.
Main Conclusions Market & Applications
• 3DIC technology is considered today as a new paradigm for the future of the semiconductor
industry!
– 3DIC will enable several more decades of chip evolution at ever lower cost, higher performance and
smaller-size features
• 3D stacked DRAM & 3D Logic SOC = biggest drivers for volume adoption of 3DIC technology
– Today, the market is driven by high-end applications using 2.5D partitioning Interposers
– Large-die FPGAs and ASICs are on the way to being commercialized for industrial applications, and
are also expected to grow in the near future in the gaming and smart TV markets
• 2013 will likely be the key turning point for the first true implementation of 3DIC technology
in significant volume, driven by the commercialization of HMC
• In terms of value, the 3D TSV market will reach $40B in 2017, growing more than 10 times
faster than the global semiconductor industry!
Cost
Performance
Size
© 2012 • 30
Copyrights © Yole Developpement SA. All rights reserved.
Main Conclusions Supply Chain
• Many supply-chain possibilities for 2.5D/3DIC integration
• Innovative business model evolutions
– Leading wafer foundries are now extending to package, assembly & test integrated
services
– Large IDMs have now opened full turnkey manufacturing services to bring key design
wins and manufacturing volume from leading IC fabless/fab-light companies in-house
– Leading packaging, assembly & test houses have the possibility of developing their own
2.5D / 3DIC technology ecosystems
• For the players unable to develop vertically into front-end/middle-end/back-end
assembly & test, there is an urgent need to settle a genuine collaborative
ecosystem
• Key challenge for these future ‘virtual IDM’ ecosystems
– To determine the ownership and responsibilities between each party involved in the
manufacturing process flow
– To develop several different flexible supply chains with fair value distribution
© 2012
Copyrights © Yole Developpement SA. All rights reserved.
Thank you for your kind attention !
Infineon
Micron Synopsys VTI
CEA LETI
Xilinx