Analog Behavioral Modeling

Sathishkumar Balasubramanian

Senior Manager, Solutions Marketing, Cadence

Technology on Tour, Singapore

July 25th , 2013

2 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Agenda

1. Mixed-signal Overview

2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL)

3 Model Generation and Validation

4. Demo: Schematic Model Generator(SMG)

5. Demo: AMS Design & Model Validation (amsDmv)

6. Conclusions

3 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Today’s needs are vast and complex

Mixed Signal Testbench

Measure

Design

How do I measure

the quality of analog

verification?

How do I verify the mixed-

signal interconnects?

How do I verify the digital

content in this SoC?

Analog

Design

How do I model analog

behavior efficiently?

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• Verification is biggest overall challenge in mixed-signal design

• Many of silicon re-spins could be prevented by better verification

MS Verification Challenge

Cause of Silicon Re-spins

Biggest Challenge in MS Verification

Main Design Challenges

Preventable by

better Verification

Methodology

5 © 2013 Cadence Design Systems, Inc. Cadence confidential.

• The performance gap between analog simulation and digital is ever-widening

• Analog simulation does not scale to IC/SoC level

Mixed signal simulation performance

1Tx 1x 10x 100x 10Kx

SPICE

FAST SPICE

AMS-HDL Models

1Kx

Digital Simulators/Emulators

Performance Gap

Event based

1Gx

Matrix based

Relative Simulation Performance

Circuit Complexity

Ru

n T

im

e

SPICE FASTSPICE

HDLsim

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Key Elements of MS Verification Solution

Assertion, Coverage and Metric-Driven Methodology

Behavioral Modeling

Simulation

Continuous advancements

in performance and features Methodology, library and

tools abstracting analog

and mixed-signal

functionality to higher level

New, Digital-like

Methodology applied on

analog and mixed-signal Integrated Environment

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Bridging the mixed signal divide

• Behavioral models used for functional verification – Real number models offer analog functionality at digital speeds

– Models are easily used in the Virtuoso and Incisive environments

• Pin/Bus communication abstracted to the transaction-level

Benefits: Increased Predictability, Productivity and Quality

Validate Models to

Circuit (amsDMV)

Analog Domain Digital Domain

D Behavioral Model

(RNM)

Transistor level

Schematic

D

D

D

D

D

D

D

R

Testbench

Mixed Signal Verification

A

Schematic Model

Generation

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• AMS Designer is a single kernel mixed-signal simulator – Flexible Use Model ( GUI / Command-line )

– Choice of Analog solvers (Spectre® / Ultrasim / APS )

– Configurable Interface Elements

Flexible simulation using AMS Designer Unifying analog and digital engines

AMS-Analog Design Environment

(Virtuoso GUI integration)

• AMS in Analog Design

Environment

• (OSS->UNL+irun)

IC & IUS

AMS-irun (AIUM)

(Incisive batch mode regression)

irun

+ amsd block

IUS only

AMS Designer AMS-Ultra & AMS-Spectre®

AMS-APS

9 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Agenda

1. Mixed-signal Overview

2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL)

3 Model Generation and Validation

4. Demo: Schematic Model Generator(SMG)

5. Demo: AMS Design & Model Validation (amsDmv)

6. Conclusions

10 © 2013 Cadence Design Systems, Inc. Cadence confidential.

• Enable high-speed simulation of analog/mixed-signal blocks by using real numbers (floating-point) for signal values in discrete-time, event-driven simulation

• Removes the analog solver dependency from mixed signal verification

• Can be written by analog designers and/or digital verification engineers

• Enables digital verification techniques for analog/mixed signal blocks – Assertion-based verification

– Coverage driven verification

– Metric driven verification

– Reusable analog verification components (UVM-MS)

• Differs from analog behavioral languages (like Verilog-A) since targeted for higher level of integration/testing (IC/SoC)

• Possible RNM languages include – Verilog-AMS (wreal and Verilog subset)

– VHDL

– SystemVerilog

Real number modeling

11 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Continuous

Discrete

Analog modeling abstraction trade-offs

Speed

Accuracy

101

102

104

108

Multiple abstractions required for high confidence in design

Electrical

Real

Logic

SPICE

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• Several languages to choose from: Verilog-AMS, SystemVerilog, VHDL – Several ways to reach your goals

– Cadence has robust language support

• Start with Verilog-AMS wreals – Works well in Virtuoso

– Allows porting from Verilog-A performance models to RNM

– Provides for a compatibility path to SystemVerilog Real (to new IEEE P1800 standard) for SoC verification teams

– Application note available today

• Technical details available if needed

Real number modeling language choices

13 © 2013 Cadence Design Systems, Inc. Cadence confidential.

• Combining the best features of VHDL and Verilog-AMS real number modeling in SystemVerilog – IEEE 1800-2012 was released in February 2013

– Cadence contributed to SV-DC additions

• New features enable robust real number modeling

• New features overcome issues with prior versions of SystemVerilog (2009 and prior LRM) – Real number nets

– Bi-directional real connections

– Multiple RNM contributors to the same net

– Modeling complex information on a single net (eg. Voltage and current)

New 2012 SystemVerilog connectivity features Driven by the IEEE 1800 SV-DC committee

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• Can carry one or more (real) values over a single net – Can be used to communicate voltage, current or other values

between design blocks

• User-defined resolutions (UDR) functions used to combine multiple outputs together

SystemVerilog used-defined nets

Analog

Behavioral

Model (SV)

Analog

Behavioral

Model (SV) Real-value

nettype

V(out) V(in)

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• IEEE 1800-2009 supports real variable port connections – Restricted to input and output only (no inout)

– Real value connections restricted to variables (multiple net contributors not allowed)

• Difference between variables and nets – Variables store value (new assignments overwrite previous values)

– Nets are used for structural connections and allow for resolution of multiple drivers

Why do we need UDTs/UDRs?

Analog

Behavioral

Model (SV)

Analog

Behavioral

Model (SV) Real variable

Analog

Behavioral

Model (SV)

16 © 2013 Cadence Design Systems, Inc. Cadence confidential.

• Internal Example: Compare 14bit ADC + 14 bit DAC in transistor and in RNM – We exercise and simulate all possible conversions of the ADC and

DAC. Because there are 14 bits, the number of conversions to simulate is 2**14=16384 steps.

– Transistor performance: several days

– RNM performance: 3 seconds

• TI success story on cadence.com

RNM performance case study

A2D D2A

“Analog”

Real

Input

“Analog”

Real

Output

Bit

0

Bit

13

V(in)

V(out)

17 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Agenda

1. Mixed-signal Overview

2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL)

3. Model Generation and Validation

4. Demo: Schematic Model Generator(SMG)

5. Demo: AMS Design & Model Validation (amsDmv)

6. Conclusions

18 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Problem Statement

• Customers concerned about behavioral modeling effort for analog/mixed signal designs

• The current methodology – write the behavioral text in a text editor – is not acceptable to many analog/mixed signal designers

• Analog designers prefer a “graphical” viewpoint of a designs function at the schematic level

– Most prefer not to interact with a model at the text language level

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Schematic Model Generator (SMG)

User creates a schematic

like representation of their

behavioural model using the

provided building blocks

SMG Processes the

schematic to create

the behavioural model

Easy to use

Building blocks are placed, wired, configured and calibrated using a standard schematic in VSE

Integrated into Cadence Virtuoso design flow

Improve consistency and model quality

Create models from existing qualified building blocks

Model-schematic can be reused, shared, reconfigured and easily maintained

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Easy to use (schematic / GUI based) – Building blocks are placed, wired, configured, and calibrated using a

standard schematic (in Virtuoso Schematic Editor) – No language to enter or understand – Fully integrated into the well know Virtuoso design flow

Reusable model-schematic – Model-schematic can be reused, shared, reconfigured, and easily

maintained – Easily understandable graphical representation of the design functionality

Model generation creates a standard text model – Provides significantly more flexibility than standard netlisting approaches – Connections between blocks can be anything (variables, constants,

parameters), not just signals

Improved and consistent model quality – Created from existing mature and qualified model building blocks – Reduces the problems resulting from the lack of a designers skill set that

adversely affects the quality and performance of the final model – Model calibration with measured results by associating ADE XL measured

result data with building block parameters

Key Benefits of SMG

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Model Validation Problems

• Analog/MS behavioral models are created and initially validated against the original transistor level design

• The design/model continues to evolve and change

• Designers do not have time to continually validate models – Issues such as pin list mismatches or result variations occur

• Using the original (out of sync) model could result in incorrect verification results which hide design flaws

• Thus, continual model validation is mandatory during the design creation and modeling process

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What is amsDmv? AMS Design and Model Validation

• Integrated model validation solution that supports: – Validation of analog and digital waveform signals saved from

simulations

– Validation of measured values: Gain, power, delay, noise, etc.

– Validation of pin/module interfaces of the design and model

• Support GUI based setup and exported command line regression run

• Provides straightforward pass/fail output, reports and extended debugging capabilities (waveform zoom, etc.)

23 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Model Validation Flow (amsDmv)

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Model Validation Flow

25 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Agenda

1. Mixed-signal Overview

2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL)

3. Model Generation and Validation

4. Demo: Schematic Model Generator(SMG)

5. Demo: AMS Design & Model Validation (amsDmv)

6. Conclusions

26 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Demo: Schematic Model Generation (SMG)

27 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Agenda

1. Mixed-signal Overview

2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL)

3 Model Generation and Validation

4. Demo: Schematic Model Generator(SMG)

5. Demo: AMS Design & Model Validation (amsDmv)

6. Conclusions

28 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Demo: AMS Design & Model Validation

29 © 2013 Cadence Design Systems, Inc. Cadence confidential.

Agenda

1. Mixed-signal Overview

2. Real Numbers (SystemVerilog, Verilog-AMS, VHDL)

3. Model Generation and Validation

4. Demo: Schematic Model Generator (SMG)

5. Demo: AMS Design & Model Validation (amsDmv)

6. Conclusions

30 © 2013 Cadence Design Systems, Inc. Cadence confidential.

• More functional verification is needed with increasing A/D interactions in designs

• Incisive enables plug-and-play mixed signal simulation using AMS Designer

• Real number modeling provides high design accuracy while increasing MS simulation speed dramatically

• Schematic Model Generator (SMG) enables analog engineers to graphically create behavioral models

• SystemVerilog users can write real number models today nettypes with built-in resolution functions or the Cadence RNM library

• Auto-inserted connect modules are powerful ways to help with AD ports automatically

• Automatic wire coercions enables plug-n-play model integration without recoding port connection types

Summary

31 © 2013 Cadence Design Systems, Inc. Cadence confidential.

• Real Number Modeling (workshop and examples) – <Incisive 12.2 path>/doc/kit_topics/dms/workshop/lab_manual

– <Incisive 12.2 path>/tools/amsd/wrealSamples/wrealModels

• SMG (examples, model schematics and models) – <IC 6.1.5 path>/tools/dfII/samples/smg/smgAmsExample.tar.Z

• AMS Designer using AIUM (26 examples) – < Incisive 12.2 path>/tools/amsd/samples/aium

• UVM for Mixed Signal (overview, appnote, labs) – <Incisive 12.2 path>/doc/kit_topics/uvm_ms/

Demos/Workshops/Examples

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