7th Sem VLSI Lab Manual using Mentor Graphics

2011-12

7TH SEM VLSI LAB MANUAL Department of Electronics and Communication Engg.

TABLE OF CONTENT

1. 7TH Sem VTU E&C VLSI LAB Syllabus 06ECL77

2. Part-A Digital Design

- Digital Design Execution Steps

3. Test Constraints for Leonardo Spectrum

4. Part-A RV-VLSI Ref. Verilog Code

- Main Module, Testbench, GateLevelTestbench

5. Part-B Analog Design

- Analog Design Execution Steps

6. Schematic, Schematic Testbench, Excepted Waveforms

7. Parameters

- nspice, spi, cir

8. User Guide

- Using Mentor Graphics Design Kit

http://www.scribd.com/doc/63648062/7th-Sem-VLSI-Lab-Manual-using-Mentor-Graphics http://www.scribd.com/doc/63645000/User-Guide-Using-mentor-graphics-design-kit

http://www.scribd.com/doc/63648062/7th-Sem-VLSI-Lab-Manual-using-Mentor-Graphics

http://www.scribd.com/doc/63645000/User-Guide-Using-mentor-graphics-design-kit

7th Sem, VLSI Lab Manual VTU-06ECL77 2011-12

Dept. of E&C, CEC 1 SKLN, RCVK

Subject Code : 06ECL77 IA Marks : 25 No. of Practical Hrs/Week : 03 Exam Hours : 03 Total no. of Practical Hrs. : 42 Exam Marks : 50

PART - A

DIGITAL DESIGN ASIC-DIGITAL DESIGN FLOW 1. Write Verilog Code for the following circuits and their Test Bench for verification, observe the waveform and synthesise the code with technological library with given Constraints*. Do the initial timing verification with gate level simulation. i. An inverter ii. A Buffer iii. Transmission Gate iv. Basic/universal gates v. Flip flop -RS, D, JK, MS, T vi. Serial & Parallel adder vii. 4-bit counter [Synchronous and Asynchronous counter] viii. Successive approximation register [SAR] * An appropriate constraint should be given

PART - B ANALOG DESIGN

Analog Design Flow 1. Design an Inverter with given specifications*, completing the design flow mentioned below:

a. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis

b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design e. Verify & Optimize for Time, Power and Area to the given constraint***

2. Design the following circuits with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following

i) DC Analysis ii) AC Analysis iii) Transient Analysis

b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design.

i) A Single Stage differential amplifier ii) Common source and Common Drain amplifier

3. Design an op-amp with given specification* using given differential amplifier Common source and Common Drain amplifier in library** and completing the design flow mentioned below:

a. Draw the schematic and verify the following i) DC Analysis ii). AC Analysis iii) Transient Analysis

b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design.

7th Sem, VLSI Lab Manual VTU-06ECL77 2011-12


4. Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned using given op-amp in the library**.

a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis

iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design.

5. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW. [Specifications to GDS-II]

* Appropriate specification should be given. ** Applicable Library should be added & information should be given to the Designer. *** An appropriate constraint should be given http://www.scribd.com/doc/63648062/7th-Sem-VLSI-Lab-Manual-using-Mentor-Graphics

7th Sem, VLSI Lab Manual PART – A: DIGITAL DESIGN STEPS IN LINUX TERMINAL 2011-12


Esc

Insert

or

I

Insert Mode

--Insert--

Menu Mode

:wproj1.v

Vi editor

Linux Terminal Steps: Username: student01 Password: student01

1. Open Terminal from Desktop i.e. Right Click in the center of plane Desktop and use “Open Terminal” 2. Start the License Server 3. Check the License Manager Status 4. Create Directory with Student USN as Directory Name 5. Inside Student USN Directory Create Workspace directory 6. Copy Library files (i.e. tsmc018_typ.syn and adk.v) from

/home/student01/libraries/ 7. Here are some Commands in Steps 1 8. Follow the below Steps 2 to execute front end programs Note: $ Linux prompt Just like C:\> MS DOS prompt Linux is Case sensitive Always use only Small Letters/Alphabets

␢ Space Character/Symbol/Space bar ↵ Carriage Return/Enter key Symbol/Enter key

Steps 1: $ source␢.cshrc↵ $ Lmstat↵ $ mkdir␢1ce01ec001↵ $ cd␢1ce01ec001↵ /1ce01ec001$ vlib␢work↵ /1ce01ec001$ cp␢/home/student01/libraries/*␢.↵ /1ce01ec001$ vi␢inverter.v↵ /1ce01ec001$ vlog␢inverter.v␢inverter_test.v↵ /1ce01ec001$ vlog␢inverter_net.v␢inverter_gatetest.v␢adk.v↵

Rest of the commands please follow STEPS 2

/1ce01ec001$ vsim␢–c␢inverter_test␢–novopt↵ /1ce01ec001$ vsim␢inverter_test␢–novopt↵ /1ce01ec001$ spectrum↵ /1ce01ec001$ ls↵ /1ce01ec001$ cd␢..↵ $ pwd↵ $ cd␢\↵ $ pwd␢--help↵ $ vi␢--help↵ $ exit↵ Vi editors basic commands

:q Quit VI. If there have been changes made, the editor will issue a warning message. :q! Quit VI without saving changes. :vi␢proj1.vStarts editing a new file. If changes have not been saved, the editor will give you awarning. :w Write out the current file. :w␢proj2.v Write the buffer to the filename specified. :wq Write the buffer and quit. :wq! Write the buffer and force quit.

7th Sem, VLSI Lab Manual PART – A: DIGITAL DESIGN STEPS IN LINUX TERMINAL 2011-12


Steps 2: 1. Create Mainmodule Verilog

$ vi␢sync_counter.v↵ 2. Check Syntax error of Only Mainmodule Verilog

$ vlog␢sync_counter.v↵ 3. Create Testbench to test Mainmodule Verilog

$ vi␢sync_counter_testbench.v↵ 4. Check Syntax error of Only Testbench

$ vlog␢sync_counter_testbench.v↵ 5. Check compatibility of both Top/Mainmodule and Testbench together to obtain Top-module name

$ vlog␢sync_counter.v␢sync_counter_testbench.v↵ 6. Simulate Testbench in Text mode using

Top-module name in Vsim $ vsim␢–c␢sync_counter_testbench␢–novopt↵ VSIM1> run␢-all↵

: VSIM2> exit↵

7. Simulate Testbench in GUI/Graphical mode in Modelsim $ vsim␢sync_counter_testbench␢–novopt↵

8. Generate SDF and Netlist file from Spectrum using constraints provided $ spectrum↵

<leonardo 1> load_library␢tsmc018_typ.syn↵ <leonardo 2> read␢-format␢verilog␢sync_counter.v↵ <leonardo 3> set␢input2register␢ 2.00↵ <leonardo 4> set␢input2output ␢ 3.00↵ <leonardo 5> set␢register2output ␢ 3.00↵ <leonardo 6> set␢register2register␢ 3.20↵ <leonardo 7> clock_cycle␢3.2␢clock↵ <leonardo 8> set_attribute␢-name␢ARRIVAL_TIME␢-value␢"0.4"␢-port␢reset↵ <leonardo 9> set_attribute␢-name␢ARRIVAL_TIME␢-value␢"0.4"␢-port␢down↵ <leonardo 10> set_attribute␢-name␢ARRIVAL_TIME␢-value␢"0.4"␢-port␢up↵ <leonardo 11> optimize↵ <leonardo 12> write␢-format␢verilog␢sync_counter_netlist.v↵ <leonardo 13> write␢-format␢sdf␢sync_counter.sdf↵ <leonardo 14> report_delay␢ >␢delay.rpt↵ <leonardo 15> report_area␢>␢area.rpt↵ <leonardo 16> exit↵

9. Create Gatelevel Testbench to test Mainmodule Verilog using 180 nm Technology $ vi␢sync_counter_gatetestbench.v↵

10. Check Syntax error of Only Gatelevel Testbench $ vlog␢sync_counter_gatetestbench.v↵

11. Check compatibility of Netlistfile, Gatelevel Testbench and adk.v library together to obtain Top-module name w.r.t. 180 nm Technology $ vlog␢sync_counter_netlist.v␢sync_counter_gatetestbench.v␢adk.v↵

12. Simulate Gatelevel Testbench in Text mode using Top-module name in Vsim $ vsim␢–c␢sync_counter_gatetestbench␢–novopt↵ VSIM1> run␢-all↵

: VSIM2> exit↵

13. Simulate Gatelevel Testbench in GUI/Graphical mode in Modelsim using Top-module name $ vsim␢sync_counter_gatetestbench␢–novopt↵

14. To Exit the Linux Terminal $ exit↵

7th Sem, VLSI Lab Manual LEONARDO SPECTRUM CONSTRAINTS 2011-12


sync_counter.tcl load_library tsmc018_typ.syn read -format verilog sync_counter.v set input2register 2.00 set input2output 3.00 set register2output 3.00 set register2register 3.20 clock_cycle 3.2 clock set_attribute -name ARRIVAL_TIME -value "0.4" -port reset set_attribute -name ARRIVAL_TIME -value "0.4" -port down set_attribute -name ARRIVAL_TIME -value "0.4" -port up optimize write -format verilog sync_counter_netlist.v write -format sdf sync_counter.sdf report_delay > delay.rpt report_area > area.rpt Async_counter.tcl load_library tsmc018_typ.syn read -format verilog Async_counter.v elaborate set input2register 2.00 set input2output 3.00 set register2output 3.00 set register2register 3.20 clock_cycle 3.2 Clock set_attribute -name ARRIVAL_TIME -value "0.4" -port Reset optimize write -format verilog Async_counter_netlist.v write -format sdf Async_counter.sdf report_delay > delay.rpt report_area > area.rpt dflipflop.tcl load_library tsmc018_typ.syn read -format verilog dflipflop.v optimize write -format verilog dflipflop_netlist.v write -format sdf dflipflop.sdf master_slave.tcl load_library tsmc018_typ.syn read -format verilog dflipflop.v read -format verilog masterslave_flipflop.v clock_cycle 1 clock_i set input2register 0.5 set register2register 1 set register2output 0.5 optimize write -format verilog master_slave_netlist.v write -format sdf masterslave.sdf rsflipflop.tcl load_library tsmc018_typ.syn read -format verilog dflipflop.v read -format verilog rsflipflop.v synthesize optimize write -format verilog rsflipflop_netlist.v write -format sdf rsflipflop.sdf

tflipflop.tcl load_library tsmc018_typ.syn read -format verilog tflipflop.v clock_cycle 1 clock_i set input2register 0.5 set register2register 1 set register2output 0.5 optimize write -format verilog tflipflop_netlist.v write -format sdf tflipflop.sdf buffer.tcl load_library tsmc018_typ.syn read -format verilog buffer.v set input2output 0.6 optimize write -format verilog buffer_netlist.v write -format sdf buffer.sdf serial_adder.tcl load_library tsmc018_typ.syn read -format verilog full_adder.v read -format verilog serial_adder_4bit.v set input2output 1 optimize write -format verilog serialadder_netlist.v write -format sdf serialadder.sdf sar.tcl load_library tsmc018_typ.syn read -format verilog sar.v set input2register 2.00 set input2output 3.00 set register2output 3.00 set register2register 3.20 clock_cycle 3.2 clock_i optimize write -format verilog sar_netlist.v write -format sdf sar.sdf report_delay > delay.rpt report_area > area.rpt parllel_adder.tcl load_library tsmc018_typ.syn read -format verilog parllel_adder.v set input2output 1 optimize write -format verilog parlleladder_netlist.v write -format sdf parlleladder.sdf tgate.tcl load_library tsmc018_typ.syn read -format verilog tgate.v optimize write -format verilog tgate_netlist.v write -format sdf tgate.sdf

7th Sem, VLSI Lab Manual LEONARDO SPECTRUM CONSTRAINTS 2011-12


inverter_syn.tcl load_library tsmc018_typ.syn read -format verilog inverter.v set input2output 0.5 optimize write -format verilog inverter_netlist.v write -format sdf inverter.sdf basic_gate.tcl load_library tsmc018_typ.syn read -format verilog and.v present_design set input2output 1 optimize write -format verilog basic_gates_and.v write -format sdf basic_gates_and.sdf report_delay > and_delay.rpt read -format verilog or.v present_design set input2output 1 optimize write -format verilog basic_gates_or.v write -format sdf basic_gates_or.sdf report_delay > or_delay.rpt read -format verilog nand.v present_design set input2output 1 optimize write -format verilog basic_gates_nand.v write -format sdf basic_gates_nand.sdf report_delay > nand_delay.rpt read -format verilog nor.v present_design set input2output 1 optimize write -format verilog basic_gates_nor.v write -format sdf basic_gates_nor.sdf report_delay > nor_delay.rpt read -format verilog xor.v present_design set input2output 1 optimize write -format verilog basic_gates_xor.v write -format sdf basic_gates_xor.sdf report_delay > xor_delay.rpt read -format verilog xnor.v present_design set input2output 1 optimize write -format verilog basic_gates_xnor.v write -format sdf basic_gates_xnor.sdf report_delay > xnor_delay.rpt

Steps: 1. Create Mainmodule Verilog

$ vi sync_counter.v 2. Check Syntax error of Only Mainmodule Verilog

$ vlog sync_counter.v 3. Create Testbench to test Mainmodule Verilog

$ vi sync_counter_testbench.v 4. Check Syntax error of Only Testbench

$ vlog sync_counter_testbench.v 5. Check compatibility of both Top/Mainmodule and

Testbench together to obtain Top-module name $ vlog sync_counter.v sync_counter_testbench.v

6. Simulate Testbench in Text mode using Top-module name in Vsim $ vsim –c sync_counter_testbench –novopt run -all

7. Simulate Testbench in GUI/Graphical mode in Modelsim $ vsim sync_counter_testbench –novopt

8. Generate SDF and Netlist file from Spectrum using constraints provided $ spectrum

<leonardo 1> load_library tsmc018_typ.syn <leonardo 2> read -format verilog sync_counter.v <leonardo 3> set input2register 2.00 <leonardo 4> set input2output 3.00 <leonardo 5> set register2output 3.00 <leonardo 6> set register2register 3.20 <leonardo 7> clock_cycle 3.2 clock <leonardo 8> set_attribute -name ARRIVAL_TIME -value "0.4" -port reset <leonardo 9> set_attribute -name ARRIVAL_TIME -value "0.4" -port down <leonardo 10> set_attribute -name ARRIVAL_TIME -value "0.4" -port up <leonardo 11> optimize <leonardo 12> write -format verilog sync_counter_netlist.v <leonardo 13> write -format sdf sync_counter.sdf <leonardo 14> report_delay > delay.rpt <leonardo 15> report_area > area.rpt <leonardo 16> exit

9. Create Gatelevel Testbench to test Mainmodule Verilog using 180 nm Technology $ vi sync_counter_gatetestbench.v

10. Check Syntax error of Only Gatelevel Testbench $ vlog sync_counter_gatetestbench.v

11. Check compatibility of Netlistfile, Gatelevel Testbench and adk.v library together to obtain Top-module name w.r.t. 180 nm Technology

$ vlog sync_counter_netlist.v sync_counter_gatetestbench.v adk.v 12. Simulate Gatelevel Testbench in Text mode using

Top-module name in Vsim $ vsim –c sync_counter_gatetestbench –novopt run -all

13. Simulate Gatelevel Testbench in GUI/Graphical mode in Modelsim using Top-module name $ vsim sync_counter_gatetestbench –novopt

Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011

VK Mentor Graphics 1

//INVERTER module inverter ( input_i, output_o ) ; input input_i ; output output_o ; reg output_o; always @(input_i) begin if (input_i) output_o = 1'b0; else output_o = 1'b1; end endmodule //INVERTER TESTBENCH module inverter_test ; reg input_i ; wire output_o; inverter inverter_dut(.input_i(input_i ), .output_o(output_o)); initial input_i = 1'b0; always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o); #2000 $finish ; end endmodule //INVERTER GATELEVEL TESTBENCH module inverter_test ; reg input_i ; wire output_o; inverter inverter_dut(.input_i(input_i ),.output_o(output_o)); initial input_i = 1'b0; always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o); #2000 $finish ; end initial begin $sdf_annotate("inverter.sdf",inverter_test.inverter_dut, , , "maximum"); end endmodule



//BUFFER module buffer (input_i,output_o); input input_i; output output_o; reg output_o; always @(input_i) begin if (input_i) output_o = 1'b1; else output_o = 1'b0; end endmodule //BUFFER TESTBENCH module buffer_test ; reg input_i ; wire output_o; buffer buffer_dut(.input_i(input_i ), .output_o(output_o)); initial input_i = 1'b0; always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o); #2000 $finish ; end endmodule //BUFFER GATE LEVEL TESTBENCH module buffer_test ; reg input_i ; wire output_o; buffer buffer_dut(.input_i(input_i ),.output_o(output_o)); initial input_i = 1'b0; always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o); #2000 $finish ; end initial $sdf_annotate("buffer.sdf",buffer_test.buffer_dut); endmodule



//TRANSMISSION GATE module tgate (input_i, cntrl_i,output_o); input input_i; input cntrl_i; output output_o; reg output_o; always @(input_i or cntrl_i) begin if (cntrl_i) output_o = input_i; else output_o = 1'b0; end endmodule //TRANSMISSION GATE TESTBENCH module tgate_test ; reg input_i ; reg cntrl_i ; wire output_o; tgate tgate_dut(.input_i(input_i ),.cntrl_i(cntrl_i ),.output_o(output_o)); initial begin input_i = 1'b0; cntrl_i =1'b1; #100 cntrl_i =1'b0 ; #200 cntrl_i =1'b1 ; end always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b cntrl_i =%b and output_o =%b " ,input_i,cntrl_i,output_o); #2000 $finish ; end endmodule //TRANSMISSION GATE GATELEVEL TESTBENCH module tgate_test ; reg input_i ; reg cntrl_i ; wire output_o; tgate tgate_dut(.input_i(input_i ),.cntrl_i(cntrl_i ),.output_o(output_o)); initial begin input_i = 1'b0; cntrl_i =1'b1; #100 cntrl_i =1'b0 ;



#200 cntrl_i =1'b1 ; end always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b cntrl_i =%b and output_o =%b " ,input_i,cntrl_i,output_o); #2000 $finish ; end initial $sdf_annotate("tgate.sdf",tgate_test.tgate_dut,, ,"Maximum"); endmodule //BASIC AND GATE module basic_gate_and(a_i, b_i, c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = a_i && b_i; endmodule //BASIC OR GATE module basic_gate_or(a_i,b_i,c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = a_i || b_i; endmodule //BASIC NAND GATE module basic_gate_nand(a_i,b_i,c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = ~(a_i && b_i); endmodule



//BASIC NOR GATE module basic_gate_nor(a_i,b_i ,c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = ~(a_i || b_i); endmodule //BASIC XOR GATE module universal_gate_xor(a_i,b_i,c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = a_i ^ b_i; endmodule //BASIC XNOR GATE module universal_gate_xnor(a_i, b_i, c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = ~(a_i ^ b_i); endmodule //BASIC UNIVERSAL GATES TESTBENCH module basic_gates_test ; reg a_i ; reg b_i ; wire [5:0]c_o; basic_gate_and and_dut(.a_i(a_i ), .b_i(b_i ), .c_o(c_o[0])); basic_gate_or or_dut(.a_i(a_i ), .b_i(b_i ),.c_o(c_o[1])); basic_gate_nand nand_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[2])); basic_gate_nor nor_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[3])); universal_gate_xor xor_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[4])); universal_gate_xnor xnor_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[5]));



initial begin $display ( $time ,"\t simulation of the and_gate begins " ); a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #40 $display ( $time ," \t simulation of the or_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #100 $display ( $time ," \t simulation of the nand_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #150 $display ( $time ," \t simulation of the nor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #200 $display ( $time ," \t simulation of the xor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end



initial begin #250 $display ( $time ," \t simulation of the xnor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #300 $finish ; end initial begin fork $monitor ( $time , "\t a=%b b =%b and output of and gate c= %b" ,a_i,b_i,c_o[0] ); #50 $monitor ( $time , "\t a=%b b =%b and output of or gate c= %b" ,a_i,b_i,c_o[1] ); #110 $monitor ( $time , "\t a=%b b =%b and output of nand gate c= %b" ,a_i,b_i,c_o[2] ); #160 $monitor ( $time , "\t a=%b b =%b and output of nor gate c= %b" ,a_i,b_i,c_o[3] ); #210 $monitor ( $time , "\t a=%b b =%b and output of xor gate c= %b" ,a_i,b_i,c_o[4] ); #260 $monitor ( $time , "\t a=%b b =%b and output of xnor gate c= %b" ,a_i,b_i,c_o[5] ); join end endmodule //BASIC UNIVERSAL GATES GATELEVEL TESTBENCH module basic_gates_test ; reg a_i ; reg b_i ; wire [5:0]c_o; basic_gate_and and_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[0])); basic_gate_or or_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[1])); basic_gate_nand nand_dut( .a_i(a_i), .b_i(b_i ), .c_o(c_o[2])); basic_gate_nor nor_dut( .a_i(a_i ), .b_i(b_i ), .c_o(c_o[3])); universal_gate_xor xor_dut( .a_i(a_i ), .b_i(b_i ), .c_o(c_o[4])); universal_gate_xnor xnor_dut( .a_i(a_i ), .b_i(b_i ), .c_o(c_o[5])); initial begin $display ( $time ,"\t simulation of the and_gate begins " ); a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end



initial begin #40 $display ( $time ," \t simulation of the or_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #100 $display ( $time ," \t simulation of the nand_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #150 $display ( $time ," \t simulation of the nor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #200 $display ( $time ," \t simulation of the xor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #250 $display ( $time ," \t simulation of the xnor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end



initial begin #300 $finish ; end initial begin fork $monitor ( $time , "\t a=%b b =%b and output of and gate c= %b" ,a_i,b_i,c_o[0] ); #50 $monitor ( $time , "\t a=%b b =%b and output of or gate c= %b" ,a_i,b_i,c_o[1] ); #110 $monitor ( $time , "\t a=%b b =%b and output of nand gate c= %b" ,a_i,b_i,c_o[2] ); #160 $monitor ( $time , "\t a=%b b =%b and output of nor gate c= %b" ,a_i,b_i,c_o[3] ); #210 $monitor ( $time , "\t a=%b b =%b and output of xor gate c= %b" ,a_i,b_i,c_o[4] ); #260 $monitor ( $time , "\t a=%b b =%b and output of xnor gate c= %b" ,a_i,b_i,c_o[5] ); join end initial begin $sdf_annotate("basic_gates_and.sdf",basic_gates_test.and_dut,, ,"Maximum"); $sdf_annotate("basic_gates_or.sdf",basic_gates_test.or_dut,, ,"Maximum"); $sdf_annotate("basic_gates_nand.sdf",basic_gates_test.nand_dut,, ,"Maximum"); $sdf_annotate("basic_gates_nor.sdf",basic_gates_test.nor_dut,, ,"Maximum"); $sdf_annotate("basic_gates_xor.sdf",basic_gates_test.xor_dut,, ,"Maximum"); $sdf_annotate("basic_gates_xnor.sdf",basic_gates_test.xnor_dut,, ,"Maximum"); end endmodule //RS FLIP FLOP module rsflipflop (S,R,clock_i,q_o,qbar_o); input clock_i; input S; input R; output q_o; output qbar_o; wire q_o; wire qbar_o; dflipflop dff(.reset_i(1'b0),.clock_i(clock_i),.data_in_i(w3),.q_o(q_o),.qbar_o(qbar_o)); not n1 (w1 ,R ); and a1 (w2,w1,q_o); or o1 (w3,S,w2); endmodule



//RS FLIP FLOP TESTBENCH module rsflipflop_test; reg clock_i; reg R; reg S; wire q_o; wire qbar_o; rsflipflop rsff(.R(R),.S(S),.clock_i(clock_i),.q_o(q_o),.qbar_o(qbar_o)); initial begin clock_i =1'b0 ; R =1'b0; end always #5 clock_i = !clock_i ; initial begin #20 R =1'b1 ; #20 S =1'b1 ; R =1'b0; #20 S =1'b0 ; R =1'b0; #30 S =1'b1 ; R =1'b1; #10 S =1'b0 ; R =1'b1; end initial begin $monitor($time ," \t clock_i =%b R= %b S =%b q=%b qbar =%b ",clock_i,R,S,q_o,qbar_o); #200 $finish; end endmodule //RS FLIP FLOP GATELEVEL TESTBENCH module rsflipflop_test; reg clock_i; reg R; reg S; wire q_o; wire qbar_o; rsflipflop rsff(.R(R),.S(S),.clock_i(clock_i),.q_o(q_o),.qbar_o(qbar_o)); initial begin clock_i =1'b0 ; R =1'b0; end



always #5 clock_i = !clock_i ; initial begin #20 R =1'b1 ; #20 S =1'b1 ; R =1'b0; #20 S =1'b0 ; R =1'b0; #80 S =1'b1 ; R =1'b1; end initial begin $monitor($time ," \t clock_i =%b R= %b S =%b q=%b qbar =%b ",clock_i,R,S,q_o,qbar_o); #200 $finish; end initial begin $sdf_annotate ("rsflipflop.sdf",rsflipflop_test.rsff); end endmodule //D FLIP FLOP module dflipflop (reset_i, clock_i, data_in_i, q_o, qbar_o); input clock_i; input reset_i; input data_in_i; output q_o; output qbar_o; reg q_o; wire qbar_o; always @(posedge clock_i) begin if(reset_i) q_o <=1'b0; else q_o <= data_in_i; end assign qbar_o = ~q_o; endmodule



//D FLIP FLOP TESTBENCH module dflipflop_test; reg clock_i; reg reset_i; reg data_in_i; wire q_o; wire qbar_o; dflipflop dff(.reset_i(reset_i),.clock_i(clock_i),.data_in_i(data_in_i),.q_o(q_o),.qbar_o(qbar_o)); initial begin clock_i =1'b0 ; reset_i =1'b0; end always #5 clock_i = !clock_i ; initial begin #20 reset_i =1'b1 ; #20 data_in_i = 1'b1; #20 data_in_i = 1'b0; reset_i =1'b0; #60 data_in_i = 1'b1; reset_i =1'b0; #100 reset_i =1'b1; end initial begin $monitor($time ," \t clock_i =%b reset_i= %b data_in_i =%b q=%b qbar_o =%b ",clock_i,reset_i,data_in_i,q_o ,qbar_o); #400 $finish; end endmodule



//D FLIP FLOP GATE LEVEL TESTBENCH module dflipflop_test; reg clock_i; reg reset_i; reg data_in_i; wire q_o; wire qbar_o; dflipflop dff(.reset_i(reset_i),.clock_i(clock_i),.data_in_i(data_in_i),.q_o(q_o),.qbar_o(qbar_o)); initial begin clock_i =1'b0 ; reset_i =1'b0; end always #5 clock_i = !clock_i ; initial begin #20 reset_i =1'b1 ; #20 data_in_i = 1'b1; #20 data_in_i = 1'b0; reset_i =1'b0; #60 data_in_i = 1'b1; reset_i =1'b0; #100 reset_i =1'b1; end initial begin $monitor($time ," \t clock_i =%b reset_i= %b data_in_i =%b q=%b qbar_o =%b ",clock_i,reset_i,data_in_i,q_o ,qbar_o); #400 $finish; end initial $sdf_annotate("dflipflop.sdf",dflipflop_test.dff,, ,"Maximum"); endmodule



//JK FLIP FLOP module jkflipflop (J_i,K_i,clock_i,q_o,qbar_o); input clock_i; input J_i; input K_i; output q_o; output qbar_o; reg q_o; reg qbar_o; always @(posedge clock_i) begin if(J_i && ~K_i) begin q_o <=1'b1; qbar_o<=1'b0; end else begin if(~J_i && K_i ) begin q_o <=1'b0; qbar_o<=1'b1; end else begin if(~J_i && ~K_i ) begin q_o <=q_o; qbar_o<=qbar_o; end else begin q_o <=~q_o; qbar_o<=~qbar_o; end end end end endmodule



//JK FLIP FLOP TESTBENCH module jkflipflop_test; reg clock_i; reg K_i; reg J_i; reg data_in_i; wire q_o; wire qbar_o; jkflipflop jkff(.K_i(K_i),.J_i(J_i),.clock_i(clock_i),.q_o(q_o),.qbar_o(qbar_o)); initial begin clock_i =1'b0 ; K_i =1'b0; end always #5 clock_i = !clock_i ; initial begin #20 K_i =1'b1 ; #20 J_i =1'b1 ; K_i =1'b0; #20 J_i =1'b0 ; K_i =1'b0; #20 J_i =1'b1 ; K_i =1'b1; end initial begin $monitor($time ," \t clock_i =%b K_i= %b J_i =%b q=%b qbar =%b ",clock_i,K_i,J_i,q_o,qbar_o); #200 $finish; end endmodule //JK FLIP FLOP GATELEVEL TESTBENCH module jkflipflop_test; reg clock_i; reg K_i; reg J_i; reg data_in_i; wire q_o; wire qbar_o; jkflipflop jkff(.K_i(K_i),.J_i(J_i),.clock_i(clock_i),.q_o(q_o),.qbar_o(qbar_o));



initial begin clock_i =1'b0 ; K_i =1'b0; end always #5 clock_i = !clock_i ; initial begin #20 K_i =1'b1 ; #20 J_i =1'b1 ; K_i =1'b0; #20 J_i =1'b0 ; K_i =1'b0; #20 J_i =1'b1 ; K_i =1'b1; end initial begin $monitor($time ," \t clock_i =%b K_i= %b J_i =%b q=%b qbar =%b ",clock_i,K_i,J_i,q_o,qbar_o); #200 $finish; end initial $sdf_annotate("jkflipflop.sdf",jkflipflop_test.jkff,, ,"Maximum"); endmodule //MASTER SLAVE FLIP FLOP module msflipflop (reset_i,clock_i,d_i,q_o); input reset_i; input clock_i; input d_i; output q_o; wire w1; dflipflop Master(.reset_i(reset_i),.clock_i(~clock_i),.data_in_i(d_i),.q_o(w1)); dflipflop Slave(.reset_i(reset_i),.clock_i(clock_i),.data_in_i(w1),.q_o(q_o)); endmodule



//MASTER SLAVE FLIP FLOP TESTBENCH module ms_test; reg clock_i; reg reset_i; reg d_i; wire q_o; msflipflop ms(reset_i,clock_i,d_i,q_o); initial begin clock_i =1'b0 ; reset_i =1'b0; end always #5 clock_i = !clock_i ; initial begin #20 reset_i =1'b1 ; #20 d_i = 1'b1; #20 d_i = 1'b0; reset_i =1'b0; #60 d_i = 1'b1; reset_i =1'b0; #100 reset_i =1'b1; end initial begin $monitor($time ," \t clock_i =%b reset_i= %b d_i =%b q=%b ",clock_i,reset_i,d_i,q_o); #400 $finish; end endmodule //MASTER SLAVE FLIP FLOP GATELEVEL TESTBENCH module ms_test; reg clock_i; reg reset_i; reg d_i; wire q_o; msflipflop ms(reset_i,clock_i,d_i,q_o); initial begin clock_i =1'b0 ; reset_i =1'b0; end



always #5 clock_i = !clock_i ; initial begin #20 reset_i =1'b1 ; #20 d_i = 1'b1; #20 d_i = 1'b0; reset_i =1'b0; #60 d_i = 1'b1; reset_i =1'b0; #100 reset_i =1'b1; end initial begin $monitor($time ," \t clock_i =%b reset_i= %b d_i =%b q=%b ",clock_i,reset_i,d_i,q_o); #400 $finish; end initial $sdf_annotate("masterslave.sdf",ms_test.ms,, ,"Maximum"); endmodule //T FLIP FLOP module tflipflop (reset_i,clock_i,T_i,q_o); input clock_i; input reset_i; input T_i; output q_o; reg q_o; always @(posedge clock_i) begin if(reset_i) q_o <=1'b0; else begin if(T_i) q_o <= ~q_o; else q_o <= q_o; end end endmodule



//T FLIP FLOP TESTBENCH module tflipflop_test; reg clock_i; reg reset_i; reg T_i; wire q_o; tflipflop tff(.reset_i(reset_i),.clock_i(clock_i),.T_i(T_i),.q_o(q_o)); initial begin clock_i =1'b0 ; reset_i =1'b0; end always #5 clock_i = !clock_i ; initial begin #20 reset_i =1'b1 ; #20 T_i = 1'b1; #20 T_i = 1'b0; reset_i =1'b0; #60 T_i = 1'b1; reset_i =1'b0; #100 reset_i =1'b1; end initial begin $monitor($time ," \t clock_i =%b reset_i= %b T_i =%b q=%b ",clock_i,reset_i,T_i,q_o); #400 $finish; end endmodule



//T FLIP FLOP GATELEVEL TESTBENCH module tflipflop_test; reg clock_i; reg reset_i; reg T_i; wire q_o; tflipflop tff(.reset_i(reset_i),.clock_i(clock_i),.T_i(T_i),.q_o(q_o)); initial begin clock_i =1'b0 ; reset_i =1'b0; end always #5 clock_i = !clock_i ; initial begin #20 reset_i =1'b1 ; #20 T_i = 1'b1; #20 T_i = 1'b0; reset_i =1'b0; #60 T_i = 1'b1; reset_i =1'b0; #100 reset_i =1'b1; end initial begin $monitor($time ," \t clock_i =%b reset_i= %b T_i =%b q=%b ",clock_i,reset_i,T_i,q_o); #400 $finish; end initial $sdf_annotate("tflipflop.sdf",tflipflop_test.tff,, ,"Maximum"); endmodule



//FULL ADDER module full_adder(a,b,cin,sum,cout); input a; input b; input cin; output sum; output cout; assign sum = cin ^ a ^ b; assign cout = (a && b ) || (b && cin) || (cin && a) ; endmodule //4BIT SERIAL ADDER module adder_4_bit(x,y,cin,z,cout); input [3:0] x ; input [3:0] y ; input cin; output [3:0] z; output cout; wire [3:1] carry; full_adder fa0(x[0],y[0],cin,z[0],carry[1]); full_adder fa1(x[1],y[1],carry[1],z[1],carry[2]); full_adder fa2(x[2],y[2],carry[2],z[2],carry[3]); full_adder fa3(x[3],y[3],carry[3],z[3],cout); endmodule //4BIT SERIAL ADDER TESTBENCH module adder_4_bit_tb; reg [3:0] x ; reg [3:0] y ; reg cin; wire [3:0] z; wire cout; wire [4:0] expected_result; wire [4:0] actual_result; adder_4_bit a0(x,y,cin,z,cout); initial begin x = 0; y = 0; cin = 0; #10 x = 4'b0101; y = 4'b0001; cin = 1'b0; #10 x = 4'b0101; y = 4'b1110; cin = 1'b1; #10 x = 4'b1111; y = 4'b1111; cin = 1'b1; #10 x = 0; y = 0; cin = 0; #10 $finish; end



assign expected_result = x+y+cin; assign actual_result = {cout,z}; initial begin if(actual_result!==expected_result) $monitor ($time , " x= %d ,y =%d cin =%b ,expected_result=%d actual_result =%d, the expected sum is not correct" , x ,y ,cin ,expected_result,actual_result); else $monitor ($time , " x= %d ,y =%d cin =%b expected_result=%d actual_result =%d , the expected sum is correct" , x ,y ,cin,expected_result,actual_result ); end endmodule //SERIAL ADDER GATE LEVEL TESTBENCH module adder_4_bit_tb; reg [3:0] x ; reg [3:0] y ; reg cin; wire [3:0] z; wire cout; wire [4:0] expected_result; wire [4:0] actual_result; adder_4_bit a0(x,y,cin,z,cout); initial begin x = 0; y = 0; cin = 0; #10 x = 4'b0101; y = 4'b0001; cin = 1'b0; #10 x = 4'b0101; y = 4'b1110; cin = 1'b1; #10 x = 4'b1111; y = 4'b1111; cin = 1'b1; #10 x = 0; y = 0; cin = 0; #10 $finish; end assign expected_result = x+y+cin; assign actual_result = {cout,z}; initial begin if(actual_result!==expected_result) $monitor ($time , " x= %d ,y =%d cin =%b ,expected_result=%d actual_result =%d , the expected sum is not correct" , x ,y ,cin ,expected_result,actual_result); else $monitor ($time , " x= %d ,y =%d cin =%b expected_result=%d actual_result =%d , the expected sum is correct" , x ,y ,cin,expected_result,actual_result ); end initial $sdf_annotate("serialadder.sdf",adder_4_bit_tb.a0,, ,"Maximum"); endmodule



//PARALLEL ADDER GATELEVEL TESTBENCH module adder_4_bit_tb; reg [3:0] x ; reg [3:0] y ; reg cin; wire [3:0] z; wire cout; wire [4:0] expected_result; wire [4:0] actual_result; cla_adder a0(.a_in(x),.b_in(y),.c_in(cin),.sum_o(z),.c_out(cout)); initial begin x = 0; y = 0; cin = 0; #10 x = 4'b0101; y = 4'b0001; cin = 1'b0; #10 x = 4'b0101; y = 4'b1110; cin = 1'b1; #10 x = 4'b1111; y = 4'b1111; cin = 1'b1; #10 x = 0; y = 0; cin = 0; #10 $finish; end assign expected_result = x+y+cin; assign actual_result = {cout,z}; initial begin if(actual_result!==expected_result) $monitor ($time , " x= %d ,y =%d cin =%b ,expected_result=%d actual_result =%d ,the expected sum is not correct" , x ,y ,cin ,expected_result,actual_result); else $monitor ($time , " x= %d ,y =%d cin =%b expected_result=%d actual_result =%d , the expected sum is correct" , x ,y ,cin,expected_result,actual_result ); end initial $sdf_annotate("parlleladder.sdf",adder_4_bit_tb.a0,, ,"Maximum"); endmodule //PARALLEL ADDER module cla_adder(a_in, b_in, c_in, sum_o, c_out); parameter SIZE = 4; input [SIZE -1 : 0] a_in; input [SIZE -1 : 0] b_in; input c_in; output [SIZE -1:0] sum_o; output c_out;



wire g0,p0,g1,p1,g2,p2,g3,p3,g4,p4,x0,x1,x2,x3,x4,x5,x6,x7,x8,x9; wire c1,c2,c3; and a1(g0,a_in[0],b_in[0]); xor xr1(p0,a_in[0],b_in[0]); and a2(g1,a_in[1],b_in[1]); xor xr2(p1,a_in[1],b_in[1]); and a3(g2,a_in[2],b_in[2]); xor xr3(p2,a_in[2],b_in[2]); and a4(g3,a_in[3],b_in[3]); xor xr4(p3,a_in[3],b_in[3]); //~~ For C1 ~~ and a6(x0,p0,c_in); or o1(c1,g0,x0); //~~ For C2 ~~ and a7(x1,c_in,p1,p0); and a8(x2,p1,g0); or o2(c2,g1,x2,x1); //~~ For C3 ~~ and a9(x3,c_in,p2,p1,p0); and a10(x4,p2,p1,g0); and a11(x5,p2,g1); or o3(c3,g2,x5,x4,x3); //~~ For C4 ~~ and a12(x6,c_in,p3,p2,p1,p0); and a13(x7,p3,p2,p1,g0); and a14(x8,p3,p2,g1); and a15(x9,p3,g2); or (c_out,g3,x9,x8,x7,x6); //~~ output logic for CLA adder ~~ xor xr6(sum_o[0],c_in,p0); xor xr7(sum_o[1],c1,p1); xor xr8(sum_o[2],c2,p2); xor xr9(sum_o[3],c3,p3); endmodule //PARALLEL ADDER TESTBENCH module adder_4_bit_tb; reg [3:0] x ; reg [3:0] y ; reg cin; wire [3:0] z; wire cout; wire [4:0] expected_result; wire [4:0] actual_result; cla_adder a0(.a_in(x),.b_in(y),.c_in(cin),.sum_o(z),.c_out(cout));



initial begin x = 0; y = 0; cin = 0; #10 x = 4'b0101; y = 4'b0001; cin = 1'b0; #10 x = 4'b0101; y = 4'b1110; cin = 1'b1; #10 x = 4'b1111; y = 4'b1111; cin = 1'b1; #10 x = 0; y = 0; cin = 0; #10 $finish; end assign expected_result = x+y+cin; assign actual_result = {cout,z}; initial begin if(actual_result!==expected_result) $monitor ($time , " x= %d ,y =%d cin =%b ,expected_result=%d actual_result =%d ,the expected sum is not correct" , x ,y ,cin ,expected_result,actual_result); else $monitor ($time , " x= %d ,y =%d cin =%b expected_result=%d actual_result =%d , the expected sum is correct" , x ,y ,cin,expected_result,actual_result ); end endmodule //4 BIT SYNCHRONOUS UP DOWN COUNTER module sync_counter (clock,reset,up,down,count); input clock; input reset; input up; input down; output [3:0] count; reg [3:0] count; always@(posedge clock) begin if (reset) count <= 4'b0; else if (up && ~down) count <= count + 1'b1; else if (down && ~up) count <= count - 1'b1; else count <= count; end endmodule



//4 BIT SYNCHRONOUS UP DOWN COUNTER TESTBENCH module tb_sync_counter; reg clk ; reg rst ; reg Up ; reg Down; wire [3:0] Count; sync_counter S1 (.clock(clk),.reset(rst),.up(Up),.down (Down ),.count(Count)); initial begin clk = 1'b0; forever begin #5; clk = ~clk; end end task Reset; begin rst = 1'b1; $display($time, "Reset is Asserted"); #10; rst = 1'b0;Up=1'b1; $display($time, "Reset is DE-Asserted"); end endtask initial begin Reset; repeat(5) begin #10 Up = 1'b1; Down = 1'b0; end repeat(10) begin #10 Up = 1'b0; Down = 1'b1; end $finish; end always@(posedge clk) $display ($time ," || CLOCK = %b || RESET = %b || UP = %b || DOWN = %b || COUNT = %b",clk,rst,Up,Down,Count); endmodule



//4 BIT SYNCHRONOUS UP DOWN COUNTER GATELEVEL TESTBENCH module tb_sync_counter; reg clk ; reg rst ; reg Up ; reg Down; wire [3:0] Count; sync_counter S1 (.clock(clk),.reset(rst),.up(Up),.down (Down ),.count(Count)); initial begin clk = 1'b0; forever begin #5; clk = ~clk; end end task Reset; begin rst = 1'b1; $display($time, "Reset is Asserted"); #10; rst = 1'b0;Up=1'b1; $display($time, "Reset is DE-Asserted"); end endtask initial begin Reset; repeat(5) begin #10 Up = 1'b1; Down = 1'b0; end repeat(10) begin #10 Up = 1'b0; Down = 1'b1; end $finish; end always@(posedge clk) $display ($time ," || CLOCK = %b || RESET = %b || UP = %b || DOWN = %b || COUNT = %b", clk,rst,Up,Down,Count); initial $sdf_annotate("sync_counter.sdf",tb_sync_counter.S1,, ,"Maximum"); endmodule



//4 BIT ASYNCHRONOUS UP DOWN COUNTER module Async_counter (Clock,Reset,count); input Clock; input Reset; output [3:0] count; tff T1 (.clock(Clock),.reset(Reset),.T(1'b1),.q(count[0])); tff T2 (.clock(!count[0]),.reset(Reset),.T(1'b1),.q(count[1])); tff T3 (.clock(!count[1]),.reset(Reset),.T(1'b1),.q(count[2])); tff T4 (.clock(!count[2]),.reset(Reset),.T(1'b1),.q(count[3])); endmodule //T FLIP FLOP SYNCHRONOUS RESET module tff (clock,reset,T,q); input clock; input reset; input T; output q; reg q; always@(posedge clock or posedge reset) begin if (reset) q <= 1'b0; else if (T) q <= ~q; else q <= q; end endmodule //4 BIT ASYNCHRONOUS UP DOWN COUNTER TESTBENCH module tb_Async_counter; reg clk ; reg rst ; wire [3:0] Count; Async_counter async_counter (.Clock(clk ),.Reset(rst ),.count(Count)); initial begin clk = 1'b0; forever begin #5;clk = ~clk; end end



task Reset; begin rst = 1'b1; $display($time, "Reset is Asserted"); #10; rst = 1'b0; $display($time, "Reset is DE-Asserted"); end endtask initial begin Reset; #50; Reset; #150 $finish; end always@(posedge clk) $display ($time ," || CLOCK = %b || RESET = %b || COUNT = %b",clk,rst,Count); endmodule //4 BIT SYNCHRONOUS UP DOWN COUNTER GATELEVEL TESTBENCH module tb_Async_counter; reg clk ; reg rst ; wire [3:0] Count; Async_counter async_counter (.Clock(clk ),.Reset(rst ),.count(Count)); initial begin clk = 1'b0; forever begin #5;clk = ~clk; end end task Reset; begin rst = 1'b1; $display($time, "Reset is Asserted"); #10; rst = 1'b0; $display($time, "Reset is DE-Asserted"); end endtask



initial begin Reset; #50; Reset; #150 $finish; end always@(posedge clk) $display ($time ," || CLOCK = %b || RESET = %b || COUNT = %b",clk,rst,Count); initial $sdf_annotate("Async_counter.sdf",tb_Async_counter.async_counter,, ,"Maximum"); endmodule //SUCCESSIVE APPROXIMATION REGISTER module sar(clock_i,reset_i,analog_gt_digital,digital_out); input clock_i; input reset_i; input analog_gt_digital; output [3:0] digital_out; reg [3:0] digital_out; always @(posedge clock_i) begin if(reset_i) digital_out <= 4'b0; else begin if (analog_gt_digital) digital_out <= digital_out+1; else digital_out <= digital_out-1; end end endmodule //SUCCESSIVE APPROXIMATION REGISTER TESTBENCH module sar_test; reg clock_i; reg reset_i; reg analog_gt_digital; wire [3:0] digital_out; sar sar(.reset_i(reset_i),.clock_i(clock_i),.analog_gt_digital(analog_gt_digital),.digital_out(digital_out));



initial begin clock_i =1'b0 ; reset_i =1'b1; end always #5 clock_i = !clock_i ; initial begin #40 reset_i =1'b0 ;analog_gt_digital=1'b1; #40 reset_i =1'b0 ;analog_gt_digital=1'b0; #40 reset_i =1'b0 ;analog_gt_digital=1'b1; #80 reset_i =1'b0 ;analog_gt_digital=1'b0; end initial begin $monitor($time ," \t clock_i =%b reset_i= %b analog_gt_digital=%b digital_out=%b ",clock_i,reset_i,analog_gt_digital,digital_out); #200 $finish; end endmodule //SUCCESSIVE APPROXIMATION REGISTER GATELEVEL TESTBENCH module sar_test; reg clock_i; reg reset_i; reg analog_gt_digital; wire [3:0] digital_out; sar sar(.reset_i(reset_i),.clock_i(clock_i),.analog_gt_digital(analog_gt_digital),.digital_out(digital_out)); initial begin clock_i =1'b0 ; reset_i =1'b1; end always #5 clock_i = !clock_i ; initial begin #40 reset_i =1'b0 ;analog_gt_digital=1'b1; #40 reset_i =1'b0 ;analog_gt_digital=1'b0; #40 reset_i =1'b0 ;analog_gt_digital=1'b1; #80 reset_i =1'b0 ;analog_gt_digital=1'b0; end



initial begin $monitor($time ," \t clock_i =%b reset_i= %b analog_gt_digital=%b digital_out=%b ", clock_i,reset_i,analog_gt_digital,digital_out); #200 $finish; end initial $sdf_annotate("sar.sdf",sar_test.sar,, ,"Maximum"); endmodule

7th Sem, VLSI Lab Manual PART-B, ANALOG DESIGN STEPS TO DESIGN SCHEMATIC IN ICSTUDIO 2011-12


␢ Space Character/Symbol/Space bar

↵ Carriage Return/Enter key Symbol/Enter key PROCEDURE 1.Create a directory and go within it by cd<directory name>

2. $ icstudio␢&↵ 3. File New Project

Window will appear, give project name:1ce08ec001 Next

Click on open library list editor edit Add MCG Design Kit.

4. A window will appear go to ⃰\... /tools.x86 Mentor

cicd_pt-05100 cicd data my kit ok

5. Next open setting editor

• Process file browse my_ kit process mgc_generic • DRC browse go back rule_deck DRC • LVS go back rule_deck LVS • PEX back rule_deck PEX

Angle Mode 90 degree • SDL Go back process Sdl_process_rules • Click ok. • Click Finish.

Note: DRC Design rule check

LVS Layout v/s schematic

PEX Parasitic extraction

6. File New Library Give the library name:VLSILAB

7. Right click on CELL window New cell view ( cell_name) View type

Schematic Click FINISH.

Keys

i add instace

r rotate

m move

c copy

wwire

z zoom in

shift z zoom out

f fit to screen

p pins

w connecting wires

7th Sem, VLSI Lab Manual PART-B, ANALOG DESIGN STEPS TO DESIGN SCHEMATIC IN ICSTUDIO 2011-12


8. press i browse MGC_DESIGN_KIT pmos (Cell)

W 0.6 u apply Ok.

Press i browse MGC_DESIGN_KIT nmos (Cell)

w 0.3 u apply Ok.

9. + Port in click on +

For changing name of the port Click on port and press q Check & Save

10. Click tools generate symbol choose shape buffer line

bubble check & save Close.

Test bench program procedure

Right click on cell new cell ( cell_tb name) finish

Press i Browse inverter (library) inv (cell) view (invl) Apply Press i Browse MGC_IC_Sources_LIB pulse_v_source delay = 0, period =5ns Apply T_fall = 1ps, trise =1ps apply width =2.5ns apply.

Press i browse MGC_IC_Sources_LIB pulse_v_source delay = 0, period =5ns Apply dc_v_source(dc=1.2v) ,(INSV1)

Browse MGC__IC_GENERIC_LAB Vdd apply OK Browse MGC__IC_GENERIC_LAB Ground apply OK

Right hand side Simulation New configuration AMS _Simulation OK Lib| Temp|Inc include files Delete all ok

Lib| Temp|Inc libraries library path browse lib.eldo lib variants (Give TT)

Analysis DC setup source voltage source (v2) stop voltage (1.2v) step (0.001) ok.

Analysis transient Setup (TSTART =0, TSTOP =100N, TPRINT =0.001) Ok.

Wave outputs Type Click on this then click add update

Netlist

Run ELDO

View waves

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# # # # # ###### ##### ##### ###### ##### # ## # # # # # # # # # # # # # # # # ##### # # # ##### # # # # # # # # # ##### # # ##### # # ## # # # # # # # # # # # # ## ###### # # # ###### # #

file:///C|/Vishvakirana/nspice_spi_cir/inverter.eldo.nspice.txt[29/10/2011 11:20:33 PM]

* ELDO netlist generated with ICnet by 'vsrinivas' on Wed Jul 21 2010 at 14:59:37

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/inverter* m2 y a vdd vdd pmos w=0.6u l=0.13u m=1 as=0.228p ad=0.228p ps=1.96u+ pd=1.96u m1 y a gnd gnd nmos w=0.3u l=0.13u m=1 as=0.114p ad=0.114p ps=1.36u+ pd=1.36u*.end

file:///C|/Vishvakirana/nspice_spi_cir/inverter_test_bench_DC_Tran_analysis.spi.txt[29/10/2011 11:20:33 PM]

** .CONNECT statements*.CONNECT GROUND 0

* ELDO netlist generated with ICnet by 'root' on Tue Sep 7 2010 at 15:46:31

** Globals.*.global VDD GROUND

** Component pathname : $VTU_Labs/default.group/logic.views/inverter [ELDOSPICE]* .include /mgc_tree/design_data/cicd_spt_051007/cicd/data/SelfPacedDemo.proj/VTU_Labs.lib/default.group/spice.views/inverter.back_annotation.spi

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/inverter_test_bench* X_INVERTER1 GROUND VDD Y A INVERTER V2 VDD GROUND DC 1.2V C1 Y GROUND 1f IC=0 V1 A GROUND PULSE ( 0V 1V 0S 1pS 1pS 5nS 10n )*.end

file:///C|/Vishvakirana/nspice_spi_cir/inverter_test_bench_DC_Tran_analysis.cir.txt[29/10/2011 11:20:33 PM]

* Component: $VTU_Labs/default.group/logic.views/inverter_test_bench Viewpoint: DC_Tran_analysis.INCLUDE $VTU_Labs/default.group/logic.views/inverter_test_bench/DC_Tran_analysis/inverter_test_bench_DC_Tran_analysis.spi.INCLUDE $MGC_DESIGN_KIT/models/include_all.OPTION NOASCII.OPTION MODWL.OPTION ENGNOT.OPTION AEX

* --- Singles.OPTION LIMPROBE = 10000

* - Analysis Setup - DCOP.OPTION PROBOP2.OPTION PROBOPX.OP

* - Analysis Setup - DC.DC V1 0 1.2 0.001

* - Analysis Setup - Trans.TRAN 0.001 50N 0

* --- Waveform Outputs.PROBE ALL SG

* --- Params.TEMP 27

* --- Scenarios.LIB $MGC_DESIGN_KIT/models/include_all.LIB KEY=LIB_0 $MGC_DESIGN_KIT/models/lib.eldo TT.LIB KEY=LIB_1 $MGC_DESIGN_KIT/models/res.spi CAPS.LIB KEY=LIB_2 $MGC_DESIGN_KIT/models/res.spi RES_T

#### #### # # # # #### # # ##### ##### ## # # # # # # # ## ## ## ## # # ## # # # # # # # # ## # # # # # ## # # ## # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # ##### ###### # # # # # # # # # # # # # # # ## # # # # # # # # ## #### #### # # # # #### # # ##### # # # # # # # ## # # ##### # # ###### # ###### ##### # # ## ## # # # # # # # # # # # # ## # # # # # ##### # ##### # # ###### # # ##### # # # # # ##### # # # # # # # # # # # # # # # # # ###### # # # ###### # #

file:///C|/Vishvakirana/nspice_spi_cir/cdampl.eldo.nspice.txt[29/10/2011 11:20:45 PM]

* ELDO netlist generated with ICnet by 'vsrinivas' on Fri May 7 2010 at 12:26:03


** Component pathname : $VTU_Labs/default.group/logic.views/common_drain_amplifier*.subckt COMMON_DRAIN_AMPLIFIER OUT IN

V3 VDD GROUND DC 2.5V R1 OUT GROUND 100K M1 VDD IN OUT VDD nmos w=40u l=0.39u m=20 as=7.64p ad=6.8p ps=44.382u+ pd=40.34u.ends COMMON_DRAIN_AMPLIFIER

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/cd_amplifier_test_bench* V2 N$2 GROUND DC 0V AC 1 0 SIN ( 0 5mv 100k 0 0 ) V1 VIN N$2 DC 2.5V X_COMMON_DRAIN_AMPLIFIER1 VOUT VIN COMMON_DRAIN_AMPLIFIER*.end

file:///C|/Vishvakirana/nspice_spi_cir/cd_amplifier_test_bench_AC_DC_Tran_analysis.spi.txt[29/10/2011 11:20:45 PM]




** Component pathname : $VTU_Labs/default.group/logic.views/common_drain_amplifier*.subckt COMMON_DRAIN_AMPLIFIER OUT IN

V3 VDD GROUND DC 2.5V R1 OUT GROUND 100K M1 VDD IN OUT VDD nmos w=40u l=0.39u m=20 as=7.64p ad=6.8p ps=44.382u+ pd=40.34u.ends COMMON_DRAIN_AMPLIFIER

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/cd_amplifier_test_bench* V2 N$2 GROUND DC 0V AC 1 0 SIN ( 0 5mv 100k 0 0 ) V1 VIN N$2 DC 2.5V X_COMMON_DRAIN_AMPLIFIER1 VOUT VIN COMMON_DRAIN_AMPLIFIER*.end

file:///C|/Vishvakirana/nspice_spi_cir/cd_amplifier_test_bench_AC_DC_Tran_analysis.cir.txt[29/10/2011 11:20:46 PM]

* Component: $VTU_Labs/default.group/logic.views/cd_amplifier_test_bench Viewpoint: AC_DC_Tran_analysis.INCLUDE cd_amplifier_test_bench_AC_DC_Tran_analysis.spi.LIB $MGC_DESIGN_KIT/models/include_all.LIB $MGC_DESIGN_KIT/models/lib.eldo TT.LIB $MGC_DESIGN_KIT/models/res.spi RES_T.INCLUDE $MGC_DESIGN_KIT/models/include_all.PROBE W .PROBE V .PROBE I .PROBE S

.OPTION NOASCII

.OPTION MODWL

.OPTION ENGNOT

.OPTION AEX

.AC dec 10 1 10MEG

.DC

.TRAN 0.0001 50u 0

#### #### # # # # #### # # # # # # ## ## ## ## # # ## # # # # # ## # # ## # # # # # # # # # # # # # # # # # # # # # # # # # # # # # ## #### #### # # # # #### # # #### #### # # ##### #### ###### # # # # # # # # # # #### # # # # # # # ##### # # # # # ##### # # # # # # # # # # # # # #### #### #### # # #### ###### ## # # ##### # # ###### # ###### ##### # # ## ## # # # # # # # # # # # # ## # # # # # ##### # ##### # # ###### # # ##### # # # # # ##### # # # # # # # # # # # # # # # # # ###### # # # ###### # #

file:///C|/Vishvakirana/nspice_spi_cir/csampl.eldo.nspice.txt[29/10/2011 11:21:20 PM]


** Globals.*.global VDD VSS GROUND

** Component pathname : $VTU_Labs/default.group/logic.views/common_source_amplifier*.subckt COMMON_SOURCE_AMPLIFIER VB VIN VOUT

V2 GROUND VSS DC 1.2V V1 VDD GROUND DC 1.2V M2 VOUT VIN VDD VDD pmos w=12u l=2u m=1 as=4.56p ad=4.56p ps=24.76u+ pd=24.76u M1 VOUT VB VSS VSS nmos w=9u l=2u m=1 as=3.42p ad=3.42p ps=18.76u+ pd=18.76u.ends COMMON_SOURCE_AMPLIFIER

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/cs_amplifier_test_bench* V3 VIN N$4 DC 0V AC 1 0 SIN ( 0 1mv 10k 0 0 ) V2 N$4 GROUND DC 700.79mV V1 NETVB GROUND DC -783.48mV X_COMMON_SOURCE_AMPLIFIER1 NETVB VIN VOUT COMMON_SOURCE_AMPLIFIER*.end

file:///C|/Vishvakirana/nspice_spi_cir/cs_amplifier_test_bench_DC_AC_Tran_Analysis.spi.txt[29/10/2011 11:21:20 PM]






** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/cs_amplifier_test_bench* V3 VIN N$4 DC 0V AC 1 0 SIN ( 0 1mv 10k 0 0 ) V2 N$4 GROUND DC 700.79mV V1 NETVB GROUND DC -783.48mV X_COMMON_SOURCE_AMPLIFIER1 NETVB VIN VOUT COMMON_SOURCE_AMPLIFIER*.end

file:///C|/Vishvakirana/nspice_spi_cir/cs_amplifier_test_bench_DC_AC_Tran_Analysis.cir.txt[29/10/2011 11:21:20 PM]

* Component: $VTU_Labs/default.group/logic.views/cs_amplifier_test_bench Viewpoint: DC_AC_Tran_Analysis.INCLUDE cs_amplifier_test_bench_DC_AC_Tran_Analysis.spi.LIB $MGC_DESIGN_KIT/models/include_all.LIB $MGC_DESIGN_KIT/models/lib.eldo TT.LIB $MGC_DESIGN_KIT/models/res.spi RES_T.INCLUDE $MGC_DESIGN_KIT/models/include_all.PROBE W .PROBE V .PROBE I .PROBE S

.OPTION NOASCII

.OPTION MODWL

.OPTION ENGNOT

.OPTION AEX

.OPTION PROBOP2

.OPTION PROBOPX

.OP

.AC dec 10 1 10MEG

.DC V2 0 1.2 0.001

.TRAN 0.001 0.5m 0

##### # ###### ###### ###### ##### ###### # # ##### # ## # # # # # # # # # # ## # # # # # # # # # ##### ##### ##### # # ##### # # # # # # # # # # # # # # ##### # # # # # # ###### # # # # # # # # # # # ## # # # # # ##### # # # ###### # # ###### # # # # # # ###### ## # # ##### # # ###### # ###### ##### # # ## ## # # # # # # # # # # # # ## # # # # # ##### # ##### # # ###### # # ##### # # # # # ##### # # # # # # # # # # # # # # # # # ###### # # # ###### # #

file:///C|/Vishvakirana/nspice_spi_cir/diffampl.eldo.nspice.txt[29/10/2011 11:21:31 PM]

* ELDO netlist generated with ICnet by 'vsrinivas' on Thu Jul 29 2010 at 21:24:29

** Globals.*.global vdd vss ground

** Component pathname : $VTU_Labs/default.group/logic.views/differential_amplifier*.subckt differential_amplifier vb vout vin1 vin2

m4 n$1708 n$1708 vdd vdd pmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u v2 ground vss DC 1.2V v1 vdd ground DC 1.2V m7 n$1910 n$1910 vdd vdd pmos w=5u l=6u m=1 as=1.9p ad=1.9p ps=10.76u+ pd=10.76u m6 vb vb vss vss nmos w=9u l=2u m=1 as=3.42p ad=3.42p ps=18.76u+ pd=18.76u m5 n$427 vb vss vss nmos w=9u l=2u m=1 as=3.42p ad=3.42p ps=18.76u+ pd=18.76u m8 vb vb n$1910 vdd pmos w=5u l=6u m=1 as=1.9p ad=1.9p ps=10.76u+ pd=10.76u m3 vout n$1708 vdd vdd pmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u m2 vout vin2 n$427 n$427 nmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u m1 n$1708 vin1 n$427 n$427 nmos w=18u l=6u m=1 as=6.84p ad=6.84p+ ps=36.76u pd=36.76u.ends differential_amplifier

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/differential_amplifier_test_bench* v4 ground n$416 DC 0V AC 1 0 SIN ( 0 0.45mv 10k 0 0 ) v3 n$415 ground DC 0V AC 1 0 SIN ( 0 0.45mv 10k 0 0 ) v1 vin2 n$415 DC 0.75 v2 vin1 n$416 DC 0.75 x_differential_amplifier1 vbias vout2 vin1 vin2 differential_amplifier*.end

file:///C|/Vishvakirana/nspice_spi_cir/differential_amplifier_test_bench_AC_DC_Tran_Analysis.spi.txt[29/10/2011 11:21:32 PM]




** Component pathname : $VTU_Labs/default.group/logic.views/differential_amplifier*.subckt DIFFERENTIAL_AMPLIFIER VB VOUT VIN1 VIN2

M4 N$1708 N$1708 VDD VDD pmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u V2 GROUND VSS DC 1.2V V1 VDD GROUND DC 1.2V M7 N$1910 N$1910 VDD VDD pmos w=5u l=6u m=1 as=1.9p ad=1.9p ps=10.76u+ pd=10.76u M6 VB VB VSS VSS nmos w=9u l=2u m=1 as=3.42p ad=3.42p ps=18.76u+ pd=18.76u M5 N$427 VB VSS VSS nmos w=9u l=2u m=1 as=3.42p ad=3.42p ps=18.76u+ pd=18.76u M8 VB VB N$1910 VDD pmos w=5u l=6u m=1 as=1.9p ad=1.9p ps=10.76u+ pd=10.76u M3 VOUT N$1708 VDD VDD pmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u M2 VOUT VIN2 N$427 N$427 nmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u M1 N$1708 VIN1 N$427 N$427 nmos w=18u l=6u m=1 as=6.84p ad=6.84p+ ps=36.76u pd=36.76u.ends DIFFERENTIAL_AMPLIFIER

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/differential_amplifier_test_bench* V4 GROUND N$416 DC 0V AC 1 0 SIN ( 0 0.45mv 10k 0 0 ) V3 N$415 GROUND DC 0V AC 1 0 SIN ( 0 0.45mv 10k 0 0 ) V1 VIN2 N$415 DC 0.75 V2 VIN1 N$416 DC 0.75 X_DIFFERENTIAL_AMPLIFIER1 VBIAS VOUT2 VIN1 VIN2 DIFFERENTIAL_AMPLIFIER*.end

file:///C|/Vishvakirana/nspice_spi_cir/differential_amplifier_test_bench_AC_DC_Tran_Analysis.cir.txt[29/10/2011 11:21:32 PM]

* Component: $VTU_Labs/default.group/logic.views/differential_amplifier_test_bench Viewpoint: AC_DC_Tran_Analysis.INCLUDE differential_amplifier_test_bench_AC_DC_Tran_Analysis.spi.LIB $MGC_DESIGN_KIT/models/include_all.LIB $MGC_DESIGN_KIT/models/lib.eldo TT.LIB $MGC_DESIGN_KIT/models/res.spi RES_T.INCLUDE $MGC_DESIGN_KIT/models/include_all.PROBE W .PROBE V .PROBE I .PROBE S

.OPTION NOASCII

.OPTION MODWL

.OPTION ENGNOT

.OPTION AEX

.OPTION PROBOP2

.OPTION PROBOPX

.OP

.AC dec 10 1 10MEG

.DC

.TRAN 0.0001 0.5m 0

#### ##### ## # # ##### # # # # # # ## ## # # # # # # ##### # # # ## # # # # # ##### ###### # # ##### # # # # # # # # #### # # # # # #

file:///C|/Vishvakirana/nspice_spi_cir/opamp.eldo.nspice.txt[29/10/2011 11:21:45 PM]

* ELDO netlist generated with ICnet by 'vsrinivas' on Mon Jul 26 2010 at 18:09:01

** Globals.*.global vdd vss ground

** Component pathname : $VTU_Labs/default.group/logic.views/differential_amplifier*.subckt differential_amplifier vb vout vin1 vin2

m4 n$1708 n$1708 vdd vdd pmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u v2 ground vss DC 1.2V v1 vdd ground DC 1.2V m7 n$1910 n$1910 vdd vdd pmos w=5u l=6u m=1 as=1.9p ad=1.9p ps=10.76u+ pd=10.76u m6 vb vb vss vss nmos w=9u l=2u m=1 as=3.42p ad=3.42p ps=18.76u+ pd=18.76u m5 n$427 vb vss vss nmos w=9u l=2u m=1 as=3.42p ad=3.42p ps=18.76u+ pd=18.76u m8 vb vb n$1910 vdd pmos w=5u l=6u m=1 as=1.9p ad=1.9p ps=10.76u+ pd=10.76u m3 vout n$1708 vdd vdd pmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u m2 vout vin2 n$427 n$427 nmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u m1 n$1708 vin1 n$427 n$427 nmos w=18u l=6u m=1 as=6.84p ad=6.84p+ ps=36.76u pd=36.76u.ends differential_amplifier

** Component pathname : $VTU_Labs/default.group/logic.views/common_source_amplifier*.subckt common_source_amplifier vb vin vout

v2 ground vss DC 1.2V v1 vdd ground DC 1.2V m2 vout vin vdd vdd pmos w=12u l=2u m=1 as=4.56p ad=4.56p ps=24.76u+ pd=24.76u m1 vout vb vss vss nmos w=9u l=2u m=1 as=3.42p ad=3.42p ps=18.76u+ pd=18.76u.ends common_source_amplifier

** Component pathname : $VTU_Labs/default.group/logic.views/op_amp*.subckt op_amp vout vin1 vin2

x_differential_amplifier1 n$214 n$212 vin1 vin2 differential_amplifier x_common_source_amplifier1 n$214 n$212 vout common_source_amplifier.ends op_amp

file:///C|/Vishvakirana/nspice_spi_cir/opamp.eldo.nspice.txt[29/10/2011 11:21:45 PM]

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/op_amp_test_bench* v3 vin1 n$5 DC 0V AC 1 0 SIN ( 0 1uv 10k 0 0 ) v2 n$5 ground DC 0.75V v1 vin2 ground DC 0.75V x_op_amp1 vout vin1 vin2 op_amp*.end

file:///C|/Vishvakirana/nspice_spi_cir/op_amp_test_bench_AC_DC_Tran_Analysis.spi.txt[29/10/2011 11:21:45 PM]





M4 N$1708 N$1708 VDD VDD pmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u M7 N$1910 N$1910 VDD VDD pmos w=5u l=6u m=1 as=1.9p ad=1.9p ps=10.76u+ pd=10.76u M6 VB VB VSS VSS nmos w=9u l=2u m=1 as=3.42p ad=3.42p ps=18.76u+ pd=18.76u M5 N$427 VB VSS VSS nmos w=9u l=2u m=1 as=3.42p ad=3.42p ps=18.76u+ pd=18.76u M8 VB VB N$1910 VDD pmos w=5u l=6u m=1 as=1.9p ad=1.9p ps=10.76u+ pd=10.76u M3 VOUT N$1708 VDD VDD pmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u M2 VOUT VIN2 N$427 N$427 nmos w=18u l=6u m=1 as=6.84p ad=6.84p ps=36.76u+ pd=36.76u M1 N$1708 VIN1 N$427 N$427 nmos w=18u l=6u m=1 as=6.84p ad=6.84p+ ps=36.76u pd=36.76u.ends DIFFERENTIAL_AMPLIFIER



** Component pathname : $VTU_Labs/default.group/logic.views/op_amp*.subckt OP_AMP VOUT VIN1 VIN2

file:///C|/Vishvakirana/nspice_spi_cir/op_amp_test_bench_AC_DC_Tran_Analysis.spi.txt[29/10/2011 11:21:45 PM]

X_DIFFERENTIAL_AMPLIFIER1 N$214 N$212 VIN1 VIN2 DIFFERENTIAL_AMPLIFIER X_COMMON_SOURCE_AMPLIFIER1 N$214 N$212 VOUT COMMON_SOURCE_AMPLIFIER.ends OP_AMP

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/op_amp_test_bench* V3 VIN1 N$5 DC 0V AC 1 0 SIN ( 0 1uv 10k 0 0 ) V2 N$5 GROUND DC 0.75V V1 VIN2 GROUND DC 0.75V X_OP_AMP1 VOUT VIN1 VIN2 OP_AMP*.end

file:///C|/Vishvakirana/nspice_spi_cir/op_amp_test_bench_AC_DC_Tran_Analysis.cir.txt[29/10/2011 11:21:45 PM]

* Component: $VTU_Labs/default.group/logic.views/op_amp_test_bench Viewpoint: AC_DC_Tran_Analysis.INCLUDE op_amp_test_bench_AC_DC_Tran_Analysis.spi.LIB $MGC_DESIGN_KIT/models/include_all.LIB $MGC_DESIGN_KIT/models/lib.eldo TT.LIB $MGC_DESIGN_KIT/models/res.spi RES_T.INCLUDE $MGC_DESIGN_KIT/models/include_all.PROBE W .PROBE V .PROBE I .PROBE S

.OPTION NOASCII

.OPTION MODWL

.OPTION ENGNOT

.OPTION AEX

.OPTION PROBOP2

.OPTION PROBOPX

.OP

.AC dec 10 1 10MEG

.DC

.TRAN 0.0001 1m 0

###### ##### ###### # # # # # # # # # # # ###### ##### ##### ###### # # # # # # # # # # # # ####### # #

file:///C|/Vishvakirana/nspice_spi_cir/r2rladder.eldo.nspice.txt[29/10/2011 11:21:58 PM]

* ELDO netlist generated with ICnet by 'vsrinivas' on Sat May 22 2010 at 11:42:37






** Component pathname : $VTU_Labs/default.group/logic.views/op_amp*.subckt OP_AMP VOUT VIN1 VIN2


file:///C|/Vishvakirana/nspice_spi_cir/r2rladder.eldo.nspice.txt[29/10/2011 11:21:58 PM]

** Component pathname : $VTU_Labs/default.group/logic.views/R-2R_ladder_DAC*.subckt R-2R_LADDER_DAC VOUT B0 B1 B2 B3 VBIAS

R8 N$626 VOUT 1K R7 VOUT B3 2K X_OP_AMP1 VOUT VOUT VBIAS OP_AMP R6 N$4 N$626 1K R5 N$10 N$4 1K R4 GROUND N$10 2K R3 N$626 B2 2K R2 N$4 B1 2K R1 N$10 B0 2K.ends R-2R_LADDER_DAC

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/R-2R_ladder_DAC_test_bench* X_R-2R_LADDER_DAC1 VOUT B0 B1 B2 B3 GROUND R-2R_LADDER_DAC V4 B0 GROUND PATTERN 1.2 0 0 1p 1p 5n 0101010101010101 V3 B1 GROUND PATTERN 1.2 0 0 1p 1p 5n 0011001100110011 V2 B2 GROUND PATTERN 1.2 0 0 1p 1p 5n 0000111100001111 V1 B3 GROUND PATTERN 1.2 0 0 1p 1p 5n 0000000011111111*.end

file:///C|/Vishvakirana/nspice_spi_cir/R-2R_ladder_DAC_test_bench_DC_Tran_analysis.spi.txt[29/10/2011 11:21:59 PM]


* ELDO netlist generated with ICnet by 'vsrinivas' on Sat May 22 2010 at 11:42:37






** Component pathname : $VTU_Labs/default.group/logic.views/op_amp

file:///C|/Vishvakirana/nspice_spi_cir/R-2R_ladder_DAC_test_bench_DC_Tran_analysis.spi.txt[29/10/2011 11:21:59 PM]

*.subckt OP_AMP VOUT VIN1 VIN2


** Component pathname : $VTU_Labs/default.group/logic.views/R-2R_ladder_DAC*.subckt R-2R_LADDER_DAC VOUT B0 B1 B2 B3 VBIAS

R8 N$626 VOUT 1K R7 VOUT B3 2K X_OP_AMP1 VOUT VOUT VBIAS OP_AMP R6 N$4 N$626 1K R5 N$10 N$4 1K R4 GROUND N$10 2K R3 N$626 B2 2K R2 N$4 B1 2K R1 N$10 B0 2K.ends R-2R_LADDER_DAC

** MAIN CELL: Component pathname : $VTU_Labs/default.group/logic.views/R-2R_ladder_DAC_test_bench* X_R-2R_LADDER_DAC1 VOUT B0 B1 B2 B3 GROUND R-2R_LADDER_DAC V4 B0 GROUND PATTERN 1.2 0 0 1p 1p 5n 0101010101010101 V3 B1 GROUND PATTERN 1.2 0 0 1p 1p 5n 0011001100110011 V2 B2 GROUND PATTERN 1.2 0 0 1p 1p 5n 0000111100001111 V1 B3 GROUND PATTERN 1.2 0 0 1p 1p 5n 0000000011111111*.end

file:///C|/Vishvakirana/nspice_spi_cir/R-2R_ladder_DAC_test_bench_DC_Tran_analysis.cir.txt[29/10/2011 11:21:59 PM]

* Component: $VTU_Labs/default.group/logic.views/R-2R_ladder_DAC_test_bench Viewpoint: DC_Tran_analysis.INCLUDE R-2R_ladder_DAC_test_bench_DC_Tran_analysis.spi.LIB $MGC_DESIGN_KIT/models/include_all.LIB $MGC_DESIGN_KIT/models/lib.eldo TT.LIB $MGC_DESIGN_KIT/models/res.spi RES_T.INCLUDE $MGC_DESIGN_KIT/models/include_all.PROBE W .PROBE V .PROBE I .PROBE S.PROBE TRAN V(VOUT)

.OPTION NOASCII

.OPTION MODWL

.OPTION ENGNOT

.OPTION AEX

.OPTION PROBOP2

.OPTION PROBOPX

.OP

.DC

.TRAN 0.001 80n 0

Using Mentor Graphics

Design Kit

2

Table of Contents

Table of Contents ……………………………………………………………. 2 Using the Design Kit …..…………………………………………………….. 3 Software Requirements ……………….……………………….…………… 3 Prerequisites ………………………………………………………...………… 4 Design Kit Contents …...……………………………………………….. 4 Design Kit Specification …...……………………………………………….. 5 Creating a Project …………………………………………………………….. 7 Creating a Library …………………………………………………………….. 12 Creating a Schematic Cell View…………………………………………….... 13 Simulating Schematic……………………………………………………….... 26 Creating a Layout Cell View…………………………………………………. 33 Verification of Layout…………………………………………………………. 39

3

Using the Design Kit The Design Kit is designed to provide an introduction to the analog design flow using the Mentor Graphics Custom IC Design products, which include ICStudio, Design Architect-IC and the ICgraph Suite of tools. It includes all the necessary items to guide you through the process of creating a schematic, setting up a testbench, simulating a design and laying out that design.

With the lessons that follow you will also become familiar with the analog design flow into the EldoTM simulation product using the ICNet netlister. The Eldo simulator offers numerous simulation and modeling options for SPICE- level simulations. Its unique "divide and conquer" partitioning scheme allows use of different algorithms on differing portions of a design, yielding high-accuracy in combination with high performance.

ICStudio manages the flow. It calls the Front End and Back End tools. The tools load the userware of this kit. The userware is designed in a way that enables you to use the tools efficiently. The dialog boxes give you the option to enter the device properties in different combinations. For example, you can enter two parameters of (R, W and L) of a resistor, and the dialog box will calculate for you the third value. In addition you can check the entered and calculated values for each device to avoid out of range values.

Software Requirements 1. Design Architect – IC v2005.1_1.1 or greater. (To check the version, enter the da_ic -version command.) 2. Eldo version v6.5_1.1 or greater. (To check the version, enter the $anacad/bin/eldo -rel command.) 3. ICgraph v2005.1_1.1 or greater. (To check the version, enter the ic -version command.) 4. Calibre.

4

Prerequisites 1. You must have MGC_HOME pointing to a valid installed Mentor Graphics Flow 2005.1 tree or a more recent release 2. You must have the Anacad software installed on your network and accessible via $anacad.

Design Kit Contents

Go into the installed design kit directory then list it by typing ls. The following sub-directories will be listed. docs - This directory is where the User Guide and the FSA check list of the Kit

exist.

qual_doc- This directory is where the QA sheet of the Kit exists.

models - This directory is where the Eldo models exist.

process - This directory contains the design kit’s process definition files.

rule_deck - This directory contains foundry Calibre rule files.

symbols - This directory contains all the kit symbols.

userware - This directory contains the DA-IC and IC Station userware.

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<insert spec.htm here>

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Creating a Project Step 1 To invoke ICStudio do the following:

Open ICStudio by typing the command icstudio & The ICStudio interface will be invoked and appear on the screen

Menu Bar and Icons Area

Libraries Area

Cells Area

Views Area

Transcript Log Area

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Step 2 To create a project click on File > New > Project from the menu bar. The New Project setup wizard will open to help you in creating the new project. Press Next to proceed with the wizard.

Step 3 Enter the project name and browse for the project location and then press Next.

Step 4 Press on the Open Location Map Editor button to set your location map.

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Step 5 Select Edit Menu followed by Add MGC Design Kit. This will add a row with a library name MGC_DESIGN_KIT. Browse for the kit installation directory in the location area.

Step 6 To add the standard libraries, select Edit Menu, and then select Add Standard

MGC Libraries. Step 7 After that press OK. This will return you back to the main wizard. Press Next to

proceed.

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Step 8 This will move you on to the Technology Settings. Press Open Setting Editor to set the technology settings.

Step 9 Browse for the paths of the Process file, DRC, LVS, SDL and PEX rules files. Step 10 Click on Miscellaneous tab. Write “$MGC_DESIGN_KIT/userware” in the

AMPLE_PATH field.

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Step 11 Press OK to return back to the main wizard. A summary of all the previous steps will then be shown.

Step 12 Press Finish to finalize the creation of new project. This is how the ICStudio

interface will look like after creating the new project.

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Creating a Library Step 1 To create a library click on File > New > Library from the menu bar. A window

will pop-up asking you for the library name.

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Creating a Schematic Cell View Step 1 To create a schematic cell click on File > New > View from the menu bar. A

window will pop-up asking for the cell name, and view type. Let the cell name be inverter and choose Schematic as view type, the view name will be named automatically Schematic.

Step 2 By Pressing Finish this will open the Design-Architect IC for you.

Workspace

Palette

Left Icon Palette

Icon & Menu bar

Pull Down

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The graphic interface is divided into four main sections – a menu bar, a workspace, and a palette. The menu bar and palette change to reflect the design task you select – laying out a schematic, setting up a testbench, or simulating a design. [As you are working with your design you will notice that the gray bar below the menu (the Info bar) contains information that changes dynamically as you go about your tasks.] The workspace provides a snap to grid for manipulating primitive-level components or higher level symbols.

Function key shortcuts Function key shortcuts provide quick one- or two-button access to common tasks like Copy, Paste, Select All, Unselect All. The function keys work in conjunction with the Shift, Control and Alt keys to provide up to four separate actions per key. To display function key shortcuts select Setup > Session and select Show Softkey Area.

Strokes with middle mouse button Design Architect–IC provides a number of shortcuts to common actions by utilizing the middle mouse button. While holding down the middle mouse button you can make simple, alphabet-like strokes in the workspace to quickly copy, move, zoom in or out, view an area or view all, delete or undo, unselect all and flip horizontally... to name just a few. To display the Quick Help on Strokes dialog box draw “?” with the middle mouse button.

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Hot keys Hot keys also provide shortcuts to a lot of functions. To get the complete list of hot key select Setup> Hotkeys > Report.

Creating a Schematic In this section you will become familiar with placing primitive analog devices for a inverter. You’ll learn how to: • place primitives on the schematic • select and manipulate devices • customizing hotkeys for placing devices • route devices • edit device parameter values • name instances • check and save the schematic • create upper hierarchical symbols • create test bench • simulate using Eldo • view results Primitive devices are selected from the design kit device library shipped with Design Architect-IC.

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Creating an Inverter Placing Devices Step 1 From the left icon palette press on Add Device icon. The Design Kit Devices

dialog box containing the entire device list for this process will pop-up. You can also press key a to call the same dialog box. Below is a typical form.

Step 2 Select the NMOS_DEVICE_MODEL from the Design Kit Devices dialog list box

to add an analog NMOS transistor. Select the NMOS_DEVICE_MODEL, press OK. Adjust any properties in the Add Instance form that comes up (sample below), then click either Apply (which accepts the change and leaves the form up). A ghost image of the transistor will be tied to the cursor. Place the NMOS transistor in the schematic. Note: you can also use the Add Instance icon and navigate to library MGC_DESIGN_KIT, cell NMOS_DEVICE_MODEL, view Symbol and add the device that way.

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Step 3 In the Add Instance form, click inside the Cell (C) field so you are editing in it, and

change the NMOS_DEVICE_MODEL to PMOS_DEVICE_MODEL. The dialog box will be refreshed, then click on Apply and place the PMOS_DEVICE_MODEL.

The schematic should now look similar to:

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Adding Ports and Connecting the Devices Step 1 Power could be added by pressing “Add Instance” icon in the left icon palette or

the hot key i. This will call the Add Instance window. Select the MGC_IC_GENERIC_LIB library followed by VDD cell and its Symbol view. Place it in the schematic window. Do the same for Ground.

Step 2 Place the IN and OUT ports in a similar way or by pressing the “Add Port” icon in the left icon palette.

Step 3 Place the cursor over the NET on the left of the IN port. Select Shift-F7 key. This

will bring up a form as shown below. Enter IN for the net name. Step 4 Connect the devices by dragging the mouse from the pin of the device. You can

also use the hot key w.

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Step 5 Do the same for the OUT net. The schematic should now look similar to. Step 6 Now from the right palette select Check & Save.

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Changing Parameter Values Your schematic is complete and you will now need to create a testbench for simulation. You can manipulate devices and change device parameters by the following method that is described below. If you are satisfied with the devices you may skip to the section entitled generating a Symbol to continue. Changing Device Parameters To change parameters on a device, select it and then either use the "q" hotkey or click on the Edit Object Properties icon on the toolbar. The Edit Object Properties form appears, similar to the form below. The Edit Object Properties form is similar to the Add Instance form. Now, you can change the parameters you want by selecting them from the list, changing their value, and then clicking Apply or OK. The valid ranges are checked and the valid choices for each property are given.

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Selecting and manipulating instances Devices can be selected with the left mouse button or by pressing the F1 function key while the cursor is over the device. With the Edit section of the schematic_edit palette you can Move, Copy, Delete, Undo, Flip or Rotate the instance.

The Flip Horizontal and Rotate strokes allow you to quickly manipulate

selected devices as do the f and r hotkeys. Unselect a device with the Unselect All stroke or by pressing the F2 key

Generating a Symbol Step 1 Select Tools > Generate Symbol from the pull down menu.

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Step 2 When you select generate symbol the next form to will popup. You can OK the form or you can change the shape to be a buffer and add a circle to create a classic inverter shape.

Step 3 You can select Circle from the symbol draw menu to add a circle to the inverter

symbol.

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Step 4 When you finish editing the symbol click Check & Save.

Creating a Testbench

Step 1 Go back to ICstudio. Notice that now the created lib contains a cell named inverter with two views, a Schematic and Symbol view. Create a new cell with a Schematic view named test_bench.

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Step 2 Now instantiate the new inverter symbol by selecting Add > Instance from the Schematic Edit Palette menu or pressing the hot key i. Select the Symbol view of the inverter cell.

Step 3 Add the IN and OUT net as before by selecting the hot key i. Name the nets with

shift-F7 function key. Step 4 Add VDD and Ground ports in a similar fashion. Step 5 Add a DC voltage source dc_v_source, from the MGC_IC_SOURCES_LIB.

Change the value of the DC property to be 3.3V. Add PULSE voltage source pulse_v_source and change the value of the pulse_value property to be 3.3V change also the delay to be 0S.

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The test_bench schematic should look similar to the next figure.

Step 6 Select Check & Save to Save schematic changes.

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Simulating Schematic Simulating the Testbench

Step 1 When you have no errors select the Simulation icon from the left icon palette to go into design context and simulate our design.

Step 2 Click ok when this form appears.

Now you are in the Design context and need to setup the analysis type, plots and load in the Eldo models.

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Step 4 Select the Setup Analysis icon. This will open a form for you to select the

analysis type. Select Transient followed by selecting the Setup button. Step 5 Let the Stop Time (TSTOP) be 100n and OK the two forms.

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Step 6 Now select the IN and OUT terminals by holding down the left mouse button and drawing a box around the terminals while pressing Shift. This will cause the wires to be highlighted.

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Step 7 While the IN and OUT nets are selected press on the Setup Outputs icon from the Icon Palette. This dialog box will appear. Select Selected Components tab make sure the Plot Items(s) is selected, and click OK.

Step 8 Another window will appear asking about the plot type, select Individually then

OK.

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Step 9 create a netlist by selecting Netlist in the Execute section or Simulation > Create

Netlist . This will open a xterm window. Press Return to close the xterm window. Step 10 View the netlist by selecting: ASCII files > View Netlist in the Results session or

View > Netlist File.

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Step 11 The netlist should look similar to this: Step 12 Close the netlist window (Shift–F12) or right-to-left stroke and select the Run

ELDO button under the Simulation Section or select Run icon. This will open another xterm.Press Return to close the Simulation xterm.

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Step 13 View the simulation results by selecting the View Waves button under the Results section of the Simulation Palette or by selecting the View Outputs icon. This will open EZWave for you with the output waveforms. This is how the waveforms look like after zooming.

Step 14 Close EZwave and DA_IC.

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Creating a Layout Cell View Step 1 To create a layout cell view select the inverter cell and click on File > New >

View from the menu bar. A window will pop-up asking for the cell view type. Choose Layout as view type, the view name will be named automatically Layout.

Step 2 By pressing Next a new window will appear asking you for the Connectivity

Source select Schematic to open IC-Station in the SDL mode.

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Step 3 By Pressing Finish this will open IC-Station.

Creating SDL

Step 1 Make the Schematic window active by selecting it with the LMB. Press on the Auto Pick & Place icon from the Icon Bar. The tool will place the devices one by one.

IC Window

Layer Palette Pull Down

Menu

Schematic Window

Icon Bar

Icon Palette

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You have now instantiated the pmos and nmos and the connectivity is maintained as illustrated by the fly lines. Next you will add ports and complete the routing.

Step 2 With the layout window active, select the Pick Place Ports icon from the icon bar. Step 3 Select the VDD port and select MET1 as a layer for this port. The Width and

Height will be updated automatically according to the minimum metal1 dimensions. Press Apply to place the port.

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Step 4 Place the rest of the ports. Step 5 To add the substrate contacts to the mosfets. Select Add Device icon from the

Left Hand Palette then select Path-based Guard Band select psub.

Step 6 Do the same for but choose nwell instead of psub. Step 7 To add the over flow lines for both psub & nwell , Select psub then Connectivity >

Net > Add to Net to set psub to Ground and the same for nwell to set it to VDD.

VDD

IN OUT

GROUND

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Routing Layout Step 1 Select the Layout window and maximize it. This will create a full window image of

the layout. Step 2 To start routing press on the IRoute icon in the icon bar. Once you place the

cursor on where you want to start routing, it will start guided by the fly lines. You can toggle between the connectivity layers by pressing space-bar.

After completion,You should see something similar to the shown below

VDD

IN OUT

GROUND

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Step 3 Add text labels to the ports to make them recognizable by LVS by pressing the

hot key l or select Add > Text This is how the layout will look like

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Verification of Layout Now you can verify the layout by running DRC and LVS checks. we will run Calibre Interactive.

Running Calibre Interactive DRC Step 1 Select Tools > Calibre > Run DRC entry from the pull down menu. Step 2 This will bring up the Calibre Interactive – DRC. Select Rules button and notice that the rule file is loaded automatically.

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Step 3 Select Run DRC. Step 4 The Calibre RVE window will popup and you should see the following results. Running Calibre Interactive LVS Step 1 Select Tools > Calibre > Run LVS entry from the pull down menu. Step 2 The Calibre Interactive – LVS window will popup. Make sure Export from

schematic viewer is selected while the Inputs and Netlist tabs are active as shown.

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Step 3 Select Run LVS. Step 4 Calibre RVE window will popup and you should see results similar to this.

This completes the Design Kit User Guide.

Thank you

http://www.scribd.com/doc/63645000/User-Guide-Using-mentor-graphics-design-kit

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7th Sem VLSI Lab Manual using Mentor Graphics

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