Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 1
//INVERTER
module inverter ( input_i, output_o ) ;
input input_i ;
output output_o ;
reg output_o;
always @(input_i)
begin
if (input_i)
output_o = 1'b0;
else
output_o = 1'b1;
end
endmodule
//INVERTER TESTBENCH
module inverter_test ;
reg input_i ;
wire output_o;
inverter inverter_dut(.input_i(input_i ), .output_o(output_o));
initial
input_i = 1'b0;
always
#5 input_i = !input_i;
initial
begin
$monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o);
#2000 $finish ;
end
endmodule
//INVERTER GATELEVEL TESTBENCH
module inverter_test ;
reg input_i ;
wire output_o;
inverter inverter_dut(.input_i(input_i ),.output_o(output_o));
initial
input_i = 1'b0;
always
#5 input_i = !input_i;
initial
begin
$monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o);
#2000 $finish ;
end
initial
begin
$sdf_annotate("inverter.sdf",inverter_test.inverter_dut, , , "maximum");
end
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 2
//BUFFER
module buffer (input_i,output_o);
input input_i;
output output_o;
reg output_o;
always @(input_i)
begin
if (input_i)
output_o = 1'b1;
else
output_o = 1'b0;
end
endmodule
//BUFFER TESTBENCH
module buffer_test ;
reg input_i ;
wire output_o;
buffer buffer_dut(.input_i(input_i ), .output_o(output_o));
initial
input_i = 1'b0;
always
#5 input_i = !input_i;
initial
begin
$monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o);
#2000 $finish ;
end
endmodule
//BUFFER GATE LEVEL TESTBENCH
module buffer_test ;
reg input_i ;
wire output_o;
buffer buffer_dut(.input_i(input_i ),.output_o(output_o));
initial
input_i = 1'b0;
always
#5 input_i = !input_i;
initial
begin
$monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o);
#2000 $finish ;
end
initial
$sdf_annotate("buffer.sdf",buffer_test.buffer_dut);
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 3
//TRANSMISSION GATE
module tgate (input_i, cntrl_i,output_o);
input input_i;
input cntrl_i;
output output_o;
reg output_o;
always @(input_i or cntrl_i)
begin
if (cntrl_i)
output_o = input_i;
else
output_o = 1'b0;
end
endmodule
//TRANSMISSION GATE TESTBENCH
module tgate_test ;
reg input_i ;
reg cntrl_i ;
wire output_o;
tgate tgate_dut(.input_i(input_i ),.cntrl_i(cntrl_i ),.output_o(output_o));
initial
begin
input_i = 1'b0; cntrl_i =1'b1;
#100 cntrl_i =1'b0 ;
#200 cntrl_i =1'b1 ;
end
always
#5 input_i = !input_i;
initial
begin
$monitor ($time ," Input_i =%b cntrl_i =%b and output_o =%b " ,input_i,cntrl_i,output_o);
#2000 $finish ;
end
endmodule
//TRANSMISSION GATE GATELEVEL TESTBENCH
module tgate_test ;
reg input_i ;
reg cntrl_i ;
wire output_o;
tgate tgate_dut(.input_i(input_i ),.cntrl_i(cntrl_i ),.output_o(output_o));
initial
begin
input_i = 1'b0; cntrl_i =1'b1;
#100 cntrl_i =1'b0 ;
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 4
#200 cntrl_i =1'b1 ;
end
always
#5 input_i = !input_i;
initial
begin
$monitor ($time ," Input_i =%b cntrl_i =%b and output_o =%b " ,input_i,cntrl_i,output_o);
#2000 $finish ;
end
initial
$sdf_annotate("tgate.sdf",tgate_test.tgate_dut,, ,"Maximum");
endmodule
//BASIC AND GATE
module basic_gate_and(a_i, b_i, c_o);
input a_i;
input b_i;
output c_o;
wire c_o;
assign c_o = a_i && b_i;
endmodule
//BASIC OR GATE
module basic_gate_or(a_i,b_i,c_o);
input a_i;
input b_i;
output c_o;
wire c_o;
assign c_o = a_i || b_i;
endmodule
//BASIC NAND GATE
module basic_gate_nand(a_i,b_i,c_o);
input a_i;
input b_i;
output c_o;
wire c_o;
assign c_o = ~(a_i && b_i);
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 5
//BASIC NOR GATE
module basic_gate_nor(a_i,b_i ,c_o);
input a_i;
input b_i;
output c_o;
wire c_o;
assign c_o = ~(a_i || b_i);
endmodule
//BASIC XOR GATE
module universal_gate_xor(a_i,b_i,c_o);
input a_i;
input b_i;
output c_o;
wire c_o;
assign c_o = a_i ^ b_i;
endmodule
//BASIC XNOR GATE
module universal_gate_xnor(a_i, b_i, c_o);
input a_i;
input b_i;
output c_o;
wire c_o;
assign c_o = ~(a_i ^ b_i);
endmodule
//BASIC UNIVERSAL GATES TESTBENCH
module basic_gates_test ;
reg a_i ;
reg b_i ;
wire [5:0]c_o;
basic_gate_and and_dut(.a_i(a_i ), .b_i(b_i ), .c_o(c_o[0]));
basic_gate_or or_dut(.a_i(a_i ), .b_i(b_i ),.c_o(c_o[1]));
basic_gate_nand nand_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[2]));
basic_gate_nor nor_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[3]));
universal_gate_xor xor_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[4]));
universal_gate_xnor xnor_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[5]));
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 6
initial
begin
$display ( $time ,"\t simulation of the and_gate begins " );
a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
initial
begin
#40 $display ( $time ," \t simulation of the or_gate begins " );
#10 a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
initial
begin
#100 $display ( $time ," \t simulation of the nand_gate begins " );
#10 a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
initial
begin
#150 $display ( $time ," \t simulation of the nor_gate begins " );
#10 a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
initial
begin
#200 $display ( $time ," \t simulation of the xor_gate begins " );
#10 a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 7
initial
begin
#250 $display ( $time ," \t simulation of the xnor_gate begins " );
#10 a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
initial
begin
#300 $finish ;
end
initial
begin
fork
$monitor ( $time , "\t a=%b b =%b and output of and gate c= %b" ,a_i,b_i,c_o[0] );
#50 $monitor ( $time , "\t a=%b b =%b and output of or gate c= %b" ,a_i,b_i,c_o[1] );
#110 $monitor ( $time , "\t a=%b b =%b and output of nand gate c= %b" ,a_i,b_i,c_o[2] );
#160 $monitor ( $time , "\t a=%b b =%b and output of nor gate c= %b" ,a_i,b_i,c_o[3] );
#210 $monitor ( $time , "\t a=%b b =%b and output of xor gate c= %b" ,a_i,b_i,c_o[4] );
#260 $monitor ( $time , "\t a=%b b =%b and output of xnor gate c= %b" ,a_i,b_i,c_o[5] );
join
end
endmodule
//BASIC UNIVERSAL GATES GATELEVEL TESTBENCH
module basic_gates_test ;
reg a_i ;
reg b_i ;
wire [5:0]c_o;
basic_gate_and and_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[0]));
basic_gate_or or_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[1]));
basic_gate_nand nand_dut( .a_i(a_i), .b_i(b_i ), .c_o(c_o[2]));
basic_gate_nor nor_dut( .a_i(a_i ), .b_i(b_i ), .c_o(c_o[3]));
universal_gate_xor xor_dut( .a_i(a_i ), .b_i(b_i ), .c_o(c_o[4]));
universal_gate_xnor xnor_dut( .a_i(a_i ), .b_i(b_i ), .c_o(c_o[5]));
initial
begin
$display ( $time ,"\t simulation of the and_gate begins " );
a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 8
initial
begin
#40 $display ( $time ," \t simulation of the or_gate begins " );
#10 a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
initial
begin
#100 $display ( $time ," \t simulation of the nand_gate begins " );
#10 a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
initial
begin
#150 $display ( $time ," \t simulation of the nor_gate begins " );
#10 a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
initial
begin
#200 $display ( $time ," \t simulation of the xor_gate begins " );
#10 a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
initial
begin
#250 $display ( $time ," \t simulation of the xnor_gate begins " );
#10 a_i =1'b0 ; b_i =1'b0;
#10 a_i =1'b0 ; b_i =1'b1;
#10 a_i =1'b1 ; b_i =1'b0;
#10 a_i =1'b1 ; b_i =1'b1;
#5 $display ( " \n" );
end
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 9
initial
begin
#300 $finish ;
end
initial
begin
fork
$monitor ( $time , "\t a=%b b =%b and output of and gate c= %b" ,a_i,b_i,c_o[0] );
#50 $monitor ( $time , "\t a=%b b =%b and output of or gate c= %b" ,a_i,b_i,c_o[1] );
#110 $monitor ( $time , "\t a=%b b =%b and output of nand gate c= %b" ,a_i,b_i,c_o[2] );
#160 $monitor ( $time , "\t a=%b b =%b and output of nor gate c= %b" ,a_i,b_i,c_o[3] );
#210 $monitor ( $time , "\t a=%b b =%b and output of xor gate c= %b" ,a_i,b_i,c_o[4] );
#260 $monitor ( $time , "\t a=%b b =%b and output of xnor gate c= %b" ,a_i,b_i,c_o[5] );
join
end
initial
begin
$sdf_annotate("basic_gates_and.sdf",basic_gates_test.and_dut,, ,"Maximum");
$sdf_annotate("basic_gates_or.sdf",basic_gates_test.or_dut,, ,"Maximum");
$sdf_annotate("basic_gates_nand.sdf",basic_gates_test.nand_dut,, ,"Maximum");
$sdf_annotate("basic_gates_nor.sdf",basic_gates_test.nor_dut,, ,"Maximum");
$sdf_annotate("basic_gates_xor.sdf",basic_gates_test.xor_dut,, ,"Maximum");
$sdf_annotate("basic_gates_xnor.sdf",basic_gates_test.xnor_dut,, ,"Maximum");
end
endmodule
//RS FLIP FLOP
module rsflipflop (S,R,clock_i,q_o,qbar_o);
input clock_i;
input S;
input R;
output q_o;
output qbar_o;
wire q_o;
wire qbar_o;
dflipflop dff(.reset_i(1'b0),.clock_i(clock_i),.data_in_i(w3),.q_o(q_o),.qbar_o(qbar_o));
not n1 (w1 ,R );
and a1 (w2,w1,q_o);
or o1 (w3,S,w2);
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 10
//RS FLIP FLOP TESTBENCH
module rsflipflop_test;
reg clock_i;
reg R;
reg S;
wire q_o;
wire qbar_o;
rsflipflop rsff(.R(R),.S(S),.clock_i(clock_i),.q_o(q_o),.qbar_o(qbar_o));
initial
begin
clock_i =1'b0 ; R =1'b0;
end
always
#5 clock_i = !clock_i ;
initial
begin
#20 R =1'b1 ;
#20 S =1'b1 ; R =1'b0;
#20 S =1'b0 ; R =1'b0;
#30 S =1'b1 ; R =1'b1;
#10 S =1'b0 ; R =1'b1;
end
initial
begin
$monitor($time ," \t clock_i =%b R= %b S =%b q=%b qbar =%b ",clock_i,R,S,q_o,qbar_o);
#200 $finish;
end
endmodule
//RS FLIP FLOP GATELEVEL TESTBENCH
module rsflipflop_test;
reg clock_i;
reg R;
reg S;
wire q_o;
wire qbar_o;
rsflipflop rsff(.R(R),.S(S),.clock_i(clock_i),.q_o(q_o),.qbar_o(qbar_o));
initial
begin
clock_i =1'b0 ; R =1'b0;
end
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 11
always
#5 clock_i = !clock_i ;
initial
begin
#20 R =1'b1 ;
#20 S =1'b1 ; R =1'b0;
#20 S =1'b0 ; R =1'b0;
#80 S =1'b1 ; R =1'b1;
end
initial
begin
$monitor($time ," \t clock_i =%b R= %b S =%b q=%b qbar =%b ",clock_i,R,S,q_o,qbar_o);
#200 $finish;
end
initial
begin
$sdf_annotate ("rsflipflop.sdf",rsflipflop_test.rsff);
end
endmodule
//D FLIP FLOP
module dflipflop (reset_i, clock_i, data_in_i, q_o, qbar_o);
input clock_i;
input reset_i;
input data_in_i;
output q_o;
output qbar_o;
reg q_o;
wire qbar_o;
always @(posedge clock_i)
begin
if(reset_i)
q_o <=1'b0;
else
q_o <= data_in_i;
end
assign qbar_o = ~q_o;
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 12
//D FLIP FLOP TESTBENCH
module dflipflop_test;
reg clock_i;
reg reset_i;
reg data_in_i;
wire q_o;
wire qbar_o;
dflipflop dff(.reset_i(reset_i),.clock_i(clock_i),.data_in_i(data_in_i),.q_o(q_o),.qbar_o(qbar_o));
initial
begin
clock_i =1'b0 ; reset_i =1'b0;
end
always
#5 clock_i = !clock_i ;
initial
begin
#20 reset_i =1'b1 ;
#20 data_in_i = 1'b1;
#20 data_in_i = 1'b0; reset_i =1'b0;
#60 data_in_i = 1'b1; reset_i =1'b0;
#100 reset_i =1'b1;
end
initial
begin
$monitor($time ," \t clock_i =%b reset_i= %b data_in_i =%b q=%b qbar_o =%b
",clock_i,reset_i,data_in_i,q_o ,qbar_o);
#400 $finish;
end
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 13
//D FLIP FLOP GATE LEVEL TESTBENCH
module dflipflop_test;
reg clock_i;
reg reset_i;
reg data_in_i;
wire q_o;
wire qbar_o;
dflipflop dff(.reset_i(reset_i),.clock_i(clock_i),.data_in_i(data_in_i),.q_o(q_o),.qbar_o(qbar_o));
initial
begin
clock_i =1'b0 ; reset_i =1'b0;
end
always
#5 clock_i = !clock_i ;
initial
begin
#20 reset_i =1'b1 ;
#20 data_in_i = 1'b1;
#20 data_in_i = 1'b0; reset_i =1'b0;
#60 data_in_i = 1'b1; reset_i =1'b0;
#100 reset_i =1'b1;
end
initial
begin
$monitor($time ," \t clock_i =%b reset_i= %b data_in_i =%b q=%b qbar_o =%b
",clock_i,reset_i,data_in_i,q_o ,qbar_o);
#400 $finish;
end
initial
$sdf_annotate("dflipflop.sdf",dflipflop_test.dff,, ,"Maximum");
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 14
//JK FLIP FLOP
module jkflipflop (J_i,K_i,clock_i,q_o,qbar_o);
input clock_i;
input J_i;
input K_i;
output q_o;
output qbar_o;
reg q_o;
reg qbar_o;
always @(posedge clock_i)
begin
if(J_i && ~K_i)
begin
q_o <=1'b1;
qbar_o<=1'b0;
end
else
begin
if(~J_i && K_i )
begin
q_o <=1'b0;
qbar_o<=1'b1;
end
else
begin
if(~J_i && ~K_i )
begin
q_o <=q_o;
qbar_o<=qbar_o;
end
else
begin
q_o <=~q_o;
qbar_o<=~qbar_o;
end
end
end
end
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 15
//JK FLIP FLOP TESTBENCH
module jkflipflop_test;
reg clock_i;
reg K_i;
reg J_i;
reg data_in_i;
wire q_o;
wire qbar_o;
jkflipflop jkff(.K_i(K_i),.J_i(J_i),.clock_i(clock_i),.q_o(q_o),.qbar_o(qbar_o));
initial
begin
clock_i =1'b0 ; K_i =1'b0;
end
always
#5 clock_i = !clock_i ;
initial
begin
#20 K_i =1'b1 ;
#20 J_i =1'b1 ; K_i =1'b0;
#20 J_i =1'b0 ; K_i =1'b0;
#20 J_i =1'b1 ; K_i =1'b1;
end
initial
begin
$monitor($time ," \t clock_i =%b K_i= %b J_i =%b q=%b qbar =%b ",clock_i,K_i,J_i,q_o,qbar_o);
#200 $finish;
end
endmodule
//JK FLIP FLOP GATELEVEL TESTBENCH
module jkflipflop_test;
reg clock_i;
reg K_i;
reg J_i;
reg data_in_i;
wire q_o;
wire qbar_o;
jkflipflop jkff(.K_i(K_i),.J_i(J_i),.clock_i(clock_i),.q_o(q_o),.qbar_o(qbar_o));
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 16
initial
begin
clock_i =1'b0 ; K_i =1'b0;
end
always
#5 clock_i = !clock_i ;
initial
begin
#20 K_i =1'b1 ;
#20 J_i =1'b1 ; K_i =1'b0;
#20 J_i =1'b0 ; K_i =1'b0;
#20 J_i =1'b1 ; K_i =1'b1;
end
initial
begin
$monitor($time ," \t clock_i =%b K_i= %b J_i =%b q=%b qbar =%b ",clock_i,K_i,J_i,q_o,qbar_o);
#200 $finish;
end
initial
$sdf_annotate("jkflipflop.sdf",jkflipflop_test.jkff,, ,"Maximum");
endmodule
//MASTER SLAVE FLIP FLOP
module msflipflop (reset_i,clock_i,d_i,q_o);
input reset_i;
input clock_i;
input d_i;
output q_o;
wire w1;
dflipflop Master(.reset_i(reset_i),.clock_i(~clock_i),.data_in_i(d_i),.q_o(w1));
dflipflop Slave(.reset_i(reset_i),.clock_i(clock_i),.data_in_i(w1),.q_o(q_o));
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 17
//MASTER SLAVE FLIP FLOP TESTBENCH
module ms_test;
reg clock_i;
reg reset_i;
reg d_i;
wire q_o;
msflipflop ms(reset_i,clock_i,d_i,q_o);
initial
begin
clock_i =1'b0 ; reset_i =1'b0;
end
always
#5 clock_i = !clock_i ;
initial
begin
#20 reset_i =1'b1 ;
#20 d_i = 1'b1;
#20 d_i = 1'b0; reset_i =1'b0;
#60 d_i = 1'b1; reset_i =1'b0;
#100 reset_i =1'b1;
end
initial
begin
$monitor($time ," \t clock_i =%b reset_i= %b d_i =%b q=%b ",clock_i,reset_i,d_i,q_o);
#400 $finish;
end
endmodule
//MASTER SLAVE FLIP FLOP GATELEVEL TESTBENCH
module ms_test;
reg clock_i;
reg reset_i;
reg d_i;
wire q_o;
msflipflop ms(reset_i,clock_i,d_i,q_o);
initial
begin
clock_i =1'b0 ; reset_i =1'b0;
end
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 18
always
#5 clock_i = !clock_i ;
initial
begin
#20 reset_i =1'b1 ;
#20 d_i = 1'b1;
#20 d_i = 1'b0; reset_i =1'b0;
#60 d_i = 1'b1; reset_i =1'b0;
#100 reset_i =1'b1;
end
initial
begin
$monitor($time ," \t clock_i =%b reset_i= %b d_i =%b q=%b ",clock_i,reset_i,d_i,q_o);
#400 $finish;
end
initial
$sdf_annotate("masterslave.sdf",ms_test.ms,, ,"Maximum");
endmodule
//T FLIP FLOP
module tflipflop (reset_i,clock_i,T_i,q_o);
input clock_i;
input reset_i;
input T_i;
output q_o;
reg q_o;
always @(posedge clock_i)
begin
if(reset_i)
q_o <=1'b0;
else
begin
if(T_i)
q_o <= ~q_o;
else
q_o <= q_o;
end
end
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 19
//T FLIP FLOP TESTBENCH
module tflipflop_test;
reg clock_i;
reg reset_i;
reg T_i;
wire q_o;
tflipflop tff(.reset_i(reset_i),.clock_i(clock_i),.T_i(T_i),.q_o(q_o));
initial
begin
clock_i =1'b0 ; reset_i =1'b0;
end
always
#5 clock_i = !clock_i ;
initial
begin
#20 reset_i =1'b1 ;
#20 T_i = 1'b1;
#20 T_i = 1'b0; reset_i =1'b0;
#60 T_i = 1'b1; reset_i =1'b0;
#100 reset_i =1'b1;
end
initial
begin
$monitor($time ," \t clock_i =%b reset_i= %b T_i =%b q=%b ",clock_i,reset_i,T_i,q_o);
#400 $finish;
end
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 20
//T FLIP FLOP GATELEVEL TESTBENCH
module tflipflop_test;
reg clock_i;
reg reset_i;
reg T_i;
wire q_o;
tflipflop tff(.reset_i(reset_i),.clock_i(clock_i),.T_i(T_i),.q_o(q_o));
initial
begin
clock_i =1'b0 ; reset_i =1'b0;
end
always
#5 clock_i = !clock_i ;
initial
begin
#20 reset_i =1'b1 ;
#20 T_i = 1'b1;
#20 T_i = 1'b0; reset_i =1'b0;
#60 T_i = 1'b1; reset_i =1'b0;
#100 reset_i =1'b1;
end
initial
begin
$monitor($time ," \t clock_i =%b reset_i= %b T_i =%b q=%b ",clock_i,reset_i,T_i,q_o);
#400 $finish;
end
initial
$sdf_annotate("tflipflop.sdf",tflipflop_test.tff,, ,"Maximum");
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 21
//FULL ADDER
module full_adder(a,b,cin,sum,cout);
input a;
input b;
input cin;
output sum;
output cout;
assign sum = cin ^ a ^ b;
assign cout = (a && b ) || (b && cin) || (cin && a) ;
endmodule
//4BIT SERIAL ADDER
module adder_4_bit(x,y,cin,z,cout);
input [3:0] x ;
input [3:0] y ;
input cin;
output [3:0] z;
output cout;
wire [3:1] carry;
full_adder fa0(x[0],y[0],cin,z[0],carry[1]);
full_adder fa1(x[1],y[1],carry[1],z[1],carry[2]);
full_adder fa2(x[2],y[2],carry[2],z[2],carry[3]);
full_adder fa3(x[3],y[3],carry[3],z[3],cout);
endmodule
//4BIT SERIAL ADDER TESTBENCH
module adder_4_bit_tb;
reg [3:0] x ;
reg [3:0] y ;
reg cin;
wire [3:0] z;
wire cout;
wire [4:0] expected_result;
wire [4:0] actual_result;
adder_4_bit a0(x,y,cin,z,cout);
initial
begin
x = 0; y = 0; cin = 0;
#10 x = 4'b0101; y = 4'b0001; cin = 1'b0;
#10 x = 4'b0101; y = 4'b1110; cin = 1'b1;
#10 x = 4'b1111; y = 4'b1111; cin = 1'b1;
#10 x = 0; y = 0; cin = 0;
#10 $finish;
end
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 22
assign expected_result = x+y+cin;
assign actual_result = {cout,z};
initial
begin
if(actual_result!==expected_result)
$monitor ($time , " x= %d ,y =%d cin =%b ,expected_result=%d actual_result =%d,
the expected sum is not correct" , x ,y ,cin ,expected_result,actual_result);
else
$monitor ($time , " x= %d ,y =%d cin =%b expected_result=%d actual_result =%d ,
the expected sum is correct" , x ,y ,cin,expected_result,actual_result );
end
endmodule
//SERIAL ADDER GATE LEVEL TESTBENCH
module adder_4_bit_tb;
reg [3:0] x ;
reg [3:0] y ;
reg cin;
wire [3:0] z;
wire cout;
wire [4:0] expected_result;
wire [4:0] actual_result;
adder_4_bit a0(x,y,cin,z,cout);
initial begin
x = 0; y = 0; cin = 0;
#10 x = 4'b0101; y = 4'b0001; cin = 1'b0;
#10 x = 4'b0101; y = 4'b1110; cin = 1'b1;
#10 x = 4'b1111; y = 4'b1111; cin = 1'b1;
#10 x = 0; y = 0; cin = 0;
#10 $finish;
end
assign expected_result = x+y+cin;
assign actual_result = {cout,z};
initial
begin
if(actual_result!==expected_result)
$monitor ($time , " x= %d ,y =%d cin =%b ,expected_result=%d actual_result =%d ,
the expected sum is not correct" , x ,y ,cin ,expected_result,actual_result);
else
$monitor ($time , " x= %d ,y =%d cin =%b expected_result=%d actual_result =%d ,
the expected sum is correct" , x ,y ,cin,expected_result,actual_result );
end
initial
$sdf_annotate("serialadder.sdf",adder_4_bit_tb.a0,, ,"Maximum");
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 23
//PARALLEL ADDER GATELEVEL TESTBENCH
module adder_4_bit_tb;
reg [3:0] x ;
reg [3:0] y ;
reg cin;
wire [3:0] z;
wire cout;
wire [4:0] expected_result;
wire [4:0] actual_result;
cla_adder a0(.a_in(x),.b_in(y),.c_in(cin),.sum_o(z),.c_out(cout));
initial
begin
x = 0; y = 0; cin = 0;
#10 x = 4'b0101; y = 4'b0001; cin = 1'b0;
#10 x = 4'b0101; y = 4'b1110; cin = 1'b1;
#10 x = 4'b1111; y = 4'b1111; cin = 1'b1;
#10 x = 0; y = 0; cin = 0;
#10 $finish;
end
assign expected_result = x+y+cin;
assign actual_result = {cout,z};
initial
begin
if(actual_result!==expected_result)
$monitor ($time , " x= %d ,y =%d cin =%b ,expected_result=%d actual_result =%d ,the expected sum is not
correct" , x ,y ,cin ,expected_result,actual_result);
else
$monitor ($time , " x= %d ,y =%d cin =%b expected_result=%d actual_result =%d , the expected sum is
correct" , x ,y ,cin,expected_result,actual_result );
end
initial
$sdf_annotate("parlleladder.sdf",adder_4_bit_tb.a0,, ,"Maximum");
endmodule
//PARALLEL ADDER
module cla_adder(a_in, b_in, c_in, sum_o, c_out);
parameter SIZE = 4;
input [SIZE -1 : 0] a_in;
input [SIZE -1 : 0] b_in;
input c_in;
output [SIZE -1:0] sum_o;
output c_out;
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 24
wire g0,p0,g1,p1,g2,p2,g3,p3,g4,p4,x0,x1,x2,x3,x4,x5,x6,x7,x8,x9;
wire c1,c2,c3;
and a1(g0,a_in[0],b_in[0]);
xor xr1(p0,a_in[0],b_in[0]);
and a2(g1,a_in[1],b_in[1]);
xor xr2(p1,a_in[1],b_in[1]);
and a3(g2,a_in[2],b_in[2]);
xor xr3(p2,a_in[2],b_in[2]);
and a4(g3,a_in[3],b_in[3]);
xor xr4(p3,a_in[3],b_in[3]);
//~~ For C1 ~~
and a6(x0,p0,c_in);
or o1(c1,g0,x0);
//~~ For C2 ~~
and a7(x1,c_in,p1,p0);
and a8(x2,p1,g0);
or o2(c2,g1,x2,x1);
//~~ For C3 ~~
and a9(x3,c_in,p2,p1,p0);
and a10(x4,p2,p1,g0);
and a11(x5,p2,g1);
or o3(c3,g2,x5,x4,x3);
//~~ For C4 ~~
and a12(x6,c_in,p3,p2,p1,p0);
and a13(x7,p3,p2,p1,g0);
and a14(x8,p3,p2,g1);
and a15(x9,p3,g2);
or (c_out,g3,x9,x8,x7,x6);
//~~ output logic for CLA adder ~~
xor xr6(sum_o[0],c_in,p0);
xor xr7(sum_o[1],c1,p1);
xor xr8(sum_o[2],c2,p2);
xor xr9(sum_o[3],c3,p3);
endmodule
//PARALLEL ADDER TESTBENCH
module adder_4_bit_tb;
reg [3:0] x ;
reg [3:0] y ;
reg cin;
wire [3:0] z;
wire cout;
wire [4:0] expected_result;
wire [4:0] actual_result;
cla_adder a0(.a_in(x),.b_in(y),.c_in(cin),.sum_o(z),.c_out(cout));
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 25
initial
begin
x = 0; y = 0; cin = 0;
#10 x = 4'b0101; y = 4'b0001; cin = 1'b0;
#10 x = 4'b0101; y = 4'b1110; cin = 1'b1;
#10 x = 4'b1111; y = 4'b1111; cin = 1'b1;
#10 x = 0; y = 0; cin = 0;
#10 $finish;
end
assign expected_result = x+y+cin;
assign actual_result = {cout,z};
initial
begin
if(actual_result!==expected_result)
$monitor ($time , " x= %d ,y =%d cin =%b ,expected_result=%d actual_result =%d ,the expected
sum is not correct" , x ,y ,cin ,expected_result,actual_result);
else
$monitor ($time , " x= %d ,y =%d cin =%b expected_result=%d actual_result =%d , the expected sum
is correct" , x ,y ,cin,expected_result,actual_result );
end
endmodule
//4 BIT SYNCHRONOUS UP DOWN COUNTER
module sync_counter (clock,reset,up,down,count);
input clock;
input reset;
input up;
input down;
output [3:0] count;
reg [3:0] count;
always@(posedge clock)
begin
if (reset)
count <= 4'b0;
else if (up && ~down)
count <= count + 1'b1;
else if (down && ~up)
count <= count - 1'b1;
else
count <= count;
end
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 26
//4 BIT SYNCHRONOUS UP DOWN COUNTER TESTBENCH
module tb_sync_counter;
reg clk ;
reg rst ;
reg Up ;
reg Down;
wire [3:0] Count;
sync_counter S1 (.clock(clk),.reset(rst),.up(Up),.down (Down ),.count(Count));
initial
begin
clk = 1'b0;
forever
begin
#5; clk = ~clk;
end
end
task Reset;
begin
rst = 1'b1;
$display($time, "Reset is Asserted");
#10;
rst = 1'b0;Up=1'b1;
$display($time, "Reset is DE-Asserted");
end
endtask
initial
begin
Reset;
repeat(5)
begin
#10 Up = 1'b1;
Down = 1'b0;
end
repeat(10)
begin
#10 Up = 1'b0;
Down = 1'b1;
end
$finish;
end
always@(posedge clk)
$display ($time ," || CLOCK = %b || RESET = %b || UP = %b || DOWN = %b || COUNT =
%b",clk,rst,Up,Down,Count);
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 27
//4 BIT SYNCHRONOUS UP DOWN COUNTER GATELEVEL TESTBENCH
module tb_sync_counter;
reg clk ;
reg rst ;
reg Up ;
reg Down;
wire [3:0] Count;
sync_counter S1 (.clock(clk),.reset(rst),.up(Up),.down (Down ),.count(Count));
initial
begin
clk = 1'b0;
forever
begin
#5; clk = ~clk;
end
end
task Reset;
begin
rst = 1'b1;
$display($time, "Reset is Asserted");
#10;
rst = 1'b0;Up=1'b1;
$display($time, "Reset is DE-Asserted");
end
endtask
initial
begin
Reset;
repeat(5)
begin
#10 Up = 1'b1;
Down = 1'b0;
end
repeat(10)
begin
#10 Up = 1'b0;
Down = 1'b1;
end
$finish;
end
always@(posedge clk)
$display ($time ," || CLOCK = %b || RESET = %b || UP = %b || DOWN = %b || COUNT = %b",
clk,rst,Up,Down,Count);
initial
$sdf_annotate("sync_counter.sdf",tb_sync_counter.S1,, ,"Maximum");
endmodule
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 28
//4 BIT ASYNCHRONOUS UP DOWN COUNTER
module Async_counter (Clock,Reset,count);
input Clock;
input Reset;
output [3:0] count;
tff T1 (.clock(Clock),.reset(Reset),.T(1'b1),.q(count[0]));
tff T2 (.clock(!count[0]),.reset(Reset),.T(1'b1),.q(count[1]));
tff T3 (.clock(!count[1]),.reset(Reset),.T(1'b1),.q(count[2]));
tff T4 (.clock(!count[2]),.reset(Reset),.T(1'b1),.q(count[3]));
endmodule
//T FLIP FLOP SYNCHRONOUS RESET
module tff (clock,reset,T,q);
input clock;
input reset;
input T;
output q;
reg q;
always@(posedge clock or posedge reset)
begin
if (reset)
q <= 1'b0;
else if (T)
q <= ~q;
else
q <= q;
end
endmodule
//4 BIT ASYNCHRONOUS UP DOWN COUNTER TESTBENCH
module tb_Async_counter;
reg clk ;
reg rst ;
wire [3:0] Count;
Async_counter async_counter (.Clock(clk ),.Reset(rst ),.count(Count));
initial
begin
clk = 1'b0;
forever
begin
#5;clk = ~clk;
end
end
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 29
task Reset;
begin
rst = 1'b1;
$display($time, "Reset is Asserted");
#10;
rst = 1'b0;
$display($time, "Reset is DE-Asserted");
end
endtask
initial
begin
Reset;
#50;
Reset;
#150
$finish;
end
always@(posedge clk)
$display ($time ," || CLOCK = %b || RESET = %b || COUNT = %b",clk,rst,Count);
endmodule
//4 BIT SYNCHRONOUS UP DOWN COUNTER GATELEVEL TESTBENCH
module tb_Async_counter;
reg clk ;
reg rst ;
wire [3:0] Count;
Async_counter async_counter (.Clock(clk ),.Reset(rst ),.count(Count));
initial
begin
clk = 1'b0;
forever
begin
#5;clk = ~clk;
end
end
task Reset;
begin
rst = 1'b1;
$display($time, "Reset is Asserted");
#10;
rst = 1'b0;
$display($time, "Reset is DE-Asserted");
end
endtask
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 30
initial
begin
Reset;
#50;
Reset;
#150
$finish;
end
always@(posedge clk)
$display ($time ," || CLOCK = %b || RESET = %b || COUNT = %b",clk,rst,Count);
initial
$sdf_annotate("Async_counter.sdf",tb_Async_counter.async_counter,, ,"Maximum");
endmodule
//SUCCESSIVE APPROXIMATION REGISTER
module sar(clock_i,reset_i,analog_gt_digital,digital_out);
input clock_i;
input reset_i;
input analog_gt_digital;
output [3:0] digital_out;
reg [3:0] digital_out;
always @(posedge clock_i)
begin
if(reset_i)
digital_out <= 4'b0;
else
begin
if (analog_gt_digital)
digital_out <= digital_out+1;
else
digital_out <= digital_out-1;
end
end
endmodule
//SUCCESSIVE APPROXIMATION REGISTER TESTBENCH
module sar_test;
reg clock_i;
reg reset_i;
reg analog_gt_digital;
wire [3:0] digital_out;
sar sar(.reset_i(reset_i),.clock_i(clock_i),.analog_gt_digital(analog_gt_digital),.digital_out(digital_out));
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 31
initial
begin
clock_i =1'b0 ; reset_i =1'b1;
end
always
#5 clock_i = !clock_i ;
initial
begin
#40 reset_i =1'b0 ;analog_gt_digital=1'b1;
#40 reset_i =1'b0 ;analog_gt_digital=1'b0;
#40 reset_i =1'b0 ;analog_gt_digital=1'b1;
#80 reset_i =1'b0 ;analog_gt_digital=1'b0;
end
initial
begin
$monitor($time ," \t clock_i =%b reset_i= %b analog_gt_digital=%b digital_out=%b
",clock_i,reset_i,analog_gt_digital,digital_out);
#200 $finish;
end
endmodule
//SUCCESSIVE APPROXIMATION REGISTER GATELEVEL TESTBENCH
module sar_test;
reg clock_i;
reg reset_i;
reg analog_gt_digital;
wire [3:0] digital_out;
sar sar(.reset_i(reset_i),.clock_i(clock_i),.analog_gt_digital(analog_gt_digital),.digital_out(digital_out));
initial
begin
clock_i =1'b0 ; reset_i =1'b1;
end
always
#5 clock_i = !clock_i ;
initial
begin
#40 reset_i =1'b0 ;analog_gt_digital=1'b1;
#40 reset_i =1'b0 ;analog_gt_digital=1'b0;
#40 reset_i =1'b0 ;analog_gt_digital=1'b1;
#80 reset_i =1'b0 ;analog_gt_digital=1'b0;
end
Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab CEC-2011
VK Mentor Graphics 32
initial
begin
$monitor($time ," \t clock_i =%b reset_i= %b analog_gt_digital=%b digital_out=%b ",
clock_i,reset_i,analog_gt_digital,digital_out);
#200 $finish;
end
initial
$sdf_annotate("sar.sdf",sar_test.sar,, ,"Maximum");
endmodule
![Frontend Electronics in SOI at FERMILAB MAMBO III · [Kerry Bernstein, SOI Circuit Design Considerations, EECS VLSI Seminar Series, University of Michigan, 1 April, 2002] Bipolar](https://static.documents.pub/doc/80x56/5e4afee93496154c4941c14f/frontend-electronics-in-soi-at-fermilab-mambo-iii-kerry-bernstein-soi-circuit.jpg)
