90nm technology

7/29/2019 90nm technology

http://slidepdf.com/reader/full/90nm-technology 1/44

&KDOOHQJHVRIQP3K\VLFDOGHVLJQ

-DFTXHV2OLYLHU3LHGQRLU &DGHQFH'HVLJQ6\VWHPV

6RSKLD$QWLSROLV 2FW



Session Title p 2

:KDWGR\RXJHWIURPWKHWXWRULDO

,QWURGXFWLRQWRQPHIIHFW&KDQJLQJQDWXUHRIGHOD\VLJQDO

LQWHJULW\

5HFDSRQEDVLFQRWLRQV'HOD\FDOFXODWLRQ3DUDVLWLFSUHGLFWLRQ

)ORRUSODQQLQJ3K\VLFDO6\QWKHVLV

/LPLWDWLRQRIFXUUHQWIORZ3K\VLFDOV\QWKHVLVEDVHG

1HZIORZEDVHGRQVLOLFRQYLUWXDOSURWRW\SH

6LJQDO,QWHJULW\

<RXZLOOQRWEHFRPHDQH[SHUWLQQPSK\VLFDOGHVLJQEXW\RX

ZLOOKDYHWKHEDFNJURXQGWRVWDUWLQYHVWLJDWLQJWKLVQHZIURQWLHU



Session Title p 3

QDQRPHWHUGHVLJQIORZ

:LUH:LUH:LUHHYHU\ZKHUH

&KDQJLQJQDWXUHRI'HOD\– Cross coupling

– IR Drop

+LVWRU\RIIORZIURPQPWRQP

QPIORZ&RQWLQXRXVFRQYHUJHQFH



Session Title p 4

:LULQJ GRPLQDWHV QDQRPHWHU GHVLJQ

:LULQJGHOD\H[FHHGVJDWHGHOD\DWQPLQDOXPLQLXP SURFHVVDQGDWQPLQFRSSHUSURFHVV

)RFXVVKLIWHGIURPORJLFRSWLPLVDWLRQWRZLUHRSWLPLVDWLRQ



Session Title p 5

&KDQJLQJ QDWXUHRI GHOD\ ±

3K\VLFDO HIIHFWV LQWURGXFH VXEVWDQWLDO GHOD\6LJQDO

LQWHJULW\,5'URS6LPSOLILHG PRGHO VXFK DVOXPSHG FDSDFLWDQFHDUHQRW

HQRXJK

/XPSHG

FDSDFLWDQFH

LQSXW

LQSXW

LQSXW



Session Title p 6

&KDQJLQJ QDWXUHRI GHOD\ ±

$W QPDQG DERYH WKH SULPDU\ ZLUH FDSDFLWDQFHLV

GXHWRFRXSOLQJ WRHOHFWULFDO JURXQG DQG LV ODUJHO\

SURSRUWLRQDWH WRZLUH OHQJWK

:LUH OHQJWK LV SUHGLFWHG EDVHG RQQHWOLVW LQIRUPDWLRQ

ZLUH ORDG PRGHORURQSODFHPHQWVWHLQHU WUHHJOREDO

URXWLQJ HVWLPDWHV

6XEVWUDWH

)ULQJH



Session Title p 7

5HPLQGHU'HILQLWLRQ:LUH /RDG 0RGHO

*RDO(VWLPDWH FDSDFLWDQFHEHIRUH SODFHPHQWLV NQRZQ

%DVHG RQVWDWLVWLFDO GDWDFDSDFLWDQFHGHSHQGV RQQXPEHU RI

LQVWDQFHVLQWKH QHWOLVW DQG QHWIDQRXW6WRUHG LQORRNXS WDEOHVLQWKH OLEUDU\ RUGHULYHG IURP

SUHYLRXV LWHUDWLRQV

&DSDFLWDQFHWRRELJ

3UHGLFWHGFDSDFLWDQFH

)DQRXW

1HWOLVW.

6ORZ)DVW

FDSDFLWDQFHWRRVPDOO Capacitance pF

nets



Session Title p 8

5HFDSGHILQLWLRQ5RXWLQJHVWLPDWHV

Steiner tree:minimum length tree

Global routing: Set of steiner treesminimizing total wire length andcongestion.

Global routing computes the topology of each net on a coarse grid(routing bin). The detailed routing (track assignment) is not know.

Primary goal is to compute wire length..

ÎGlobal routing can predict wire length but cannot predict coupling effect.



Session Title p 9

&KDQJLQJ QDWXUHRI GHOD\&URVV

&RXSOLQJ

$VJHRPHWULHVGHFUHDVHWKHSULPDU\FDSDFLWLYHFRXSOLQJRQDJLYHQZLUH

PRYHVWRLWVQHLJKERULQJZLUHV

&DSDFLWDQFHGHSHQGVRQWKHORFDOZLUHJHRPHWU\DQGLQPDQ\FDVHVWRWKHDFWXDOVLJQDOV

Variation is +/- 30% for 1MMwire and +80%/-60% for 3MMwires.



Session Title p 10

&URVVFRXSOLQJFRQFOXVLRQ

3ODFHPHQWEDVHGHVWLPDWHVVWHLQHU WUHHVJOREDOURXWLQJDUHQRW

DFFXUDWHHQRXJK'HWDLOHGURXWLQJLVUHTXLUHGWRSUHGLFW

SHUIRUPDQFHV

,VVXHV

– How can we get early access to detail routing.

– How can we iterate fast enough when detailed routing is required.



Session Title p 11

&KDQJLQJQDWXUHRIGHOD\,5'URS

5HVLVWDQFHLQWKHSRZHUDQGJURXQGZLUHQHWZRUNV

FUHDWH,5'URS

9ROWDJHVGHSHQGRQFXUUHQWV

RIRWKHUFHOOV

3DG3RZHUVXSSO\

QHWZRUNFRQVLVWV

RIZLUHVRIYDU\LQJ

VL]HVWKH\PXVWEHELJ

HQRXJKEXWWRRELJZDVWHVDUHD

&XUUHQWVGHSHQGRQGULYHUW\SH

ORDGVDQGKRZRIWHQFHOOLV

VZLWFKHG

$OORZDEOH

YROWDJH

GURSDWSLQ



Session Title p 12

&KDQJLQJQDWXUHRIGHOD\,5'URSDQG

GHOD\

$Q,5'URSIURP9WR9LVFDSDEOHRISURGXFLQJGHOD\

YDULDWLRQRIRUPRUH

2QHVWXG\RIGHVLJQVDWQPVKRZHGWKDWRIGHVLJQV

IDLOHGRQILUVWVLOLFRQGXHWRH[FHVVLYH,5'URSDORQH

&RQFOXVLRQQPIORZVKRXOGLQFOXGHDWRROWRFRPSXWH,5

'URSDQGDGHOD\FDOFXODWRUWDNLQJLQWRDFFRXQWWKH,5'URS



Session Title p 13

5HFDSGHOD\FDOFXODWLRQ

7LPLQJYHULILFDWLRQLVVSOLWLQWRWZRFRPSRQHQWV

–

Delay calculator: computes delay between gate output and gateinputs based on extracted RCs.

– Static Timing Analysis engine: propagate the delay in the cells andin the interconnect to check for timing violations.

QP'&VXFKDV6LJQDO6WRUPWDNHVLQWRDFFRXQW

– IR Drop

– Cross talk impact on delay.

67$WRROVVXFKDV3ULPHWLPH%XLOGJDWHV UHDGLQDQ6')ILOHWKHGHOD\FRPSXWHGE\WKH'HOD\FDOFXODWRU



Session Title p 14

'HOD\&DOFXODWRUIORZ



QDQRPHWHUGHVLJQIORZ



Session Title p 16

:KDWKDYHZHVHHQVRIDU

'HOD\LVGRPLQDWHGE\ZLUHV

'HOD\LVGHSHQGHQWRQ6,LVVXHVFURVVFRXSOLQJDQG,5'URS

Î1H[WIRLOVZLOOLQYHVWLJDWHWKHLPSDFWRIWKHDERYHRQWKH

SK\VLFDOGHVLJQIORZDQGWKHSK\VLFDOLPSOHPHQWDWLRQWRROV



Session Title p 17

1DQRPHWHUGHVLJQIORZ

'RPLQDQFHRIZLUHGHOD\VKDVVLJQLILFDQWO\PRGLILHGWKHIORZLQWKHODVW\HDUV

QPDQGDERYH

– Gates dominate delay. Wire delay can be estimated using wire load model. Synthesisand place and route are two different steps.

QP– Wire delay starts dominating overall delay. Better accuracy is needed in wire delay

estimation:– Placement and Synthesis merge (Physical Compiler, PKS) at the block level

– Floorplanner to estimate top level wires.

QPDQGEHORZ– Wire delay dominates the design. Wire delay depends on cross couplingÎPerformance is unknown before routing.

– Introduction of tools and flow that generate wires as soon as possible (“time to wire”).



Session Title p 18

QP6LPSOLILHG'(6,*1)/2:

57/

/D\RXW

1HWOLVW

6\QWKHVLV

3ODFHDQG5RXWH

'5&

Equivalencechecking

Simulation

Simulation

Extraction

R.C

Timing Verification

Wire Load Models







Session Title p 21

1DQRPHWHUGHVLJQLWHUDWLRQV

³WLPHWRZLUH´

Design methodology must minimize time to wire and full chip iteration time: Continuousconvergence methodology.

In nanometer designphysical synthesis isused only on thoseblocks that full chipdetailed routingidentifies as notmeeting timing.



Session Title p 22

&RQWLQXRXVFRQYHUJHQFH

&RQWLQXRXVFRQYHUJHQFHEHJLQVZLWKDQLQLWLDOIXOOFKLS

GHVLJQUHSUHVHQWDWLRQZLWKZLUHVFDOOHGVLOLFRQYLUWXDO

SURWRW\SH693

693WUHDWVDOODVSHFWVRIWKHGHVLJQORJLFWLPLQJ6,,5

'URS(OHFWURPLJUDWLRQ,2DQGPDQXIDFWXUDELOLW\

693VKRXOGKDYHDRQHGD\WXUQDURXQGWRDOORZGHVLJQWHDPVWRLGHQWLI\DQGSULRULWL]HSHUIRUPDQFHDQG

PDQXIDFWXULQJLVVXHV

693LVIROORZHGE\DILQDOFKLSLPSOHPHQWDWLRQZKHQDOO

GHVLJQSDUDPHWHUVDQGDUFKLWHFWXUHVKDYHEHHQILQDOL]HGDQGYDOLGDWHG



Session Title p 23

&RQWLQXRXVFRQYHUJHQFH



6LJQDO,QWHJULW\





Session Title p 26

3HUIRUPDQFH5HOLDELOLW\DQG0DQXIDFWXUDELOLW\

LQ6LJQDOLQWHJULW\

Performance

– Crosstalk

– IR Drop

Reliability

– Hot Electron

– Electromigration

– Wire Self Heat

Manufacturability

– Process Antenna Effect (PAE)

– Metal Density

2YHUYLHZ







Session Title p 29

&URVVWDON

Aggressor & Victim Relationship

6SDWLDO– Proximity and Width of conductors

(Capacitance and resistance)

– Coupling location distance from drivers

Failures Caused

)XQFWLRQDO/RJLFOHYHOFKDQJH

7LPLQJ6HWXS+ROG

Simple Definition:

&RXSOLQJRIHOHFWULFDQGPDJQHWLF

ILHOGVEHWZHHQFRQGXFWRUV

*HQHUDO&RQFHSWV3HUIRUPDQFH

9LFWLP

9LFWLP

$JJUHVVRUV &RXSOLQJ

QV QVQV QV

9

9YLFWLP

QRFRXSOLQJDJJUHVVRU

YLFWLPFRXSOLQJ;WDON

'HOD\

•Temporal

–Signal slews and time of switch



Session Title p 30

$QDO\VLVDQG$YRLGDQFH

Analysis Requirements– Driver Strength

–

Routing topology and RC’s– Timing Analysis to identify slew relationship and edge alignment

– Victims’ net receiver noise margin

Avoidance– Separate victim from Aggressor

– Shield Aggressor

– Reduce victim slew, Increase aggressor slew

– Change Temporal relationship





Session Title p 32

,5'URS

Failures Caused

)XQFWLRQDO/RJLFOHYHOFKDQJH GXHWRQRLVHPDUJLQUHGXFWLRQ

7LPLQJ6HWXSDQG+ROGGXHWRFLUFXLWVORZGRZQRUVSHHGXS

– IR drop in power grid will create variations in delay across the chip

– Performance of a chip roughly varies by 7-9% when vdd is varied by 10%

– Affect clock skew in the clock network

Simple Definition:

5HVLVWDQFHLQSRZHUJULGFDXVHVD

UHGXFHGVXSSO\YROWDJHDWWKHGHOLYHU\

SRLQW

'9,59GG 5

9VV

5

, 9GG '9

&/

'HOD\9V6XSSO\9ROWDJH

QV QVQV

9

9

97

6XSSO\9ROWDJH9DULDWLRQ

'HOD\9DULDWLRQ











Session Title p 37


Analysis Requirements

– Characterization of cells’ current consumption

– Power supply network RC’s extraction

– Wire DC and peak current densities based on the current consumption of each

cell and the resistance of the power grid.

– DC current densities are compared to the process limits.

Avoidance

– General estimation of power network using DC or average DC current drawn

per cell and row utilization.

– Network resistance reduction (adding via cuts and increasing or tapering wire

width).









Session Title p 41


Analysis Requirements

– Metal Area to Gate Area ratio

– Metal Side Area to Gate Area ratio– Layer Only Vs Cumulative

Avoidance

– Layer hoping

– Diode insertion during routing

– Diode embedded in cell

– Buffer/Repeater insertion right on the pin inside the block

–

Force pin assignment to last metal on critical nets.

$QWHQQD$SSURDFK

5DWLRQDOHDQG,PSDFW







Date post:	04-Apr-2018
Category:	Documents
Upload:	pdnoob
View:	219 times
Download:	0 times

90nm technology

Documents