A 2.4-GHz LC-Tank VCO withMinimum Supply Pushing Regulation Technique
Xuejin Wang' and Bertan Bakkaloglu2'Cadence Design Systems, Inc., Tempe, AZ 85282, USA
2Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287, USA
Abstract- Design of low drop-out (LDO) supply regulated Vin2.4GHz low phase noise LC-tank voltage controlled oscillator(VCO) is presented. Low-frequency supply noise sensitivity of Referencethe VCO phase noise is derived, and output noise and power Voltage Err - Passsupply rejection (PSR) profile of the LDO is optimized for Amp Elementminimum supply pushing. The LDO PSR and output noise is + Vregoptimized by shaping the LDO AC response and tuning the
co
equivalent-series resistance (ESR) of the bypass capacitor, vcowhile achieving maximum LDO current efficiency. To verify Feedback outputthe results, two 2.4GHz LC-tank VCOs, with a PMOS and an ResrNMOS switching pair respectively with associated PMOSsupply regulators are designed and fabricated in a 0.18pm, 7-layer metal CMOS process. The implemented VCOs achieve Fig. 1. Block diagram of the proposed supply regulated VCOless than 95dBc/Hz phase noise at 100kHz offset with a design.current consumption of 2.2mA. By utilizing the proposedregulator AC loop shaping, the VCO phase noise sensitivity to In this paper nonlinear tank capacitance and devicesupply noise is improved by 30dB for offset frequency up to conductance based VCO supply pushing characteristics are10MHz with no phase noise peaking.1OMHz wihnophae noise eaking.analyzed and an optimum co-design of LDO noise andIndex Terms - DC-DC power conversion, low-dropout alyed and anjoptimu codsg of LD noise and
regulators, voltage controlled oscillators, phase noise, power power supply rejection (PSR) profile iS presented. Thesupply rejection. proposed LDO uses a PMOS pass element and achieves
30nV/\'Hz noise density at 10kHz and a unity gainI. INTRODUCTION bandwidth of 166kHz. The proposed architecture can be
VCO phase noise performance impacts several RF optimized for both PMOS and NMOS switching pairsystem specifications such as error-vector-magnitude VCOs. With the proposed co-design scheme, the VCO
(EVM), SNR and SNR under blocking conditions. There supply pushing is shown to be reduced from 66.9MHz/V
are two major sources for VCO phase noise: VCO circuit to 1.5MHz/V. VCO supply noise sensitivity is alsodevice noise and ambient noise such as supply, ground and reduced by 30dB for offset frequencies up to 10MHz
compared to an unregulated LDO.substrate noise. The supply noise is becoming a major gThe paper iS organized as follows. Section II outlinescontributor in deep-submicron low noise VCOs due to the Thesources ofgsupply s si inlCStan VO and
reduced power supply voltage, reduced clock swings,higher order of digital integration and increased number of provide trade-offs between device induced phase noise and
circuits on the same IC. It has been shown that positive supply sensitivity. Section III provides details of an
optimum AC frequency response LDO design for VCOsupply noise has the highest impact on VCO phase noise in.... .~~~~~~~ aplications. Section IV summarizes the experimentalterm of deterministic noise [1]. To reduce the effect of . .supply ripple, low dropout linear regulators (LDOs) [2] [3] results for the proposed minimum supply pushing VCOs in
' . . ~~~~~~~~a0.1 8pim CMOS process. Finally the conclusions areare usually preferred for low noise voltage regulation. a in Secio V.A block level diagram of a supply regulated VCO is
shown in Fig. 1. The LDO circuit includes a voltage 1. SUPPLY SENSITIVITY OF LC-TANK VCOSreference, an error amplifier, a pass element, and afeedback network. The pass element can be implemented A. Supply Sensitivity Analysiswith bipolar or MOS transistors. The MOS transistor LOW frequency power supply noise up-conversion toimplementation gives lower quiescent current and it is VCO phase noise is directly related to VCO power supplymore compatible with state of the art CMOS processes. frequency pushing factor.
M3 M2 LO LI G =6(Vi -v t) = ocoxLc (VI Vt ) (2)Vtune L
MO Ml Vdd The resulting half circuit of the oscillator with the
+Ibias H LI ;;lbias 4 switching device conductance is shown in Fig. 3. Weco CO C1 , < v ;;assume the inductor has a parasitic resistance of R, whichCO- MOIm
6 |>1 , 141 | MOMI yields the inductor quality factor of -LIR.<Vtune 2 < J For a fixed conductance G, the oscillation frequency ofLO LI M3 M2 the circuit is given by
0) 1 RC-GL 202 = (3)
Fig. 2. Designed PMOS and NMOS switching pair cross- LC 2LC)coupled LC VCO topologies. When Vdd varies, it affects the switch conductance G
In this design two typical cross-coupled LC tank VCOs and changes the oscillation frequency. The relationshipthat use PMOS and NMOS switching-pair transistors between ,6, Vdd and the oscillation frequency for a typicalrespectively are implemented, as shown in Fig. 2. VCO is shown in Fig. 3.Frequency pushing factor k is defined by the oscillation Vddfrequency change Ac in response to a supply voltagechange of AV as k = Aow / AV [rads/V]. The supply noise c
induced phase noise in dBc/Hz at frequency offset f, can o40
be expressed as Z
L(fn) = 20logk| +2OlogV-20log(22rf) 6.02, (1), V
where V is the supply noise amplitude at frequency f. As G.0 V 8Vdd
shown in equation (1) the low frequency supply noiseinduced phase noise magnitude increases with frequency Fig. 3. Linearized half circuit of the VCO for thepushing factor k, and decreases with the supply ripple switching device in the linear region and oscillationfrequencyfn. frequency dependency on circuit parameters
The VCO phase noise conversion and frequencypushing is shown to be induced by the AM-PM conversion B. Device Noise versus Supply Sensitivity Trade-Offsdue to the nonlinear capacitance of the varactors [4] and When the tail current device M2 operates in saturationMOS devices [5]. In order to minimize supply pushing region, the VCO operates in current limited region and theeffects of the VCOs, cancellation circuit for the nonlinear tank amplitude strongly depends on the bias current.tank capacitors has been proposed [6]. Therefore the bias current noise becomes a major
In addition to the AM-PM conversion of nonlinear contributor to the VCO phase noise. The bias current noisecapacitances, the NMOS VCO also suffers from the contribution can be effectively suppressed by making thefrequency pushing due to the change of the varactor tail transistor spend most (or even all) of oscillation periodquiescent point. The DC voltage across the varactors for in triode region [7]. In this region, the tank amplitude isthe NMOS VCO is Vdd - Vtune which follows the change of limited by the voltage supply. The main drawback of thisVdd. This has the same impact as the VCO frequency operation is that the VCO phase noise becomes moretuning by the tuning voltage Vtune. The pushing factor due sensitive to the power supply noise, which needs to beto this effect has the opposite sign from the nonlinear minimized by supply regulation.capacitance AM-PM conversion. As seen above, there is a distinct trade-off between
In this paper another critical frequency pushing power supply induced phase noise and device inducedcontribution due to voltage dependent nonlinear operation phase noise, including tail current noise contribution. Byof the switching devices is shown. Throughout most of the designing the output referred noise and PSR of the LDO inoscillation period, one of the switching devices is in cut- conjunction with the VCO supply sensitivityoff region and the complementary pair is in triode region. characteristics, the VCO could be optimized for bothThe current through the triode region transistor is reduced device inducedAphase noise, as well as minimizedcontrolled by its gate voltage. The effect ofthe transistor is power supply induced phase noise. The details of thislike a nonlinear variable resistance in parallel with the LC optimization will be discussed in Section III.
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III. LDO DESIGN FOR Low NOISE VCOS VCO+LDO VCO+LDO VCO+LDOSensitivisitivity Sensitivity
The circuit block diagram of the proposed PMOS passdevice LDO is shown in Fig. 4. The error amplifier of theLDO is implemented with a folded cascode amplifier. The LDO PSR LDO PSR LDO PSR
feedback network consists of resistors R1 and R2. The Frequency Frequency Frequencybypass capacitor Co also provides frequency compensation (a) (b) (c)at the output node and helps with high frequency PSR. The Fig. 5. Typical LDO PSR and VCO supply sensitivity forresistor Res, is the equivalent-series resistance (ESR) of Co. different Resr values (a) high Resr (b) moderate Resr (c) low ResrCritical specifications of an LDO from an RF VCO supply I. EXPERIMENTAL RESULTSregulation point are line regulation, load regulation,temperature stability, settling time, output capacitor, ESR In order to verify the optimum LDO PSR and noiserange, quiescent current, and input/output voltage range. shaping, two regulated VCOs as shown in Fig. 2 are
Vin implemented in a 7-layer metal, 0.18ptm CMOS processalong with the associated LDOs. The die micrograph is
HHL1 Vg gmp showninFig.6.Vout
| 9 iR2 co NMOS VCO PMO
~VrefVfRi Resr d
vb1 -i
Fig. 6. Die micrograph of the VCOs along with regulators.
Fig. 4. The LDO with PMOS regulation device. The VCOs are designed for a nominal oscillationfrequency of 2.4GHz with a power supply of 1.65V and a
In order to minimize VCO power supply induced noise, current consumption of 2.2mA. The VCOs are optimizedfrequency characteristics of LDO PSR and output noise to achieve low phase noise by sizing the switching andneeds to be optimized. The LDO PSR frequency response bias devices as well as the varactors. The tail currentis affected by the error amplifier, pass device, and output device is biased at slight triode region to suppress thecapacitor. A high gain-bandwidth (GBW) error amplifier current noise from the bias device, utilizing the regulatedimproves the low and moderate frequency PSR, with the supply voltage conditions as much as possible.cost of high current consumption and reduced efficiency. The LDO is designed to have an input voltage range ofThe trade-off between high frequency and moderate 2V to 2.5V and an output voltage of 1.65V. It can operatefrequency PSR can be made by tuning the series resistance with an internal MIM bypass capacitor or an externalResr of the bypass capacitor with minimum efficiency ceramic type capacitor with an extra series resistance fordegradation, as shown in Fig. 5: characterization purposes. The LDO can support a range* When Res, is very low, the VCO power supply sensitivity of capacitors between 500pF to 5uF. For the followingaround the unity gain frequency will be deteriorated by experiments, a maximally flat PSR and noise response isthe LDO's PSR frequency peaking. designed with an Res, value between 1Q and 5Q. The LDO
* When Res, is high, the VCO power supply sensitivity is is designed to have an AC response similar to Fig. 5(b). Atimproved at moderate frequency but worsens at higher VCO supply current levels, the LDO achieves 76%frequencies. efficiency.
* With moderate Resr, trade-offs can be made for given The designed LDO has an output noise density to beVCO power supply sensitivity frequency specification. less than 30nVUHz for frequencies above 10kHz. ToThe thermal and flicker noise of the LDO also evaluate the contribution from LDO internal noise, the
contributes to the VCO phase noise. For a given VCO VCO phase noise is measured at two conditions: a)phase noise supply sensitivity profile and phase noise powered by a low-noise 1.65V battery, b) powered by thespecifications, the requirement of LDO output noise can LDO with a 2V battery input and 1.65V output voltage. Asbe derived. The LDO output noise spectrum and PSR is shown in Fig. 7 the VCO spot phase noise for these twoaffected by theESRwith similar trends. cases is within 0.2dB error margin, indicating that the
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phase noise contribution from the LDO noise is much less [7] A. Hajimiri, T. H. Lee, "Design issues in CMOS differentialthan the VCO internal noise. LC oscillators," IEEE Journal of Solid-State Circuits, vol.To capture the impact of global power supply ripple on 34, no. 5, pp. 717-724, May 1999.
VCO phase noise, a frequency-swept single-tone sine vco Phase Noisewave is applied to global power supply. The power of the -40
powered by 1 .65V batterysupply ripple is first measured in dBm referred to 50Q powered by LDO with 2V batteryimpedance. The FM spur power at that frequency is then -60measured in dBc with respect to carrier. The phase noisesensitivity to power supply is defined as the ratio of thespur power and the input sine wave power, which isplotted in Fig. 8. Positive supply sensitivity of the phase z
noise for the PMOS and NMOS VCOs is designed to besimilar for characterization purposes. The improved phasenoise sensitivity to power supply is plotted in Fig. 9. The -140 -LDO PSR is also potted in the same figure to show thejoint optimization. -1600k 0k 1M 1 )M
Frequency (Hz)
V. CONCLUSIONS Fig. 7. Phase noise of VCO powered by 1.65V battery orLDO with 2V battery.
Design of supply regulated LC tank VCOs withVCO Phase Noise Sensitivity to Power Supply Noiseminimum supply noise and ripple is presented. The aC -20 - X r r T X r X 7 X =1 1 * r 1 T r * * 1 * 1 *~~~~~~~~~~~~ PMOSVCO
loop-shaping for the LDO for minimum peaking and 30 + NMOS VCOoutput noise is achieved by the output capacitor ESR and F PMOS VCO with LDO
-40 NMOS VCO with LDOerror amplifier response. By tuning the capacitor ESR inconjunction with the load current associated with the -50VCO, overall supply sensitivity can be reduced without X -60frequency peaking. Proposed LDO AC response along 7with VCO phase noise is verified with experimentalresults. @ X A4
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