Abstract Proceeding AVLSI 2018

8/19/2019 Abstract Proceeding AVLSI 2018

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Welcome to the AVW 2011

thWelcome to the 14 annualIEEJ International Analog VLSI Workshop, AVLSIWS 2011, at Bali,Indonesia.This workshop is sponsored by theResearch Committee on Electronic Circuits of the Institute of ElectricalEngineers of Japan (IEEJ), and it is being conducted in collaborationwith the IEEE Circuits and Systems Society Japan Chapter,BandungInstitute of Technology, and IEEE Indonesia Section.

This year, our technical program consists of 2 keynote speeches, 4invited talks, and 10 regular lecture sessions. Authors from around theworld will be attending the workshop, where they will present theirlatest research results. A total of 47 papers fromeightcountries weresubmitted for the regular track. This corresponds to an acceptance rateof 77%.The program has been carefully organized to uphold thetraditional on-track policy.

The AVLSI is an opportunity for our community to congregatein ordershare our experiences, exchange ideas and inspirations, discover

research breakthroughs, and establish connections.This workshop hasbeen organized to overcome difficulties related to analog VLSI amongthe main engineering players from universities andindustries, involvedin teaching, research, and technical developments in this field.

We would like to extend our gratitude to all the authors who devotedconsiderable time and effortto the preparation of their submittedpapers. We also wish to thank the Technical Program Committee for AVLSIWS 2011 and the dedicated conference staff for their tireless

support.

Trio AdionoGeneral Chair2011 IEEJ International Analog VLSI Workshop

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November 2, 2011

9:00 - 9:15 Opening Ceremony

9:15 - 10:15 Keynote Speech 1: "Future Power Electronics Possibility for Sustainable Society"Dr. Hiromichi Ohashi

National Institute of Advanced Industrial Science and Technology, Japan

10:15 - 10:40 Coffee Break

10:40 - 12:00

Analog I

10015 An Almost 2VDD Rail-to-Rail Input and Output Operational Amplifier Using VDD CMOSFETs

Yasuaki Inoue, Zhangcai Huang,Changquan Jin, Zhao Chen

10027 An Improved Local-Feedback MOS Transconductor for LowFrequency Applications

Takeshi Ohbuchi, Fujihiko Matsumoto

10031 A Synthesis of Linear Transconductors Using MOSFETsOperating in Weak-Inversion Region Based on SINH Circuit

Fujihiko Matsumoto, Ryutaro Sugimoto,Takeshi Ohbuchi, Tomomi Abe

10042 A Constant-gm Rail-to-Rail Operational Amplifier with Low-gain Variation and It's Analysis

Nobuyuki Yokoyama, Cong-Kha Pham

12:00 - 13:30 Lunch

13:30 - 15:00

RF Circuit

Invited I High Performance SOI CMOS SPMT RF Switch for CellularTerminals

Tsuyoshi Sugiura, Kouki Tanji, NorihisaOtani, Eiichiro Otobe

10022 Power Consumption Improvement of Wideband CMOSDifferential LNA–Mixer with Two Noise Cancellation

Shintaro Tanaka, Akira Hyogo, KeitaroSekine

10023 An Inductorless Variable Gain Mixer with Variable Resistorfor 900-MHz and 2.4-GHz Application

Naoki Tsukahara, Akira Hyogo, KeitaroSekine

10025 A Cascode Class-E Power Amplifier with Improved PowerEfficiency by Adding a Parallel Capacitor

Dai Miyauchi, Akira Hyogo, KeitaroSekine


15:20 - 16:40

Converters I

10032 The Multiplier Less Two-path Cross-coupled D-S Modulator Takeshi Shima, Takumi Ikegami

10038 Continuous-time Delta-sigma Modulator Using Vector Filter inFeedback Path to Reduce Effect of Clock Jitter and Excess Loop Delay

Yuki Kimura, Akira Yasuda, MichitakaYoshino

10041 Complex Bandpass DS Modulator with Bandpass ErrorFeedback Structure

Shuhei Kato, Satoshi Saikatsu, AkiraYasuda, Michitaka Yoshino

10044 Two-Path Delay Line Based Quadrature Band-Pass Sigma-Delta Modulator

Nithin Kumar Y.B., Edoardo Bonizzoni, Amit Patra, Franco Maloberti

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November 3, 2011

9:00 - 10:10

Keynote Speech 2: "Real-Time WiMAX System on Chip Design, Impelementation and Field Test”Dr. Trio Adiono

Bandung Institute of Technology


10:30 - 12:00

Sensor & Signal Processing

Invited II Power Management of Autonomous Wireless Sensor Node Prof. Toshihiko Hamasaki

10019 Low-power Wake-up Reciever With Subthreshold CMOSCircuits for Wireless Sensor Networks

Kazuhiro Takahagi, Hiromichi Matsushita, Tomoki Iida,Masayuki Ikebe, Yoshihito Amemiya, Eiichi Sano

10020 A CMOS Optical-Flow Image Sensor Based on Speed- Adaptive Multiple-Frame Single-Pixel-Shift Block Matching

Takemasa Komori and Tadashi Shibata

10036 An Analog K-means Learning Processor Employing Fully-Parallel Self-Converging Circuitry

Renyuan Zhang, Tadashi Shibata

12:00 - 13:40 Lunch

13:40 - 15:00

Power Supply & Management

10003 A Novel Low Quiescent Current PFM Method withIndependent Threshold for Buck Switching Converters

Bin Shao

10004 Flexible UFR Island to Prevent Black Out Rukmito Ari Ardianto, Djuma'iyah

10026 A Small, Low Power Boost Regulator Optimized for EnergyHarvesting Applications

Zachary Nosker, Yasunori Kobori, Haruo Kobayashi, KiichiNiitsu, Nobukazu Takai, Takeshi Oomori, TakahiroOdaguchi, Isao Nakanishi, Kenji Nemoto, Junichi Matsuda

10030 Digital Simulation of the Generalized Unified Power FlowController System with 60-pulse GTO-based VSC

Rakhmad Syafutra Lubis


15:20 - 16:50

Signal Processing & Communication I

Invited III TBD Prof. Siddik Yarman

10013 Optimum VLSI Architecture of High PerformanceSynchronizer for WiMAX OFDMA System

Nana Sutisna , Trio Adiono

10018 Architecture of High-Efficiency Digitally-Controlled Class-EPower Amplifier

Jiani Ye, Zachary Nosker, Kazuyuki Wakabayashi, TakuyaYagi, Nobukazu Takai, Kiichi Niitsu, Keisuke Kato, TakaoOotsuki, Haruo Kobayashi, Osamu Yamamoto, Isao Akiyama

10047 Design of Wide Gain Range CMOS VGA for WLAN Receiver Laksono Widyo Isworo, Cosy Muto,Hiroshi Ochi, Hiroshi Tanimoto

19:00 Gala Dinner & Award Ceremony

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November 4, 2011

09:00 - 10:50

Signal Processing & Communication II

Invited IV TBD Dr. Satoru Shingai

10028 Implementation of Low-Noise Switched-Capacitor Low-passFilters with Small Area

Nicodimus Retdian, Shigetaka Takagi

10037 Loop Design Optimization of 4th-Order Fractional-N PLLFrequency Synthesizers

Lee Jun Gyu, Shoichi Masui

10046 Active Inductor Design using Distortion Reduction Technique Takahide Sato, Toshihiro Ito

10024 A gain improved CMOS LNA using Negative Resistance ofan Active Inductor

Dai Ichihoshi, Akira Hyogo, KeitaroSekine


11:10 - 11:50

Digital Signal Processing

10017 Design and Implementation 2k/4k/8k FFT-IFFT Core usingBlock Floating Point for DVB-T and DVB-H

Ir. Amy Hamidah Salman, MSc, Andy’esFourman Duta Akbar Sudirdja, ST

10034 An Optimized 8-Level Turbo Decoder Algorithm and VLSI Architecture for LTE

Ardimas Andi Purwita, Trio Adiono

11:50 - 13:50 Lunch

13:50 - 15:10

Converters II

10040Robust Switched-Capacitor ADC Based on Beta-expansion

Tsubasa Maruyama, Hao San andMasao Hotta

10012 Non-Binary Pipelined ADC with b-Encoding Hao San, Tomonari Ka to, TsubasaMaruyama, Masao Hotta

10014 Substrate Noise Measurement and Analysis on theComponents of the Pipeline Analog to Digital Converter

Annisa Karima, Kazuyuki Wada

10029 Telescopic Op-Amp Design with CMFB for 1.5 bit/stagePipelined ADC

Mohd Hairi, Zulfiqar Ali Abdul Aziz


15:30 - 16:30

Analog II

10039Temperature Coefficient Improvement of PTAT VoltageGenerator Based on Temperature Dependence ofMOSFET Threshold Voltage

Junichi Fujitsuka, Kawori Sekine

10043 A Linearity Optimization Method for CMOS R-2R LadderNetwork

Yuta Kato, Cong-Kha Pham

10009 A Novel Bulk Input Four Quadrant Analog Multiplier inWeak Inversion

Antaryami Panigrahi, Prashanta KumarPaul

16:30 Closing Ceremony

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Map of AVW 2011Bali Room at Melia Hotel

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Contents

Invited Paper I :

Invited Paper II :

10003 :

10009 :

I High Performance SOI CMOS SPMT RF Switch for

Cellular TerminalsPower ManagementofAutonomous of WirelessSensor Node

A Novel Low Quiescent Current PFM Method with IndependentThreshold for Buck Switching Converters

A Novel Bulk-input Low Voltage and Low Power FourQuadrant Analog Multiplier in Weak Inversion

10012 : Non-Binary Pipeline ADC with b-Encoding10013 : Optimum VLSI architecture of high performance

Synchronizer for WiMAX OFDMA system10014 : Substrate Noise Measurement and Analysis on the

Components of the Pipeline Analog to Digital Converter10015 : An Almost 2VDD Rail-to-Rail Input and Output Operational

Amplifier Using VDD CMOSFETs10017 : Design and Implementation 2k/4k/8k FFT-IFFT Core using

Block Floating Point10018 : Architecture of High-Efficiency Digitally-Controlled Class-E

Power Amplifier10019 : Low-power Wake-up Receiver With Sub-threshold CMOS

Circuits for Wireless Sensor Networks10020 : A CMOS Optical-Flow Image Sensor Based on Speed-

Adaptive Multiple-Frame Single-Pixel-Shift Block Matching10022 : Power Consumption Improvement of Wideband CMOS

Differential LNA–Mixer with Two Noise Cancellation

10023 : An Inductorless Variable Gain Mixer with Variable Resistorfor 900-MHz and 2.4-GHz application

10024 : A gain improved CMOS LNA using negative resistance of anactive inductor

10025 : A Cascode Class-E Power Amplifier with Improved PowerEfficiency by Adding a Parallel Capacitor

10026 : A Small, Low Power Boost Regulator Optimized for Energy

Harvesting Applications10027 : An Improved Local-Feedback MOS Transconductor for LowFrequency Applications

10028 : Implementation of Low-Noise Switched-Capacitor Low-passFilters with Small Area

10029 : Telescopic Op-Amp Design with CMFB for 1.5 bit/stagePipelined ADC

10030 : Digital Simulation of the Generalized Unified Power FlowController System with 60-pulse GTO-based VSC

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Contents

10031 : A Synthesis of Linear Transconductors Using MOSFETs

Operating in Weak-Inversion Region Based on SINH Circuit10032 : The Multiplier Less Two-path Cross-coupled Ó- Ä Modulator10034 : An Optimized 8-Level Turbo Decoder Algorithm and VLSI

Architecture for LTE10036 : An Analog K-means Learning Processor Employing Fully-

Parallel Self-Converging Circuitry10037 : Loop Design Optimization of 4th-Order Fractional-N PLL

Frequency Synthesizers10038 : Continuous-time delta-sigma modulator using vector filter

in feedback path to reduce effect of clock jitter and excessloop delay

10039 : Temperature Coefficient Improvement of PTAT VoltageGenerator Based on Temperature Dependence of MOSFETThreshold Voltage

10040 : Robust Switched-Capacitor ADC based on b-expansion10041 : Complex Bandpass ÄÓ Modulator with Bandpass Error

Feedback Structure

10042 : A Constant-gm Rail-to-Rail Operational Amplifier withLow-gain Variation and It's Analysis

10043 : A Linearity Optimization Method for CMOS R-2R LadderNetwork

10044 : Two-Path Delay Line Based Quadrature Band-Pass ÄÓ Modulator

10046 : Active Inductor Design using Distortion ReductionTechnique

10047 : Design of Wide Gain Range CMOS VGA for WLAN Receiver

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Tsuyoshi Sugiura, Kouki Tanji, Norihisa Otani, Eiichiro OtobeSamsung Yokohama Research Institute, Kanagawa, Japan

Abstract—We have developed a single pole multi-throw (SPMT) RF antenna switch thatis based on high resistivity 0.18-um partially depleted (PD) silicon on insulator (SOI)CMOS technology with low insertion loss, high linearity, and small chip size. Bodycontacted (BC) and multi-stacked FETs are chosen to achieve a high linearity and highpower handling. A switch driver circuit is integrated with a RF switch on the same chip.The wafer level chip size package (WLCSP) is chosen for its consumer advantage. Themeasured data of the RF switch shows that the insertion loss of the TRX/TX port is lessthan 0.40 dB at 850 MHZ and 0.55 dB at 1900 MHz in the case of SP7T. For SP12T, the

insertion loss of the TRX/TX port was less than 0.53 dB at 850 MHz, 0.70 dB at 1900MHz, and 0.74 dB at 2200 MHz. The 2nd & 3rd harmonics are averaged to -60 dBm atPin 35 dBm and 850 MHz, and -45 dBm at Pin 33 dBm and 1900 MHZ, respectively. TheRF switch chips are 1.1 x 1.1 mm, 1.2 x 1.6 mm, and 1.2 x 1.8 mm for SP7T, SP10T, andSP12T, respectively. Our developed SOI CMOS SPMT RF switch is suitable for thecommercial cellular phone market.

Invited Paper I“High Performance SOI CMOS SPMT RF Switch for CellularTerminals”

Toshihiko HamasakiInformation Systems and SciencesHiroshima Institute of Technology, Hiroshima, Japan

Abstract—This paper presents the design concepts of wireless sensor network systemconstructed with autonomous sensing nodes, which operates at extremely low powerlevels. At first, conventional, wired civil structure health monitoring (SHM) system isreviewed. Then, the monitoring methodology is discussed focusing quantitativemeasurement accuracy. Issues of node synchronized sampling, multi-Layer cluster andintegrated sensor node module are discussed. Also, radio transceiver protocolcandidates are reviewed fromthe point of connection to the internet gateway. Sensornode consists of microprocessor, sensing analog front end, and radio transceiver. Lasttwo factors are critical for power consumption. Therefore, low duty cycle measurementis essential, in order to accomplish the ultra low power level, which is equivalent toenergy harvesting source, such as piezoelectric and solar cells, sensor node powermanagement device circuit design is demonstrated for the high-spec measurement.

Invited Paper II” Power ManagementofAutonomous of Wireless Sensor Node”

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Bin Shao. Analog Devices, Shanghai Design Center, Shanghai, ChinaFudan University, State Key Laboratory of ASIC and System, Shanghai, China

Abstract—Efficiency is the key parameter of the switching regulators. PFM (PulseFrequency Modulation) is often used to reduce the dynamic loss at the light loadcondition, while PWM (Pulse Width Modulation) is used in heavy load case. Theefficiency at the heavy load is usually process dependent, however there are manycircuits design considerations for the efficiency improvement and other electricalperformances in light load case. This paper will propose a method which can get theaccurate PFM threshold independent to input voltage, output voltage, switching

frequency and inductor value; as well as the accurate zero cross comparator and verylow quiescent current consumption in the skip period.

10003“A Novel Low Quiescent Current PFM Method with IndependentThreshold for Buck Switching Converters”

Antaryami Panigrahi, Prashanta Kumar Paul.Department of Electronics and CommunicationEngineering, National Institute of Technology, Silchar, Assam, India

Abstract—A new four quadrant voltage mode bulk input analog multiplier is presented.The proposed multiplier is designed to operate in weak inversion. Multiplication is doneby driving the bulk terminals of the MOS devices which offers higher linear dynamicrange of ±80mV.The simulation shows, it has a linearity error of 5.6%, THD of nearly 5%and -3dB band width of 221 kHz. Total power consumption is very low i.e. 714nW. Thecircuit operates at a supply voltage of 0.5V and is designed using AMI .6um CMOStechnology. It is suitable for low power bioelectronics and neural applications.

10009“A Novel Bulk-input Low Voltage and Low Power Four QuadrantAnalog Multiplier in Weak Inversion”

Hao San, Tomonari Kato, Tsubasa Maruyama, Masao Hotta.Integrated System Laboratory, Tokyo City University Tamazutsumi1-28-1,Setagaya-ku,Tokyo,158-8557Japan

Abstract—This paper proposes a non-binary pipeline ADC architecture based on-expansion. Proposed radix- 1bit pipeline stage with switched-capacitor (SC) multiplyingdigital-to-analog converter (MDAC) is similar to the convention alone. However, theinterstage gain of MDACs is (1


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10013“Optimum VLSI architecture of high performance synchronizer forWiMAX OFDMA system ”

Nana Sutisna, Trio Adiono.Bandung Institute of Technology,Bandung 40132 West Java Indonesia

Abstract—This paper proposes an optimum VLSI architecture for frame synchronizationin WiMAX OFDMA downlink system. Proposed synchronization method utilizespreamble properties by exploiting conjugate symmetry, periodicity of preamble and CPrepetition. Using proposed method, synchronization rate is very high under variouschannel condition. Some critical issues in hardware implementation, such ascomputational complexity, area efficiency, low latency processing, and low powerdesign are addressed to obtain optimum architecture design. Design 2 implementationresult shows chip area is about 2.7 mm and achieves targeted 56 MHz clock frequency.

Annisa Karima, Kazuyuki Wada.Department Information and Computer Science, Toyohashi University of Technology1-1, Hibarigaoka, Tempaku-cho, Toyohashi, Aichi, JAPAN 441-8580

Abstract— Substrate noise around shift register (SR) that designed and fabricated in

ROHM 0.18 µm standard CMOS process are measured. Substrate potential has slightsignal changes about several tens milivolts. Resistor networks can be used as substratemodel for system with digital parts working below 80 MHz. Model of substrate noisepropagation can be reproduced by using resistor network and 8 transistors as simplesubstrate noise sources. From measurement result of Pipeline Analog to DigitalConverter (ADC), substrate noise didn’t affect the system of fully differential amplifier.Substrate noise also makes uncertainty on decision time delay of comparator known as jitter. The comparator its self can generate substrate noise due to switching phase.

10014“Substrate Noise Measurement and Analysis on the Components ofthe Pipeline Analog to Digital Converter”

Yasuaki Inoue, Changquan Jin, Zhao Chen.Graduate School of Information, Production and SystemsWaseda University, Kitakyushu, JapanZhangcai HuangFukuoka Industry Science Technology FoundationFukuoka, Japan

Abstract—In this paper, we propose a high-voltage tolerant rail-to-rail input and

operational amplifier with almost 2VDD output over the device breakdown voltage VDD.The proposed amplifier is verified by circuit simulation using a 0.18um standard CMOSprocess, where VDD =1.8V. The simulation results show that the proposed circuit has acommon-mode input voltage range and an output voltage swing of almost 2VDD .

10015

”An Almost 2VDD Rail-to-Rail Input and Output Operational AmplifierUsing VDD CMOSFETs”

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10017”Design and Implementation 2k/4k/8k FFT-IFFT Core using BlockFloating Point”

Amy Hamidah Salman, Andy’es Fourman Duta Akbar Sudirdja.Electrical Engineering, Sekolah Teknik Elektro dan InformatikaInstitut Teknologi Bandung, Indonesia

Abstract—DVB-H and DVB-T are digital television standard created by DVB consortiumin Europe. DVB-T used for static digital television (terrestrial) whereas DVB-T used formobile digital television. These two DVB standard using OFDM modulation technique.This modulation allow each sub-carrier neighboring without creating inter carrierinterference (ICI). The modulation using IFFT to convert data signal from frequencydomain into time domain. And in demodulation part used FFT module which convert itback into frequency domain in receiver module. FFT-IFFT 2k/4k/8k using Block Floating

Point (BFP) which made support FFT and IFFT algorithm for 2048 points, 4096 pointsand 8192 points mode. The FFT-IFFT core created using radix-2, radix-4 and radix-8.Designed to receive data continuously without temporary buffer. The design of FFT-IFFT module 2k/4k/8k started with MATLAB © functional design as a model for the nextstage. Furthermore, the hardware architecture design is made referring to thefunctional modelling design using MATLAB ©. This architectural design will be thefoundation in making bit precision modelling. And then bit precision model design as afoundation for designing hardware using Register Transfer Level (RTL). The results ofthe FFT-IFFT output modules meet standards set by the DVB consortium with theresults of testing the maximum frequency of FFT-IFFT 2k/4k/8k Core using BlockFloating Point (BFP) is 72.83 MHz which has been shown that qualify on the standard

(40 MHZ). In addition the module has a high throughput with an average throughput has39.7 M symbols / s.

10018”Architecture of High-Efficiency Digitally-Controlled Class-E PowerAmplifier”

Jiani Ye, Zachary Nosker, Yasunori Kobori, Haruo Kobayashi, Kiichi Niitsu, NobukazuTakai, Takeshi Oomori, Takahiro Odaguchi, Isao Nakanishi, Kenji Nemoto, JunichiMatsuda.Department of Electronic Engineering, Gunma University Faculty of Engineering 1-5-1, Tenjincho, Kiryu, Gunma 376-8515

Abstract—This paper describes the analysis and design of digitally-controlled class-Epower amplifiers, which are suitable for fine CMOS implementation. Two methods forimplementing digitally-controlled class-E(-like) amplifiers have already been proposed:using NMOS switch arrays or digital PWM. In this paper we analyze the operation andefficiency of these methods, and then propose combining them to achieve higherefficiency.

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Kazuhiro Takahagi, Hiromichi Matsushita, Tomoki Iida, Masayuki Ikebe, Yoshihito Amemiya, Eiichi Sano.Graduate School of Information Science and Technology, Research Center forIntegrated Quantum Electronics, Hokkaido University, Sapporo 060–0814 Japan

Abstract— We developed a wake-up receiver comprised of subthreshold CMOScircuits. The proposed receiver includes an envelope detector, a high-gain basebandamplifier, clock and data recovery (CDR), and a wake-up signal recognition circuit. Thedrain nonlinearity in the subthreshold region effectively detects the baseband signal witha microwave carrier. The offset cancellation method with a biasing circuit operated bythe subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A

PWM CDR drastically reduces the power consumption of the receiver. A 2.4-GHzdetector and high-gain amplifier were designed and fabricated with 0.18-ìm CMOSprocess with one poly and six metal layers. The fabricated detector and high-gainamplifier achieved a tangential sensitivity of - 47.2 dBm while consuming only 6.8 ìWfrom a 1.5 V supply.

10019“Low-power Wake-up Receiver With Subthreshold CMOS Circuits forWireless Sensor Networks”

Takemasa Komori, Tadashi Shibata.Department of Electrical Engineering and Information Systems, The University of Tokyo7-3-1 Hongo, Bunkyo-ku, Tokyo, 113-8656, Japan

Abstract—A CMOS image sensor for calculating optical flow based on ±1-pixel-shiftblock matching has been developed. In order to detect multiple-speed objects in thesame scene, a multiple-frame block matching scheme has been explored. Each pixelstores multiple pixel intensities with different time stamps in analog memories andprovides neighboring pixels with appropriate data when the right timing of motiondetection comes in respective neighbors. As a result, multiple-speed objects detectionhas been made possible by best-match search only within ±1-pixel range. Optical flow isefficiently calculated in row parallel processing architecture. The proof-of-concept chipwas fabricated in a 0.18-ìm CMOS technology, which demonstrated the performance of139 frame/sec at only 10 MHz of operation.

10020”A CMOS Optical-Flow Image Sensor Based on Speed-AdaptiveMultiple-Frame Single-Pixel-Shift Block Matching”

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Shintaro Tanaka, Akira Hyogo, Keitaro Sekine.Department of Electrical Engineering, Faculty of Science and Technology Tokyo University of Science, Japan

Abstract—This paper presents a low power and wideband differential LNA-Mixer in0.18-ìm CMOS technology. This method allows wideband input matching and getting ahigh conversion gain. In addition, we design the low power LNA -Mixer using two noisecanceling techniques. The simulation results show that a minimum single- sidebandnoise figure is 7.6 dB and a conversion gain of more than 20.6 dB from 0.6 to 4.5 GHz. Ithas a third-order intermodulation intercept point of -6 dBm at 3GHz. The proposed circuitconsumes 9.7 mW with a 1.2 V supply voltage. Compared to the conventional circuit, we

can reduce the power consumptions of 30 percent. However, simulation results show0.2–dB worse NFs in average compared to conventional one.

10022“Power Consumption Improvement of Wideband CMOS DifferentialLNA –Mixer with Two Noise Cancellation”

Naoki Tsukahara, Akira Hyogo, Keitaro Sekine .Department of Electrical Engineering, Faculty of Science and Technology Tokyo University of Science, Japan

Abstract— This paper presents an inductorless variable gain mixer for two bands use;900 MHz and 2.4 GHz. By using variable resistor, the proposed mixer has the sameConversion Gain (CG) at both bands, and it can select from low noise figure mode to lowcurrent mode. The simulation results in a 0.18-ìm CMOS technology show that we canselect the CG of 15 dB or 10 dB at both bands respectively, noise figure of less than 12dB or 15 dB and current consumption of less than 6 mA or 2 mA with a 1.8 V supply.

10023”An Inductorless Variable Gain Mixer with Variable Resistor for 900-MHz and 2.4-GHz application ”

Dai Ichihoshi, Akira Hyogo, Keitaro Sekine.Department of Electrical Engineering, Faculty of Science and Technology Tokyo University of Science, Japan

Abstract— This paper presentsaCMOS LNAwhich is improvedgain. The proposed LNAuses negative resistance of an active inductor to improve its gain. The simulation resultsusing 0.18-? m CMOS technology show that the gain of proposed circuit achieves S21of27.8dB which is 11.6dB higher than 16.2dB of a LNA with a load inductor.

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”A gain improved CMOS LNA using negative resistanceof an activeinductor ”

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Dai Miyauchi, Akira Hyogo, Keitaro Sekine .Department of Electrical Engineering, Faculty of Science and Technology Tokyo University of Science, Japan

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Abstract— This paper presents a cascode class-E power amplifier (PA) with improvedpower efficiency by keeping parallel capacitance of switch to be constant. A conventionalcascode class-E PA has an inductor paralleled to a common-source transistor. Theproposed class-E PA inserts a capacitor between the drain node of common-gatetransistor and the source node of that in addition to the conventional circuit. Thesimulation results using 0.18 m CMOS technology show that the proposed circuitimproves the drain efficiency of 1.4% compared to the conventional one at gate length

0.4 m.

10025“ A Cascode Class-E Power Amplifier with Improved Power Efficiencyby Adding a Parallel Capacitor ”

Zachary Nosker, Yasunori Kobori, Haruo Kobayashi, Kiichi Niitsu,Nobukazu Takai.Department of Electronic Engineering, Gunma University Takeshi Oomori, Takahiro Odaguchi, Isao Nakanishi, Kenji Nemoto AKM Technology Corporation

Junichi Matsuda Asahi Kasei, Power Devices Corporation

Abstract— A small, low power bootstrapped boost regulator is introduced that can startup with an input voltage of 240mV and achieve a maximum efficiency of 96%. Theeffectiveness of this approach is shown through Spectre simulation results.

10026”A Small, Low Power Boost Regulator Optimized for EnergyHarvesting Applications ”

Takeshi Ohbuchi, Fujihiko Matsumoto.Department of Applied Physics, National Defense Academy 1-10-20, Hashirimizu, Yokosuka, 239-8686, Japan

Abstract— For medical devices, low frequency and low power applications are required.Thus, a transconductor which has a low transconductance is needed. The conventionalcurrent division scheme wastes the operating current. This paper proposes an improvedlocal-feedback MOS transconductor operating in subthreshold region. The proposedtransconductor is optimally designed using maximally approximation method. From theoptimization, two optimum values are obtained. The characteristics of proposed

transconductor are confirmed by simulation. The transfer characteristics of theproposed transconductor are linear, and the CMRR around 60 dB and the THD, thefrequency of the sinusoidal input is 1 kHz, under the -50 dB are satisfactory. Simulationresults show validities and availability of the proposed transconductor.

10027”An Improved Local-Feedback MOS Transconductor for LowFrequency Applications ”

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Nicodimus Retdian, Shigetaka Takagi.Global Edge Institute, Dept. of Communications & Integrated SystemsTokyo Institute of Technology, Tokyo, Japan

Abstract— A design methodology for implementation of lownoise switched-capacitorlow-pass filter (SC LPF) with small area consumption is proposed. The proposedmethod is focused on the reduction of operational amplifier noise transfer gain at lowfrequencies and the reduction of total capacitance. A new SC LPF topology is proposedin order to adapt the correlated double sampling and capacitance scaling technique atthe same time. A design example shows that proposed filter reduces the totalcapacitance by 90.4% compared to the conventional one without having significant

increase in noise transfer gain.

10028“Implementation of Low-Noise Switched-Capacitor Low-pass Filterswith Small Area”

Mohd Hairi, Zulfiqar Ali Abdul Aziz.Department of Electronic Engineering, Gunma University

Abstract—This paper presents the design of fully differential telescopic op-amp withoutstanding characteristic of high bandwidth and slew rate. The fully deferentialtelescopic op-amp with common mode feedback (CMFB) has been design using Silterra0.18ìm CMOS technology. The fully differential telescopic op-amp has been used tosimulate the operation of 1.5 bit/stage pipelined ADC for Worldwide Interoperability forMicrowave Access (WiMAX) application successfully.In this paper, the trade-off between gain, bandwidth and current consumptions is achallenging task. The amplifier consists of two parts, a fully differential telescopic op-amp that provides all the open loop gain and common mode feedback to maintain theconstant output voltage. Designed in CMOS technology, the design required 3.3V powersupply and 112mA current consumption to produce 41dB voltage gain with 54.71MHzbandwidth and 44.81? phase margin. The design has very high slew rate 2.13k V/ìs andfast settling time at 7.5ns.

10029”Telescopic Op-Amp Design with CMFB for 1.5 bit/stage PipelinedADC ”

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Rakhmad Syafutra Lubis Electrical Engineering, Syiah Kuala UniversityBanda Aceh, Indonesia

Abstract— The Generalized Unified Power Flow Controller (GUPFC) is a VoltageSource Converter (VSC) based Flexible AC Transmission System (FACTS) controllerfor shunt and series compensation among the multiline transmission systems of asubstation. The paper proposes a full model comprising of 60-pulse Gate Turn-Offthyristor VSC that is constructed becomes the GUPFC in digital simulation system andinvestigates the dynamic operation of control scheme for shunt and two series VSC foractive and reactive power compensation and voltage stabilization of the electric grid

network. The complete digital simulation of the shunt VSC operating as a StaticSynchronous Compensator (STATCOM) controlling voltage at bus and two series VSCoperating as a Static Synchronous Series Capacitor (SSSC) controlling injectedvoltage, while keeping injected voltage in quadrature with current within the powersystem is performed in the MATLAB/Simulink environment using the Power SystemBlockset (PSB). The GUPFC, control system scheme and the electric grid network aremodeled by specific electric blocks from the power system blockset. The controllers forthe shunt VSC and two series VSC are presented in this paper based on a decoupledcurrent control strategy. The performance of GUPFC schemes connected to the 500-kVgrid are evaluated. The proposed GUPFC controller schemes is fully validated by digitalsimulation.

10030“ Digital Simulation of the Generalized Unified Power Flow ControllerSystem with 60-pulse GTO-based VSC ”

Fujihiko Matsumoto, Ryutaro Sugimoto, Takeshi Ohbuchi, Tomomi Abe.Department of Applied Physics, National Defense Academy 1-10-20, Hashirimizu, Yokosuka, Kanagawa, 239-8686, Japan

Abstract—In this paper a synthesis of linear transconductors using MOSFETs operatingin weak-inversion region is pro-posed. The proposed transconductors are extendedSINH circuits, which are based on a SINH circuit with an intermediate voltage terminal.The transfer characteristic of the SINH circuit is not linear. The linear input ranges of theproposed transconductors become wider than the SINH circuit. The proposedtransconductors have several intermediate voltage nodes. The intermediate voltagesare realized by an active voltage divider composed of source coupled pairs. The voltagedivider has high input impedance and it is suitable for low-voltage circuits.The simulationresults show that the proposed technique is effective for improvement of the linearity.

10031”A Synthesis of Linear Transconductors Using MOSFETs Operatingin Weak-Inversion Region Based on SINH Circuit”

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23/30

Takeshi Shima, Takumi Ikegami.

Department of Electronics and Informatics FrontiersKanagawa University, Yokohama, Japan 221–8686

Abstract— The cross-coupled two-path sigma-delta modulator requires the additionalmultipliers to improve the noise shaping performance. In this paper, to reduce additionalmultipliers in the conventional cross-coupled two-path sigma-delta modulator, two newcircuits are proposed and their stability test analysis is performed.

10032“The Multiplier Less Two-path Cross-coupled Ó ? ÄModulator ”

Ardimas Andi Purwita, Trio Adiono.School of Electrical Engineering and Informatics, Electrical Engineering Department Institut Teknologi Bandung, Indonesia

Abstract—Turbo code is a high performance channel coding which is able to closelyreach the channel capacity of Shannon limit. It plays an important role to increase theperformance in one of the latest standard in the mobile network technology, such as LTE[1]. In this paper, Turbo code decoder VLSI Architecture is discussed. The optimization isdone to reduce computational complexity and excessive memory requirement as well as

the latency and delay. In order to increase the processing speed, 8-level parallelarchitecture is proposed. Furthermore, to increase the processing parallelization, wealso applied the Maxlog-MAP [2][3][4], Sliding Window Algorithm (SWA) [5], and dualbank ram for interleaver and deinterleaver block. Based on the simulation result,proposed algorithm is almost 16 faster than original algorithm [6] and 42 times smallerfor the memory requirement. Additionally, proposed algorithm reduces the size ofinterleaver and deinterleaver block by almost 50%. Besides, the decoder are alsoreduced by applying shared modules.

10034”An Optimized 8-Level Turbo Decoder Algorithm and VLSI

Architecture for LTE”

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10036“An Analog K-means Learning Processor Employing Fully-ParallelSelf-Converging Circuitry”

Renyuan Zhang, Tadashi Shibata.Department of Electrical Engineering and Information Systems, The University of Tokyo7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan

Abstract— A fast self-converging analog K-means learning processor is presented inthis paper for use in image clustering. The image patterns represented by high-dimensional vectors can be clustered into different classes based on our proposedhardwarefriendly version of the K-means algorithm. In order to speed up the K-meanslearning, we developed an analog circuit to carry out the Euclidean distance betweenhigh-dimensional vectors in realtime. Furthermore, a fully-parallel learning and self-converging structure was built employing these analog circuits. The chiparea and

interconnect explosion problem has been resolved in this proposed structure. Since thelearning autonomously proceeds in a fully-parallel manner via analog free-feedbacksignals without any clock control, learning can be accomplished within a single clockcycle, which is far faster than the conventional iterationbased approaches. A proof-of-concept system was constructed and verified by the HSPICE and Nanosim simulations.Sixteen actual images of two objects were randomly selected from the database andconverted into 64-dimensional vectors. Feeding these vectors into our K-means system,the images were all correctly categorized into two classes within one clock cycle forseveral different initialization conditions.

10037“Loop Design Optimization of 4th-Order Fractional-N PLL FrequencySynthesizers”

Lee Jun Gyu, Shoichi Masui.Research Institute of Electrical Communication,Tohoku University, Sendai, Japan

Abstract—We propose a methodology of loop design optimization for 4th-orderfractional-N PLL frequency synthesizers featuring a settling time of 5? sec for

applications such as an active RFID and automobile smart-key systems. The optimizeddesign flow overcomes the inaccuracy to derive the relationship between the settlingtime and loop bandwidth in the 4th-order PLL by using MATLAB Control System Toolboxand features the worst-case design against the process, voltage and temperature (PVT)variations in the loop filter components. Also the trade off between the phase noise andarea is considered. The optimization process consists of 1) derivation of the accuraterelationship between the settling time and loop bandwidth for various PVT conditions, 2)derivation of phase noise and area as a function of an area-dominant filter capacitance,and 3) derivation of all loop filter components. The optimized design result is comparedwith circuit simulations using an actually designed 4th-order fractional-N PLL in a 1.8V0.18? m CMOS technology, and the error has been revealed as less than 5.3%

(0.2? sec) that is suitable for the target applications.

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10038“Continuous-time delta-sigma modulator using vector filter infeedback path to reduce effect of clock jitter and excess loop delay”

Yuki Kimura, Akira Yasuda, Michitaka Yoshino.Engineering Research Course, Faculty of Science and Engineering University of Hosei, Koganei, Japan

Abstract— In this paper, we propose a novel delta-sigma modulator (DSM) that reducesthe effects of clock jitter and excess loop delay by using a vector filter in the feedbackpath. The vector filter divides the input signal into a high-frequency part and a low-frequency part. The low-pass signal is placed in the path to the first-stage digital-to-analog converter (DAC) for reducing the effects of the clock jitter, and the high-passsignal is placed in the feedback path to the last integrator in order to compensate for theexcess loop delay. The DSM using the vector filter in the feedback path (DSM-VF) is

verified using MATLAB/Simulink. Further, a clock jitter (0.1%) in DSM-VF leads to animprovement in the signal-to-noise-ratio (SNR) to 22.5 dB as compared to the SNR of aconventional CTDSM. Moreover, the SNR deterioration caused by the excess loopdelay is improved.

10039“Temperature Coefficient Improvement of PTAT Voltage GeneratorBased on Temperature Dependence of MOSFET Threshold Voltage”

Junichi Fujitsuka, Kawori Sekine.Department of Electric technology, Meiji University Kanagawa, Japan

Abstract—PTAT Voltage Generator is composed with MOSFETs in subthreshold regionat view of ultra low power supply and small scale. Temperature coefficient is low and hasto be improved. Stacking PTAT circuits improve temperature coefficient. However bystacking PTAT circuits, the range of sensing temperature would be narrow because ofoperation region of MOSFETs. In order to keep the range of sensing temperature, theway of improving temperature coefficient based on temperature dependence ofMOSFET threshold voltage is proposed. The proposed circuit consisting of CTAT

Voltage Generator and level shifter compensates the temperature dependence ofMOSFET threshold voltage. The n-stacked PTAT Voltage Generator with proposedcompensation circuit can improve the temperature coefficient. The proposed circuit wasfabricated with 0.18ìm n-well CMOS process and measured. The measured value iscompared with theoretical value and considered. The theoretical value of temperaturecoefficient is based on diffusion current of four-terminal MOSFET operating insubthreshold region.

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10040

“Robust Switched-Capacitor ADC based onb-expansion”

Tsubasa Maruyama, Hao San, Masao Hotta.

Integrated System Laboratory, Tokyo City University Tamazutsumi 1-28-1, Setagaya-ku, Tokyo, 158-8557 Japan

b

b

b

Abstract— In this paper, a cyclic ADC architecture with -encoder is proposed and

circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the

conventional binary ADC, the proposed ADC outputs -expansion code and has an

advantage of error correction. This feature makes ADC robust against capacitormismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because thepower penalty of highgain amplifier and the required accuracy of circuit elements forhigh resolution ADC can be relaxed, the proposed architecture is suitable for deep

submicron CMOS technologies beyond 90 nm. We also propose a -value estimationalgorithm to realize high accuracy ADC based on -encoder.

10041“Complex Bandpass ÄÓ Modulator with Bandpass Error FeedbackStructure”

Shuhei Kato, Satosho Saikatsu, Akira Yasuda, Michitaka Yoshino.Engineering Research & Faculty of science and Engineering Course

Hosei University, 3-7-2, Kajino-cho, Koganei-shi, Tokyo 184-8584, Japan

Abstract—This paper describes a method for reducing the influence of the mismatchbetween the I and Q paths in a complex bandpass ÄÓ modulator. The disadvantage ofsuch modulators is SNR deterioration due to aliasing of image band noise when amismatch exists between I and Q paths. This situation can be improved by adding a newnotch filter to reduce the image band noise. Consequently, a bandpass error feedbackstructure is proposed here to add the new notch to an image signal band. This structurecan produce a new notch in the desired signal band and image signal band. Therefore,this structure not only reduces the influence of the mismatch but also strengthens thenoise-shaping characteristic in the desired signal band. The effectiveness of this

structure is confirmed by a simulation using MATLAB with Simulink.

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10042“A Constant-gm Rail-to-Rail Operational Amplifier with Low-gainVariation and It's Analysis”

Nobuyuki Yokoyama, Cong-Kha Pham.Dept. of Engineering ScienceThe University of Electro-Communications (UEC), Chofu,Japan

Abstract— A constant-gm Rail-to-Rail Operational Amplifier with Low-gain Variation isintroduced in this paper. The input stage is based on the dynamic current scalingtechnique, and the output stage with feed-forward class-AB output circuit. The dynamiccurrent scaling technique is proposed as scales the output signal currents of the inputdifferential pairs dynamically for a constant-gm while keeping tail currents of the inputtransistors unchanged. To obtain low gain variation, the feed-forward class-AB outputcircuit is added. This proposed Op Amp's configuration suppresses the change of gain

and phase margin over the entire common-mode input range. Moreover, gain,commonmode rejection ratio (CMRR) and power-supply rejection ratio (PSRR) areclarified by the equivalent circuit of the proposed circuit. The rail-to-rail Op Amp isdesigned with 5V of supply voltage in 1.2um CMOS technology, and simulated by H-spice. The Op Amp has 88 dB gain, 5.3-MHZ bandwidth (PM=71°) at 10pF and 100kÙoutput load. Simulations show that, when the input common-mode voltage swings fromrail-to-rail, the OpAmp's input stage gm varies within 7.8%, the output stage gm varieswithin 3% and gain varies within 0.6 dB. When simulated values and calculated valuesare compared by each of gain, CMRR and PSRR, it is recognized that each equivalentcircuit is clarified.

10043“A Linearity Optimization Method for CMOS R-2R Ladder Network”

Yuta Kato, Cong-Kha Pham.Dept. of Engineering ScienceThe University of Electro-Communications (UEC), Chofu,Japan

Abstract—This paper presents a optimization method of a linearity for CMOS only R-2Rladder network. This new approach significantly reduces the integral non-linearity (INL)and differential non-linearity (DNL) of R-2R ladder by adjusting channel width W forreducing current mismatch on each node of a bit cell. 8-bit R-2R ladder have beenoptimized in BSIM3v3 level 53 (0.18um) model on a circuit simulator in which channellength L is vaned from 0.18um to 10.0um. The INL value was reduced from ±4LSB to±0.4LSB and the DNL value was reduced from ±6LSB to ±0.7LSB in case which L is0.18um and initial W is 1.44um. The optimized results and other specifications arepresented and the limitations are discussed.

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10044“Two-Path Delay Line Based Quadrature Band-Pass ÄÓ Modulator”

Nithin Kumar Y.B., Edoardo Bonizzoni, Amit Patray, Franco Maloberti.

Department of Electronics, University of Pavia, Via Ferrata, 1 - 27100 Pavia - ITALY Department of Electrical and Electronics, IIT Kharagpur - INDIA

ÄÓ

ÄÓ

Abstract— This paper presents a new concept for an efective quadrature band-passmodulator and discusses the high level implementation for a third order two-pathscheme based on delay line. The methodology uses an architecture which locks IFfrequencies to the sampling frequency. Robustness of the structure against themismatch is analyzed. Simulations at the behavioural level verify the architectureimplementation which uses a novel switched capacitor scheme. Index Terms—Analog-to-Digital conversion, band-pass modulation, complex filters.

10046“Active Inductor Design using Distortion Reduction Technique”

Takahide Sato, Toshihiro Ito.University of Yamanashi Interdisciplinary Graduate School of Medicine and Engineering

Abstract—This paper proposes a distortion reduction technique for active inductors.Bias current of a MOSFET, which acts as transconductor, is controlled to reduce adistortion of a active inductor. When a input voltage swing of the MOSFET increases, its

bias currents is decreased by a control circuit. As a result of this control,transconductance of the MOSFET remains constant. An active inductor using thistechnique is free from distortion caused by transconductance of a MOSFET. Theproposed technique is applied to two basic conventional active inductors and novel lowdistortion active inductors are derived. HSPICE simulations show that distortion of theproposed active inductor is very low. One of the proposed low distortion active inductorsis applied to a 2nd order bandpass filter. Thanks to the proposed technique, the totalharmonic distortion of the bandpass filter becomes 0.26% at 1 GHz.

10047“Design of Wide Gain Range CMOS VGA for WLAN Receiver”

Laksono Widyo IsworoKyushu Institute of Technology Cosy Muto Hiroshi TanimotoNagasaki University Kitami Institute of Technology

Hiroshi OchiRadrix Co. Ltd

Abstract—A design of variable gain amplifier (VGA) for WLAN 802.11 a/b/g receiver hasbeen reported. The proposed VGA which is designed in 0.18 m CMOS technology under 1.8 V supply voltage has about 70 dB gain range which varies from 0 to 70 dB over 16

MHz bandwidth. This wide gain range is achieved in coarse and fine gain scheme bycombining and controlling digitally high gain amplifiers and a dB-linear gain amplifierwhich is driven by a novel pseudo-exponential function generator.

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Author Index

Akira Hyogo

Akira Yasuda Amit Patra Amy Hamidah Salman Andy’es Fourman Duta Akbar Sudirdja Annisa Karima Antaryami Panigrahi Ardimas Andi PurwitaBin ShaoChangquan JinCong-Kha PhamCosy MutoDai IchihoshiDai MiyauchiEdoardo BonizzoniEiichi SanoFranco MalobertiFujihiko MatsumotoHao SanHaruo KobayashiHiromichi MatsushitaHiroshi Ochi

Hiroshi TanimotoIsao AkiyamaIsao NakanishiJiani YeJunichi FujitsukaJunichi MatsudaKawori SekineKazuhiro TakahagiKazuyuki WadaKazuyuki Wakabayashi

Keisuke KatoKeitaro SekineKenji NemotoKiichi NiitsuLaksono Widyo IsworoLee Jun GyuMasao HottaMasayuki IkebeMichitaka YoshinoMohd HairiNana SutisnaNaoki TsukaharaNicodimus Retdian

16

........................................................................................................5, 6, 7

12, 13154432

1023

141567

155

157, 9

2, 134, 7

515

15474

127

12534

46, 77

4, 71511

2, 135

12, 138368

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Author Index

Nithin Kumar Y.B.

Nobukazu TakaiNobuyuki YokoyamaOsamu YamamotoPrashanta Kumar PaulRakhmad Syafutra LubisRenyuan ZhangRyutaro SugimotoSatoshi SaikatsuShigetaka TakagiShintaro TanakaShuhei KatoShoichi MasuiTadashi ShibataTakahide SatoTakahiro OdaguchiTakao OotsukiTakemasa KomoriTakeshi OhbuchiTakeshi OomoriTakeshi ShimaTakumi Ikegami

Takuya YagiTomoki IidaTomomi AbeTomonari KatoToshihiro ItoTrio AdionoTsubasa Maruyama

Yasuaki Inoue Yasunori Kobori Yoshihito Amemiya

Yuki Kimura Yuta KatoZachary NoskerZulfiqar Ali Abdul AzizZhangcai HuangZhao Chen

...................................................................................................15

.....................................................................................................4, 7................................................................................................14......................................................................................................4

..............................................................................................2..........................................................................................9

.........................................................................................................11.......................................................................................................9

......................................................................................................13.......................................................................................................8

.........................................................................................................6..............................................................................................................13

...........................................................................................................11....................................................................................................5, 11

....................................................................................................15.....................................................................................................7

.............................................................................................................4.......................................................................................................5

.....................................................................................................7, 9...........................................................................................................7

..........................................................................................................10........................................................................................................10

.................................................................................................................4

.................................................................................................................5

.................................................................................................................9............................................................................................................2

..............................................................................................................15............................................................................................................3, 10

..............................................................................................2, 13.............................................................................................................3

..........................................................................................................7.....................................................................................................5

.............................................................................................................12..................................................................................................................14......................................................................................................4, 7

...............................................................................................8.........................................................................................................3

...................................................................................................................3

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Abstract Proceeding AVLSI 2018

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