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EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical Interfaces
Lecture #15
CDR & Coding
Jared Zerbe3/9/04
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AgendaIntroductionExample CDRsCDR IssuesSecond-order loops4-PAM CDRsCoding and Transition Density
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Clocking : Terminology
Needs CDR!
Can do with orwithout CDR
Poulton’99
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What’s a CDR?Clock and Data Recovery
Recovering clock from the dataCan recover clock completely, or just phaseJust phase: need a reference clock
Why?Allows separate xtals on different boardsDon’t have to match trace lengths, delaysEasier system design / clock distribution
Why NotExpensive: takes area, powerRequires coding or transition density or at a minimum a training sequence
8b10b coding uses 10b to xfer 8b of info; 20% BW loss
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Clock Data Recovery
CDR
PLL
PLLoutCDRout
DataData
CLK
PLLout
Data
CDRout
Clock Data Recovery
CDR
PLL
PLLoutCDRout
DataData
CLK
PLLout
Data
CDRout
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Clock Data Recovery
CDR
PLL
PLLoutCDRout
DataData
CLK
PLLout
Data
CDRout
Clock Data Recovery
CDR
PLL
PLLoutCDRout
DataData
CLK
PLLout
Data
CDRout
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Clock Data Recovery
CDR
PLL
PLLoutCDRout
DataData
CLK
PLLout
Data
CDRout
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AgendaIntroductionExample CDRsCDR IssuesSecond-order loops4-PAM CDRsCoding and Transition Density
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Example CDR : PLL TechniqueSimple bang-bang PLL
Observe data with phase detectorFilter Early/Late & drive VCO
AdvantagesGood frequency rangeLow Jitter
ChallengesPhase offsetLock time - startup sequenceLoss of lock - coding dependantHow to integrate?
Multiple PLLs Harmonic locking problems
Incoming Data
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Dual PLL Problem: Harmonic Locking
Potentially serious in highly integrated plesiochronous systems where residual phase error is close to noise injection in magnitude
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2-PAM Eye With Density
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Slicer
PD
deserializer
PLL
dataOut
ref Clk
Phasecontrol
Phasemixeredge Clk
data Clk
2x Oversampling
Generate early/late from dn,dn-1,enSimple 1st order loop, cancels receiver setup time
Jitter on d Clk ≠ PLL outputBase is linear PLL jitterCan add non-linear phase selector noise from CDR
dn-1
dn
en (late)
dn
en
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Dual-Loop CDRCombination of
Core PLL provides multiple phases at frequencyPeriphery DLL mixes and make desired phase
AdvantagesAvoids harmonic locking
Easy to integrate manyRapid CDR lock timeCDR very stable
Digital = flexible filtering, controlCan even ‘hold’ phase state
ChallengesLimited Freq offset from PLLJitter not as low as PLL
PDLow Pass
Filter VCORefClk
÷ N
Phase MixersCDRLogic
RXData
RClk
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Baud-Rate CDR
Use information from data-level sampler(already there for adaptation) : eliminate edge sampler, eclk
Curvature to waveform here Use a comparitor to differentiate between dlev & signalDecide later if 0 or 1 from comparitor means early or late
Even more transition-like level behavior in 4-PAM mid-data levels
dlev
dn
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AgendaIntroductionExample CDRsCDR IssuesSecond-order loops4-PAM CDRsCoding and Transition Density
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CDR Issues : Transitions & TrackingCDRs require transition density
PLL based CDRs require to keep lock even in mesochronousDLL based require for plesiochronous tracking
Often coding is used to guaranteeCan alternately use a scrambler + XOR
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CDR Issues : Jitter
CDR Jitter starts out worse than PLL jitterAlso can have ‘dither jitter’ : phase wander when locked
dither
lock
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CDR Dither JitterCaused by need to track plesiochronous differences Dither jitter set by
Latency of the loop usually 10-20 cyclesStep size usually 10m-UI# of averages usually 16+
The last two along with transition density set the tracking rate
-> Conflicting requirements between tracking and jitter
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AgendaIntroductionExample CDRsCDR IssuesSecond-order loops4-PAM CDRsCoding and Transition Density
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Second-Order LoopsIdea : solve the plesiochronous vs. jitter problem
Build a second-order loop insteadOne loop for tracking the constant frequency difference with very low tracking rate & bandwidth (thus low jitter)A very small step size & dither for tracking normal phase shifts
Currently an area of interesting research
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AgendaIntroductionExample CDRsCDR IssuesSecond-order loops4-PAM CDRsCoding and Transition Density
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4-PAM : Multiple Transitions
So many transition types make 2-PAM CDR unusable
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4-PAM Eye With Density
Offset transitions clearly visibleBut good transitions exist…
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4-PAM Edges & CDR Approach #1
Offset edge sampler to data level to get mid-levelsBest available edge-rate in FSE systemRequires edge samplers placed accurately on data level
Mid-level
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01
00
MSB threshold
MSBData levels
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4-PAM Edges & CDR Approach #2
Use all minor transitions and one major transitionMore transitions to choose from, no voltage offset requiredPoorer edge-rate from minor transitions
Minor Major
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01
00
MSB threshold
LSBthresholds
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Measured 4-PAM CDR Performance
2-PAM CDR on 4-PAM data
60ps p-p @ 8Gb/s
Phase
Phase
Cycle
4-PAM CDR uses only minor transitions Lower dither jitter
35ps p-p @ 8Gb/s
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AgendaIntroductionExample CDRsCDR IssuesSecond-order loops4-PAM CDRsCoding and Transition Density
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CDR In a Plesiochronous System
Goal is to transfer 8bits @ f1 on chip 1 to 8bits @ f2 on chip2First encode and transfer data based on local clock f1Then recover data and clock (f1) on chip 2Elastic buffer (FIFO) used to transfer data from f1 to f2Finally, decode to get 8 bits @ f2
PLL CDR
Encode Serializer FIFODeserializerTx Rx
8b/10b
ElasticBuffer
8 bits@ f1
10 bits@ f1
10 bits@ f1
Decode
10b/8b
10 bits@ f2
8 bits@ f2
f2f1
CHIP 1 CHIP 2
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Plesiochronous System ImpactThere must be packets with appropriate slack time
How else to recover timing difference?Idle characters must be recognized for slack
There must be FIFOs deep enoughSet by maximum frequency difference & maximum data length
CDR must have tracking rateMust be able to track maximum difference including dither
Frequency difference, protocol, maximum data packet size different system components
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CDR : Coding & Transition DensityCDR requires transition density to keep lockAC - coupling requires DC-balancePlesiochronous operation requires packets & null characters…..Coding as solutionTypical code : 8b10b from IBM
8 bits into the link => 10 bits on the wiresRaw data rate must be 25% faster than effective data rate
6.25Gb raw for 5Gb effective8b10b code guarantees
DC balanceTransition density : 2 transitions every 10 bitsReserved codes, control characters
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8b10b Code Overview
• DC Balanced within everycode word
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64/66 Code Overview
Walker IEEE 802.3HSSG
Much lower overheadPoorer DC balance & transition properties
