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Alice EMCAL meeting, 15-16 July 20081
EMCAL jet trigger status
Olivier BOURRION
LPSC, Grenoble
Alice EMCAL meeting, 15-16 July 20082
Trigger specification :
• L0 trigger : OR of the 34 L0 calculated by the TRU.
• L1-gamma trigger: Energy summed over sliding window of 4x4 towers (2x2 fast
OR) and compared to a multiplicity corrected threshold.
• L1-jet trigger : Energy summed over a sliding window of n*n subregions and
compared to a multiplicity corrected threshold (a subregion is defined as 8x8
towers)
Reminder : the Summary Trigger Unit
STU
TRU
TRU
L0
L1-gamma
L1-jet
34 T
RU
Multiplicity from V0
4 diff pairEthernet CAT7 cable
TRU is clocked by the BC clock forwarded by STU (40.08MHz)
TTC link
To
CT
P
DDLDCS
Put trigger data in the data stream on
L2a (via DDL)
LVDS links
Alice EMCAL meeting, 15-16 July 20083
Detector layout as understood
Alice EMCAL meeting, 15-16 July 20084
EMCAL layout (1/2)
Region orientation / numbering?View from beam or cal frame?
Mirr
ored
SM
The understanding of the layout is thekey point for building the trigger algorithm
Alice EMCAL meeting, 15-16 July 20085
EMCAL layout for one TRU (2/2)
The ADC channel number has to be known by STU, in order to compute the triggersFor instance, one 4X4 window is channel 5,6,9 and 10
Confirmation of the ADC channel affectation vs geometrical position
?
Alice EMCAL meeting, 15-16 July 20086
Functional simulation scenario(see R. GUERNANE talk)
1
3 2
1. Overlapping 2 neighboring regions in phi
2. Overlapping 2 neighboring regions in Z
3. Overlapping 4 regions
Alice EMCAL meeting, 15-16 July 20087
Current status
Alice EMCAL meeting, 15-16 July 20088
DCS board modification and testing
The transformer less Ethernet board was tested at LCMI in march 2008
No packet loss @ 0.53 T
Alice EMCAL meeting, 15-16 July 20089
Thermal study results(work done by Julien GIRAUD : [email protected])
• Problem: board will dissipate nearly 36 W• Assumptions:
– water flow 20°C, tube =5 mm, Q= 1l/min
– Hot component coupled with a 2 mm copper plate via a thermal foam
• hottest spot 36°C (conservative, convection neglected)
2 mm copperplate
Alice EMCAL meeting, 15-16 July 200810
Actual STU board layoutFor TRU: Dual stacked RJ45. 10 on left side, 20 on front, 10 on right side
Alice EMCAL meeting, 15-16 July 200811
Summary of the STU status• Work done so far
– LVDS Link validation (july 07)– DCS hardware modification and qualification– Thermal study– PVSS and DCS know-how gained by G. DARGAUD on Pixel trigger– Some VHDL available (deserializer, TTCrq interface)– Board layout, fabrication in progress (board received july 11th)
• To do– VHDL design:
• final VHDL• degraded versions for tests (TRU link only, limited L1-gamma, L1-jet). This
has to be defined– TRU link validation (to be discussed)– Interfaces tests and validation (DDL, V0, TTC)– PVSS driver for Emcal
Alice EMCAL meeting, 15-16 July 200812
Proposed TRU-STU link validation methodology
1. An emitting buffer is loaded via the testing tools2. A frame transfer is initiated3. The receiving buffer is read by the testing toolsAbove steps have to be repeated many times with different packet contents.
This scheme will exercise the link as in the final design.
- This is somewhat similar to the tests performed in july 2007 on the TOR board
- Has to be performed before TRU full production order (September 08??)
TRU
USB LVDS
USBSlow control
LVDS
CA
T7
LV
DS
ca
ble
1
5m
Testing tools
STU
Alice EMCAL meeting, 15-16 July 200813
SPARES
Alice EMCAL meeting, 15-16 July 200814
Available L1 processing time
t
inte
ract
ion
One
or
seve
ral T
RU
se
nds
L0 t
o S
TU
0 ns
600
ns
ST
U f
orw
ard
one
L0 t
o C
TP
700
ns
L0 f
rom
CT
P a
t R
CU
1200
ns
L1 r
ecep
tion
de
adlin
e (a
t C
TP
inpu
t)
TR
U s
tart
of
tran
smis
sio
n14
00 n
s
All
dat
a in
ST
U31
55 n
s
6100
ns
PHOS: 112*12 bit/800Mbs+75ns=1.755µsEMCAL: 96*12 bit/800Mbs+75ns=1.515µs75ns : estimated 15m of wire
L1
em
issi
on
dea
dli
ne
(at
ST
U o
uput
)59
00 n
s
200ns : estimated 40m of wirePHOS: 112*12 bit/800Mbs+75ns=1.755µsEMCAL: 96*12 bit/800Mbs+75ns=1.515µs75ns : estimated 15m of wire
Available 2745 ns (PHOS)Available 2985 ns (EMCAL)
Alice EMCAL meeting, 15-16 July 200815
L1-gamma processing (1/2)
Now the numbers are the readout orderColumn are read top to bottom and then row right to left
Refering to the previous slideDPRAM readout is 4,3,1,2,8,7,5,6,…
A r
egio
nA
+1,
R+
1 re
gion
R region
Alice EMCAL meeting, 15-16 July 200816
L1-gamma processing (2/2)
The trigger is computed for each region, with neighboring region inputs.
Requires 4 accumulators (col size) X 2 (window size)
Latency is roughly 100 X 1/120MHz~900 ns
Alice EMCAL meeting, 15-16 July 200817
L1-jet processing (1/2)
Based on P. Jacobs proposal:6 subregions are created in each region.
Row/ col
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92
1 1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93
2 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94
3 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 67 71 75 79 83 87 91 95
Numbers are the readout order and not the ADC channel number
Total: 204 subregions
Below subregion delimitation, 4x4 fast OR 8x8=64 towers
Each subregion energy sum is computed in parallel with L1-gamma
6 accumulators (no overlapping) latency ~900 ns
Alice EMCAL meeting, 15-16 July 200818
L1-jet processing (2/2)
The algorithm to apply is somewhat similar to L1-gamma except that here the columns contains 12 elements No accumulators for 1 subregion patch, direct threshold comparison12*2 accumulators for a 2X2 subregion patch12*3 accumulators for 3X3 subregion patchLatency: >204 clock cycles >1.7µs (remaining margin: 2.985-1.7-0.9=385ns)