A STAGGERED CUP IO METHODOLOGY USING ENCOUNTER

PLATFORM

Pinkesh Shah Rahul Shelke Prasan Shanbhag Gargee Das

11 October 2007

AMMOS 2007

Agenda

! Introduction

– SoC pin count trends

! Types of IO Placement techniques

! Our Design Requirement

! Advantage of CUP IO Placement

! Ammos IO Implementation flow

! Good to have Features

AMMOS 2007

Introduction! In Today's high performance SoC designs, with increase in IO

count, the IO ring design and Bond/Bump placements gets complex.

! Pad limited designs pose several challenges for design implementation and to the backend designers.

– The Solution would be to use Flip Chip or staggered I/O placement techniques.

! We will look into different IO placement techniques.

! We will focus on our Staggered CUP IO implementation using Encounter platform.

! We will not talk about– IO ring design and IO circuit design.– Packaging consideration.

AMMOS 2007

SoC Pin Count Trends

ITRS in 2001 predicted that by 2010, thousands of pins will have to be accommodated on a die for high performance chips [1]

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Types of IO Placement Technique

! IO placement types

– Inline

– Staggered

! Non-CUP

! CUP ( Circuit-Under-Pad)

– Flip Chip

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Inline IO Placement! Pads are placed next to each other, with the

corresponding bond pads lined up against each other having a small gap in between.

! Minimum pitch is determined by foundry/vendor and is technology dependent.

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Staggered (Non-CUP) IO Placement! Useful technique if design is “Pad Limited”.! Designer needs to place an inner and outer bond pad

alternately.! From the placement shown, it is obvious that a larger number

of pads can be accommodated in the design, but a big disadvantage of this type of placement is that the overall height of the pad structure increases significantly .

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Staggered CUP IO Placement! Circuit Under Pad technology violates the rule of conventional

layout and arranges the bond pad right over the pad circuitry. ! This technique ensures that no extra space is consumed on the die

and be implemented with either the in-line or staggered IO placement techniques.

! Extra care needs to be exercised while implementing this technology so as to ensure that the circuit under the bond pad does not suffer any mechanical stress which could be fatal to the chips operation.

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Flip Chip IO Placement! Flip Chip type packaging is simply a direct connection of a flipped

electrical component onto a substrate, carrier, or circuit board by means of conductive bumps instead of the conventional wire-bond.

! In the Flip chip methodology, I/O bumps and driver cells may be placed in the peripheral or core area. Note, the large octagonal area I/O bumps overlaying placed cells in the core area. No chip area benefit for small chips - Full bump array redistribution is very difficult

Fig: Encounter placement window showing Area I/O bumps [6]

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What is CUP IO?! CUP I/O is an I/O with the bonding pad over the I/O body itself. The pad

pin is located close to the center of the I/O body for easier routing, signal integrity, and space saving purposes.

! Bonding pad has to be placed over the I/O body and have it connected to the PAD pin of I/O.

! CUP I/O can substantially reduce the die size since the bonding pad does not take any extra space in addition to the I/O body itself.

Fig: Staggered Bonding Approach Using CUP I/O [5]

AMMOS 2007

Our Design Requirement! Separate Ground scheme

– With this scheme core and I/O area are separated. It reduces

the ground noise to the core area.

! SSO and ESD considerations

– Due to high switching I/O’s and ESD protection, the number of

power and ground pads increased to take extra protection.

! Constraint on Die size achievement

– With ~550k placeable cells to place, die size was the major

concern.

! Packaging Cost

! Design was Pad limited

AMMOS 2007

Advantages of CUP IO Placement

! As compared to conventional IO placement techniques, Staggered CUP IO has following advantages,– More number of IO’s as compared to Inline

– Optimal Area utilization using CUP IO placement technique, as compare to staggered non-CUP

– Lower Cost in comparison to Flip-chip package.

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Ammos IO Bond Placement flow

Modified DEF file for IO co-ordinates

Read IO location file dumped from Encounter

Calculate IO location and set the orientation

Place BOND pad on calculated locations

and orientation set

Get instance name and orientation of IO’s

Get instance name and coordinates of IO Pad

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Results Achieved! Table showing area comparison

! Area comparison of IO placement techniquesOverall Area Consumed

10091.93

46.77

0

20

40

60

80

100

120

Type of IO placement

Are

a C

onsu

med

In-lineStaggered non CUPStaggered CUP IO

100%100%100%100%Inline I/O

46.77%70%67%67%Staggered CUP I/O

91.93%137.5%67%67%Staggered non CUP I/O

Total I/O AreaHeight of each I/O

Width of total I/O

Pitch requirement

IO Type

AMMOS 2007

Good to have Feature in Encounter

! An In-Built SKILL command to place the Bond Pads as per user requirement

! verifyGeometry/verifyConnectivity to consider the IO Bond placement violations

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References

! Wood Scott; An IC Design Perspective “Why Would We Choose Flip Chip”; IEEE International Symposium for Quality Electronic Design 2003.

! Low. Q.H, Othieno Maurice, McCormick John; Bonding Copper Low K Die with Bond pads over Active Circuitry (Pads on I/O)I; 2004 IEEE/SEMI Int’l Electronics Manufacturing Technology Symposium

! Huixian Wu, Vance Archer, Sailesh Merchant, James Cargo, Daniel Chesire, Jose Antol, Rafe Mengel, John Osenbach, Steve Horvat, Carl Peridier, Marvin White; Advanced Failure Analysis of Circuit-Under-Pad (CUP) structures in Cu/FSG and Cu/low K technologies; IEEE 05CH37616 43dAnnual International Reliability Phvsics Symposium, San Jose, 2005

! http://www.freshpatents.com/Circuit-under-pad-structure-and-bonding-pad-process-dt20070531ptan20070123021.php

! Vendor PDK kit! Kevin Kelley; “Alternative flip chip methodologies in first encounter”;

International Cadence Users Group Conference 2004

AMMOS 2007

THANK YOU