Andrew Kahng – April 2002 1 A Roadmap and Vision for Physical Design ISPD-2002 April 9, 2002...

Andrew Kahng – April 2002 1

A Roadmap and Vision for Physical Design

ISPD-2002April 9, 2002

Andrew B. Kahng, UCSD CSE & ECE Departmentsemail: [email protected]: http://vlsicad.ucsd.edu


OutlineOutline

• What we need– ITRS challenges, logical/circuit/physical needs– SRC needs

• What we do– Allocation of effort, versus needs and resources– Harmful practices

• What we need to do– Coopetition– Shared red bricks

• What we need to do, II– A top-10 list


The “Red Brick Wall” - 2001 vs. 1999

Source: Semiconductor International - http://www.e-insite.net/semiconductor/index.asp?layout=article&articleId=CA187876


Roadmap Acceleration and Deceleration

Year of Production: 1999 2002 2005 2008 2011 2014

DRAM Half-Pitch [nm]: 180 130 100 70 50 35

Overlay Accuracy [nm]: 65 45 35 25 20 15

MPU Gate Length [nm]: 140 85-90 65 45 30-32 20-22

CD Control [nm]: 14 9 6 4 3 2

TOX (equivalent) [nm]: 1.9-2.5 1.5-1.9 1.0-1.5 0.8-1.2 0.6-0.8 0.5-0.6

Junction Depth [nm]: 42-70 25-43 20-33 16-26 11-19 8-13

Metal Cladding [nm]: 17 13 10 000

Inter-Metal Dielectric 3.5-4.0 2.7-3.5 1.6-2.2 1.5

2001 versus 1999

Source: A. Allan, Intel


An ITRS AnalogyAn ITRS Analogy• ITRS is like a car• Before, two drivers (husband = MPU, wife =

DRAM)• The drivers looked mostly in the rear-view mirror

(destination = “Moore’s Law”)• Many passengers in the car (ASIC, SOC, Analog,

Mobile, Low-Power, Networking/Wireless, …) wanted to go different places

• This year: – Some passengers became drivers– All drivers explain more clearly where they are going– See the new “System Drivers” Chapter of the ITRS


HP / LOP / LSTP Device RoadmapsHP / LOP / LSTP Device RoadmapsParameter Type 99 01 03 05 07 10 13 16

Vdd MPU 1.5 1.2 1.0 0.9 0.7 0.6 0.5 0.4 LOP 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 LSTP 1.3 1.2 1.2 1.2 1.1 1.0 0.9 0.9Vth (V) MPU 0.21 0.19 0.13 0.09 0.05 0.021 0.003 0.003 LOP 0.34 0.34 0.36 0.33 0.29 0.29 0.25 0.22 LSTP 0.51 0.51 0.53 0.54 0.52 0.49 0.45 0.45Ion (uA/um) MPU 1041 926 967 924 1091 1250 1492 1507 LOP 636 600 600 600 700 700 800 900 LSTP 300 300 400 400 500 500 600 800CV/I (ps) MPU 2.00 1.63 1.16 0.86 0.66 0.39 0.23 0.16 LOP 3.50 2.55 2.02 1.58 1.14 0.85 0.56 0.35 LSTP 4.21 4.61 2.96 2.51 1.81 1.43 0.91 0.57

Ioff (uA/um) MPU 0.00 0.01 0.07 0.30 1.00 3 7 10 LOP 1e-4 1e-4 1e-4 3e-4 7e-4 1e-3 3e-3 1e-2 LSTP 1e-6 1e-6 1e-6 1e-6 1e-6 3e-6 7e-6 1e-5


Silicon Complexity ChallengesSilicon Complexity Challenges• Impact of process scaling, new materials, new

device/interconnect architectures• Non-ideal scaling (leakage, power management, circuit/device

innovation, current delivery)• Coupled high-frequency devices and interconnects (signal

integrity analysis and management)• Manufacturing variability (library characterization, analog and

digital circuit performance, error-tolerant design, layout reusability, static performance verification methodology/tools)

• Scaling of global interconnect performance (communication, synchronization)

• Decreased reliability (SEU, gate insulator tunneling and breakdown, joule heating and electromigration)

• Complexity of manufacturing handoff (reticle enhancement and mask writing/inspection flow, manufacturing NRE cost)


System Complexity ChallengesSystem Complexity Challenges• Exponentially increasing transistor counts, with increased

diversity (mixed-signal SOC, …)• Reuse (hierarchical design support, heterogeneous SOC

integration, reuse of verification/test/IP)• Verification and test (specification capture, design for

verifiability, verification reuse, system-level and software verification, AMS self-test, noise-delay fault tests, test reuse)

• Cost-driven design optimization (manufacturing cost modeling and analysis, quality metrics, die-package co-optimization, …)

• Embedded software design (platform-based system design methodologies, software verification/analysis, codesign w/HW)

• Reliable implementation platforms (predictable chip implementation onto multiple fabrics, higher-level handoff)

• Design process management (team size / geog distribution, data mgmt, collaborative design, process improvement)


Big-Picture Design Technology Crises

Manufacturing

NR

E C

ost

SW Design

Verification

HW Design

TestT

urn

aro

un

d T

ime

Manufacturing

Incremental Cost Per Transistor

• 2-3X more verification engineers than designers on microprocessor teams

• Software = 80% of system development cost (and Analog design hasn’t scaled)

• Design NRE > 10’s of $M manufacturing NRE $1M

• Design TAT = months or years manufacturing TAT = weeks

• Without DFT, test cost per transistor grows exponentially relative to mfg cost

Where is the Physical

Design?


SRC Grand Challenges1. Extend CMOS to its ultimate limit2. Support continuation of Moore's Law by providing a knowledge base for CMOS

replacement devices 3. Enable Wireless/Telecomm systems by addressing technical barriers in

design, test, process, device and packaging technologies4. Create mixed-domain transistor and device interconnection technologies,

architectures, and tools for future microsystems that mitigate the limitations projected by ITRS

5. Search for radical, cost effective post NGL patterning options6. Provide low-cost environmentally benign IC processes7. Increase factory capital utilization efficiency through operational modeling8. Provide design tools and techniques which enhance design productivity

and reduce cost for correct, manufacturable and testable SOC's and SOP's9. Enable low power and low voltage solutions for mobile/battery conserving

applications through system and circuit design, test and packaging approaches.10. Enable very low cost components11. Provide tools enabling rapid implementation of new system architectures


Design?


SRC ICSS Key Technologies (Top 12) Systems

S3.2: Early Design Space Exploration

S1.2: Low Power, Real-Time Algorithms and Architectures

S4.1: On-Chip Communication

S1.3: High Bandwidth and/or Low Power Communication

S2.4: Deep Submicron Aware Microarchitectures, Accounting for Noise, Power, Timing, Interconnects, etc.

S1.1: High Level Specifications of Complex Systems

CircuitsC1.2: Digital Low Power and/or Low Voltage Circuit Design

C2.1: Mixed Signal Circuits on Advanced Technologies

C2.4: Mixed Signal Low Power and/or Low Voltage Circuit Design

C1.1: Digital Circuits on Advanced Technologies

C2.3: Mixed Signal Design for Test

C2.2: Mixed Signal Noise Immune and/or Tolerant Circuits


Design?


ITRS Logical/Physical/Circuit ChallengesITRS Logical/Physical/Circuit Challenges• Efficient and predictable implementation

• Scalable, incremental analyses and optimizations• Unified implementation/interconnect planning and

estimation/prediction• Synchronization and global signaling• Heterogeneous system composition• Links to verification and test• Reliable, predictable fabric- and application-specific silicon

implementation platforms• Cost-driven implementation flows

• Variability and design-manufacturing interface• Uncertainty of fundamental chip parameters (timing, skew,

matching) due to manufacturing and dynamic variability sources• Process modeling and characterization• Cost-effective circuit, layout and reticle enhancement to manage

manufacturing variability• Increasing atomic-scale variability effects


• Silicon complexity, non-ideal device scaling and power management

• Leakage and power management• Reliability and fault tolerance• Analysis complexity and consistent analyses / synthesis objectives• Recapture of reliability lost in manufacturing test

• Circuit design to fully exploit device technology innovation

• Support for new circuit families that address power and performance challenges

• Implementation tools for SOI• Analog synthesis• Increasing atomic-scale effects• Adaptive and self-repairing circuits• Low-power sensing and sensor interface circuits; micro-optical

devices

ITRS Logical/Physical/Circuit ChallengesITRS Logical/Physical/Circuit Challenges


SRC CADT PD Research Needs (2002 Draft)

– Placement and Routing

– Synthesis/Layout Integration

– Power Distribution and Analysis

– High Level Planning and Estimation

– Clocking Design and Analysis Above 15GHz

– Interconnect Synthesis and Analysis

– Timing Analysis and Verification

– Correct by Construction

Where are the ITRS

challenges?


OutlineOutline






Our ResourcesOur Resources• 6000 EDA R&D, worldwide (Gartner/Dataquest)• EDA tools revenue per designer has increased by

3.9% per year over past decade• Ratio of design value over design effort is perceived

to decrease as level of abstraction moves downward from behavior to layout

• PD is at most one-sixth (by market size, or by headcount) of EDA and design technology

• 150-200 ISPD attendees, ~60 DAC/ICCAD/ISPD papers in PD domain, per year


Research Funding Gap Study• C. Nuese, SRC• Research needs

– Time frame 2008+ (50-, 35-, and 22-nm nodes in ITRS)– Assessed by SRC Science Area Directors (131 total tasks)

• Research funding– 2001 used for all data– U.S., Europe, Japan and Asia-Pacific – Assumed % of R&D (or % of Sales)

Semiconductor Industry: U.S. & Foreign

Equipment, Materials & EDA Suppliers

Industry

U.S. Gov’t• NSF• DARPA• DoD S&T• DoE

Foreign Gov’ts• MEDEA+• 6th Framework• LETI• IMEC• ASUKA• MIRAI• SELETE• STARC

Government

Source: C. Nuese / SRC


Funding Modelas % of as % ofSales R&D

By Semiconductor Industry 0.24% 2.0%By Semi Equipment Suppliers 0.06% 0.5%By Semi Material Suppliers 0.00% 0.2%

By EDA suppliers 0.11% 0.5%

Redundancy in WW Research Funding % Redund

(Due to uncoordinated project funding between different regions of the world)

Lack of WW Research "Accessibility" % Accessible

of Asian results to U.S. researchers 40%of European results to U.S. researchers 70%

of U.S. results to Asian researchers 70%of European results to Asian researchers 70%

of U.S. results to European researchers 80%of Asian results to European researchers 50%

Industry funding for ITRS nodes

30%

-16.7%Forecast Change in Semiconductor Sales between

year 2000 & 2001 (in %)



Research Funding Gap Results

1005Factory Integr305ES&H

16820Ckt Des & Sys Arch28026Design CAD15313Interconnects24525Patterning28015Proc Integr, Dev & Struct15022Front-end Processing

Funds ($M)

#TasksScience Area

(~ 0.8% of sales)

Research Needs

1,406131

1005Factory Integr

305ES&H

16820Ckt Des & Sys Arch

28026Design CAD

15313Interconnects

24525Patterning

28015Proc Integr, Dev & Struct

15022Front-end Processing

Funds ($ M)

#TasksScience Area

(~ 0.8% of sales)

Research Needs

1,406131

2001

Industry Funding

IndustrySales

($B)R&D ($B) LT ITRS

($M)

Semiconductors 170 21 413

Equip Suppliers 35 4 22

Mat’rl Suppliers 26 1 3

EDA Suppliers 4 1 4

Total

U.S. $ 224M

Europe $ 47M

Japan $ 171M

2001 Indust

ry Fundi

ng

IndustrySales

($B)R&D ($B)

LT ITRS ($M)

Semiconductors 170 21413

Equip Suppliers 35 422

Mat’rl Suppliers 26 13

EDA Suppliers 4 14

Total

Totals41Nanotechnology8Engr Res Centers5Comp & Info Sciences1Electronics

NSF30Misc

DoE6Microelectronics

45Nanotechnology10Misc

DUSD (S&T)3Defense Sciences Office

18Info Tech Office88Microsystems Tech Office

DARPA

LT ITRS Funds ($M)Agency/Program

$254M

U.S. Gov’t Funding

U.S. Gov’t Funding

Agency/ProgramLT ITRS

Funds ($M)

DARPA

Microsystems Tech Office 88

Info Tech Office18

Defense Sciences Office 3

DUSD (S&T)

Misc10

Nanotechnology45

Microelectronics6

DoEMisc

30NSF

Electronics1

Comp & Info Sciences5

Engr Res Centers8

Nanotechnology41

Totals

Foreign Government Funding

Program

Amount ($M)

Program

198Total

25Other

55IMEC, LETI, Fraunhofer

23MEDEA-Plus

95European Community 6th Framework

Amount ($M)

Program

96Total

14MARAI

31SELETE (next phase)

21STARC (next phase)

30Sub-0.1 micron Project

Amount ($M)

Program

Japan & Asia-PacificEurope

Foreign Government Funding

Foreign redundancy and inaccessibility significantly increase size of effective research gap.

$1,406M

$442M

$548M

$990M

$416M

Summary

WW RESEARCH GAP

Total Research Funding

Total Government96Japan & Asia-Pac

198Europe254U.S.

GovernmentTotal Industry

4EDA Suppliers3Materials Suppliers

22Equipment Suppliers413Semiconductor Mfg

IndustryRESEARCH FUNDING

Total Science Areas

RESEARCH NEEDS

$M



Anatomy of ITRS PD NeedsAnatomy of ITRS PD Needs

• Analog layout synthesis and reuse• Layout-BIST synergies for UDSM fault models• New paradigms for global signaling, synchronization

and system-level interconnect• Modeling and simulation• Mitigation of increased process variability and non-

recurring costs in mask and foundry flows

• Multi-(Vdd, Vt, tox, biasing) performance optimization

• …


Anatomy of Recent PD LiteratureAnatomy of Recent PD Literature• (1) placement / partitioning• (2) routing / global routing / wireplanning• (3) interconnect tree (buffered / Steiner / RAT / …) construction• (4) floorplanning / block packing / macro-cell placement• (5) performance optimization (sizing, etc.)• (6) RTL-down methodology / flow• (7) clock• (8) power• (9) custom layout (transistor-level / migration / compaction)• (10) analog• (11) manufacturability / yield• (12) logical-physical interactions• (13) signal integrity• Table: DAC (Y) / ICCAD (Y) / ISPD (Y+1), in Y = 1996, …, 2001


Distribution of Physical Design Papers Among 13 Topics

0

10

20

30

40

50

60

70

80

1996 1997 1998 1999 2000 2001

SIL-PMfgAnaFCVDDClkFloPOFPIntRTP/P

Where are the ITRS

challenges?


Dissimilarity by Compression File .gz +97.gz +02.gz 97 02

ABK 665 2008 1985 0.937 0.939

CADT 187 1525 1498 0.934 0.933

ICSS 352 1685 1660 0.930 0.931

L/P/C 793 2118 2066 0.925 0.906

Si/Sys 814 2143 2104 0.927 0.918

Strat 620 1941 1911 0.922 0.919

• ((ISPD97 + CADT).gz – CADT.gz) / ISPD97.gz

• ((ISPD97 + ISPD02).gz – ISPD02.gz) / ISPD97.gz = 0.78


OutlineOutline






What Is Going On Here?What Is Going On Here?• Three pernicious phenomena

– (1) Long lead times and latencies: formulation to solution to technology transfer to marketplace …

– (2) High startup costs and other barriers to entry in research– (3) Research field recreates itself in its own image


It’s It’s NotNot A Moving Target A Moving Target• PD roadmap has been static

– Convergent integration of logic, timing, spatial embedding– Unification of incremental timing/SI closure with PA

backplane– Methodology and routing contexts

• Some references– NTRS/ITRS since 1994– 1995 Sematech CHDS specification– L. Scheffer, PDW96: “We’re Solving the Wrong Problems”– Other examples listed in paper


Hello? Hello?


Hello??


Too Much Back-Filling?Too Much Back-Filling?• Practice of putting well-known and already

commercialized techniques into the public literature– Some impact on IP and research efficiency, but only if there

is adequate transfer of the resulting technology!

• Standard planning framework, next-generation detailed routers, etc. are better left to industry

• Academia would benefit from more industry-strength shared research infrastructures


What Should Be Novel in Research?What Should Be Novel in Research?• Novelty in formulation, or novelty in optimization?• Claim: PD is focusing more on “novel” problem

statements, while only transferring or reusing core optimization techniques– 15+ years ago: PD was the source of simulated annealing,

LP relaxation/rounding, hierarchical routing, etc.– Past decade: mostly transferring methods (e.g., multilevel

(PDW96, DAC97))

• Again: “We’re solving the wrong problems”– Cf. “packing obsession” in floorplanning literature– Shortage of optimization tools– No shortage of problems


OutlineOutline



• What we need to do– Mindset Change #1: Coopetition– Mindset Change #2: Shared red bricks



Vision: Improved Design Technology Productivity

• MARCO GSRC Calibrating Achievable Design theme• http://vlsicad.ucsd.edu/GSRC/

• Improved design technology planning (“specify”): • What will the design problem look like? What do we need to solve?

• Improved execution (“develop”): • How can we quickly (TTM) develop the right design technology (QOR)?• Reusable, commodity, foundation CAD-IP (+ new publication standards)

• Improved measurement (“measure and improve” ):• Did we solve the problem (QOR)? Did the design process improve? Did we

increase the envelope of achievable design?• Design tool/process metrics, design process instrumentation and continuous process

improvement

• Ethos of “coopetition” (cooperation among competitors)


““Living ITRS” FrameworkLiving ITRS” Framework


CAD-IP Reuse

• Rapid development and evaluation of fundamental algorithm technology, via CAD-IP reuse

• CAD-IP = Data models and benchmarks– context descriptions and use models– testcases and good solutions

• CAD-IP = Algorithms and algorithm analyses– mathematical formulations– comparison and evaluation methodologies for algorithms – executables and source code of implementations– leading-edge performance results

• CAD-IP = Traditional (paper-based) publications


MARCO GSRC Bookshelf: A Repository for CAD-IP

• New element of VLSI CAD culture– “Community memory” currently centered in back-end

• data models, algorithms, implementations• repository for open-source “foundation CAD-IP”

– Publication medium that supports efficient CAD R&D• benchmarks, performance results• algorithm descriptions and analyses• quality implementations (e.g., open-source UCLA PDTools)

• Enables comparisons to identify best approaches• Enables communication by industry of use models,

problem formulations• http://gigascale.org/bookshelf/• Have you open-sourced your code in the Bookshelf?


OutlineOutline



• What we need to do– Mindset Change #1: Coopetition– Mindset Change #2: Shared red bricks



What Is A “Red Brick” ?What Is A “Red Brick” ?• Red Brick = ITRS Technology Requirement with

no known solution

• Alternate definition: Red Brick = something that REQUIRES billions of dollars in R&D investment


Another ITRS AnalogyAnother ITRS Analogy• ITRS technologies are like parts of the car

• Every one takes the “engine” point of view when it defines its requirements– “Why, you may take the most gallant sailor, the most intrepid airman, the

most audacious soldier, put them at a table together – what do you get? The sum of their fears.” - Winston Churchill

• All parts must work together to make the car go smoothly

• Need global optimization of resource allocations with respect to requirements shared red bricks


““Design-Manufacturing Integration”Design-Manufacturing Integration”

• 2001 ITRS Design Chapter: “Manufacturing Integration” = one of five Cross-Cutting Challenges

• Goal: share red bricks with other ITRS technologies– Lithography CD variability requirement new Design

techniques that can better handle variability

– Mask data volume requirement solved by Design-Mfg interfaces and flows that pass functional requirements, verification knowledge to mask writing and inspection

– ATE cost and speed red bricks solved by DFT, BIST/BOST techniques for high-speed I/O, signal integrity, analog/MS

– Does “X initiative” have as much impact as copper?


YEAR

TECHNOLOGY NODE

2001 2002 2003 2004 2005 2006 2007

DRAM ½ PITCH (nm) (SC. 2.0) 130 115 100 90 80 70 65

MPU/ASIC ½ PITCH (nm) (SC. 3.7) 150 130 107 90 80 70 65

MPU PRINTED GATE LENGTH (nm) (SC. 3.7) 90 75 65 53 45 40 35

MPU PHYSICAL GATE LENGTH (nm) (SC. 3.7) 65 53 45 37 32 28 25

Conductor effective resistivity(-cm) Cu intermediate wiring*

2.2 2.2 2.2 2.2 2.2 2.2 2.2

Barrier/cladding thickness(for Cu intermediate wiring) (nm)

18 15 13 11 10 9 8

Interlevel metal insulator—effective dielectric constant ()

3.0-3.7 3.0–3.7 2.9–3.5 2.5–3.0 2.5–3.0 2.5–3.0 2.0–2.5

Interlevel metal insulator (minimumexpected)—bulk dielectric constant ()

2.7 2.7 2.7 2.2 2.2 2.2 1.7

Example Red Brick: Dielectric Permittivity

Bulk and effective dielectric constants

Porous low-k requires alternative planarization solutions

Cu at all nodes - conformal barriersC. Case, BOC Edwards – ITRS-2001

Do we really

need this?


Cu Resistivity vs. Linewidth WITHOUT Cu Barrier

1.5

1.6

1.7

1.8

1.9

2

2.1

2.2

2.3

2.4

2.5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Line Width (um)

Res

isti

vity

(u

oh

m-c

m)

70nm ITRS RequirementWITH Cu Barrier

100nm ITRS RequirementWITH Cu Barrier

Courtesy of SEMATECH

Conductor resistivity increasesexpected to appear around 100 nm linewidth -will impact intermediate wiring first - ~ 2006

C. Case, BOC Edwards – ITRS-2001

Example Red Brick: Copper Resistivity

Is this even possible?


PD + PIDS (Devices/Structures)PD + PIDS (Devices/Structures)

• CV/I trend (17% per year improvement) = “constraint”• Huge increase in subthreshold Ioff

– Room temperature: increases from 0.01 uA/um in 2001 to 10 uA/um at end of ITRS (22nm node)

• At operating temperatures (100 – 125 deg C), increase by 15 - 40x

– Standby power challenge• Manage multi-Vt, multi-Vdd, multi-Tox in same core• Aggressive substrate biasing• Constant-throughput power minimization• Modeling and controls passed to operating system and applications

• Aggressive reduction of Tox– Physical Tox thickness < 1.4nm (down to 1.0nm) starting in

2001, even if high-k gate dielectrics arrive in 2004– Variability challenge: “10%” < one atomic monolayer


PD + LithographyPD + Lithography• 10% CD uniformity is a red brick today• 10% < 1 atomic monolayer at end of ITRS• This year: Lithography, PIDS, FEP agreed to raise CD

uniformity requirement to 15% (but still a red brick)• Design for variability

– Novel circuit topologies– Circuit optimization (conflict between slack minimization and

guardbanding of quadratically increasing delay sensitivity)– Centering and design for $/wafer

• Design for when devices, interconnects no longer 100% guaranteed correct?– Potentially huge savings in manufacturing, verification, test

costs


PD + Assembly and PackagingPD + Assembly and Packaging• Goal: cost control ($0.07/pin, $2 package, …)• “Grand Challenge” for A&P: work with Design to

develop die-package co-analysis, co-optimization tools• Bump/pad counts scale with chip area only

– Effective bump pitch roughly constant at 300um – MPU pad counts flat from 2001-2005, but chip current draw increases 64%

• IR drop control challenge– Metal requirements explode with Ichip and wiring resistance

• Power challenge– 50 W/cm2 limit for forced-air cooling; MPU area becomes flat because

power budget is flat– More control (e.g., dynamic frequency and supply scaling) given to OS and

application– Long-term: Peltier-type thermoelectric cooling, …


PD + Manufacturing TestPD + Manufacturing Test• High-speed interfaces (networking, memory I/O)

– Frequencies on same scale as overall tester timing accuracy

• Heterogeneous SOC design– Test reuse– Integration of distinct test technologies within single device– Analog/mixed-signal test

• Reliability screens failing– Burn-in screening not practical with lower Vdd, higher power

budgets overkill impact on yield

• Design challenges: DFT, BIST PD IS in the loop!– Analog/mixed-signal– Signal integrity and advanced fault models– BIST for single-event upsets (in logic as well as memory)– Reliability-related fault tolerance


How to Share Red BricksHow to Share Red Bricks• Cost is the biggest missing link within the ITRS

– Manufacturing cost (silicon cost per transistor)– Manufacturing NRE cost (mask, probe card, …)– Design NRE cost (engineers, tools, integration, …)– Test cost– Technology development cost who should solve a given

red brick wall?

• Return On Investment (ROI) = Value / Cost– Value needs to be defined (“design quality”, “time-to-market”)

• Understanding cost and ROI allows sensible sharing of red bricks across industries

• PD is at the heart of these potential partnerships• PD is in the best position to share R&D investment!


OutlineOutline






A Top-10 ListA Top-10 List• (0) Sensible unifications to co-optimize global signaling,

manufacturability enhancement, and clock/test/power distribution

• (1) Fundamental new combinatorial optimization technologies (and possibly geometry engines) for future constraint-dominated layout regimes

• (2) New decomposition schemes for physical design• (3) Global routing that is truly path-timing aware, truly

combinatorial, and able to invoke “atomistic” interconnect synthesis

• (4) In-context layout synthesis that maximizes process window while meeting electrical (functional) spec


A Top-10 ListA Top-10 List

• (5) Efficient analog and mixed-signal layout synthesis• (6) Methods for synchronization and global signaling at

multi-GHz or –Gbps, extending to system-level• (7) Analysis, modeling and simulation methods that are

tied more closely to PD syntheses, and that adapt to resource and accuracy and fidelity constraints

• (8) Revival of platform-specific (parallel, distributed, hardware-accelerated) algorithm implementations

• (9) Mindset changes, including a culture of “duplicating, deconstructing and debunking”


ConclusionsConclusions• PD roadmap is static and well-known• There is a mismatch with semiconductor industry needs,

and basic problems remain untouched• We in academia should not overemphasize back-filling

and formulation over innovation and optimization• As a community, we must become more mature and

efficient in how we prioritize research directions and use our human resources

• The scope of PD must expand: up, down, out, back – even as renewed focus is placed on basic optimization technology

• PD is at the heart of shared red bricks – we should and must seize this opportunity for new R&D investment


Thank you !


Analogy #1Analogy #1• ITRS is like a car• Before, two drivers (husband = MPU, wife =

DRAM)• The drivers looked mostly in the rear-view mirror

(destination = “Moore’s Law”)• Many passengers in the car (ASIC, SOC, Analog,

Mobile, Low-Power, Networking/Wireless, …) wanted to go different places

• This year: – Some passengers became drivers– All drivers explain more clearly where they are going


Design Chapter OutlineDesign Chapter Outline• Introduction

– Scope of design technology– Complexities (silicon, system)

• Design Cross-Cutting Challenges– Productivity– Power– Manufacturing Integration– Interference– Error-Tolerance

• Details given w.r.t. five traditional technology areas– Design Process, System-Level, Logical/Physical/Circuit,

Functional Verification, Test– Each area: table of challenges + mapping to driver classes


2001 Big Picture2001 Big Picture• Message: Cost of Design threatens continuation of the

semiconductor roadmap– New Design cost model– Challenges are now Crises

• Strengthen bridge between semiconductors and applications, software, architectures– Frequency and bits are not the same as efficiency and utility– New System Drivers chapter, with productivity and power foci

• Strengthen bridges between ITRS technologies– Are there synergies that “share red bricks” more cost-

effectively than independent technological advances?– “Manufacturing Integration” cross-cutting challenge– “Living ITRS” framework to promote consistency validation


Design Cost ModelDesign Cost Model• Engineer cost per year increases 5% / year ($181,568 in 1990)

• EDA tool cost per year (per engineer) increases 3.9% per year ($99,301 in 1990)

• Productivity due to 8 major Design Technology innovations (3.5 of which are still unavailable) : RTL methodology; In-house P&R; Tall-thin engineer; Small-block reuse; Large-block reuse; IC implementation suite; Intelligent testbench; Electronic System-level methodology

• Matched up against SOC-LP PDA content:– SOC-LP PDA design cost = $15M in 2001

– Would have been $342M without EDA innovations and the resulting improvements in design productivity


SOC Design Cost Model

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Design Cost of SOC-LP PDA Driver


Methodology Basic Precepts• Exploit reuse• Evolve rapidly

– Analyses and simulation models and verifications objectives and constraints for synthesis and optimization

– Bottom-up commoditization (e.g., analyses, physical layout / verification)

• Avoid iteration• Replace verification by prevention• Improve predictability• Orthogonalize concerns

– Behavior from architecture; timing from layout; …

• Expand scope, and unify– E.g., down to manufacturing, up to package/system


Future Design System Architecture Required Advance in Design System Architecture

Tomorrow 50 nm

Functional Performance

Testability Verification

SPEC

Perf Timing Power Noise Test Mfg

.

Cost Repository

HW/SW/Mfg Data Model

Analyze Comm.

Cockpit Auto-Pilot

MASKS

System Design System

Model

Today 130 nm

Perf Model

System Design System

Model

File

Logic Synthesis + Timing Analysis + Placement Opt

Placement + Timing Analysis

+ Logic Opt

SW Opt

Performance Testability

Verification

Functional Verification

File MASKS

SW E

qu

iva

len

ce

ch

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ing

HW / SW Optimization

RTL

• Verification moves to higher levels, followed in lower levels by equivalence checking and assertion driven optimizations

• Design optimized over many constraints with tightly integrated analyses and syntheses (optimizations)

• Integration through modular open architecture with industry standard interface for data control

• Shared data in memory to eliminate disk accesses in critical loops with common data for cooperating applications

• Incremental specification, synthesis (optimization) and analysis

other

HW/SW SW Logic

Circuit Embedding Interconnect other

Optimize

EQ

ch

eck

Timing


Analogy #2Analogy #2• ITRS technologies are like parts of the car• Every one takes the “engine” point of view when

it defines its requirements– “Why, you may take the most gallant sailor, the most intrepid airman, the

most audacious soldier, put them at a table together – what do you get? The sum of their fears.” - Winston Churchill

• All parts must work together to make the car go smoothly

• (Design = Steering wheel and/or tires … but has never “squeaked” loudly enough)

• Need “global optimization” of requirements


FO4 INV Delays Per Clock Period

• FO4 INV = inverter driving 4 identical inverters (no interconnect)• Half of freq improvement has been from reduced logic stages


Roadmap Changes Since 2000Roadmap Changes Since 2000

• Next “node” = 0.7x half-pitch or minimum feature size– 2x transistors on the same size die

• 90nm node in 2004 (100nm in 2003)– 90nm node physical gate length = 45nm

• MPU/ASIC half-pitch = DRAM half-pitch in 2004– Previous ITRS (2000): convergence in 2015

• Psychology: everyone must beat the Roadmap– Reasons: density, cost reduction, competitive position– TSMC CL010G logic/mixed-signal SOC process: risk

production in 4Q02 with multi-Vt, multi-oxide, embedded DRAM and flash, low standby power derivatives, …


Problem Statements V• Pass functional intent down to OPC insertion

– OPC insertion is for predictable circuit performance, function

– Problem: make only corrections that win $$$, reduce perf variation (i.e., link to performance analysis, optimizations and sensitivities)

• Pass limits of mask verification up to layout– Problem: avoid making corrections that can’t be

manufactured or verified

• // I.e., 2-way fat pipe between process and design !– SPICE models are not a sufficient process abstraction…


Problem Statements VI• Minimize data volume

– Problem: make corrections that win $$$, reduce perf variation up to some limit of data volume for resulting layout (== mask complexity, cost)

• Layout needs models of OPC insertion process– Problem: taxonomize implications of layout geometry on

cost of the OPC that is required to yield function or “faithfully” print the geometry

– find a realistic cost model for breaking hierarchy (including verification, characterization costs)


Other Oldies But Goodies• Constraint-dominated and cost-driven layout

• Good practices (no doglegs, no Ts, even fingering…)• Constrained orientations (no 45s, one direction only)• Constrained pitches (forbidden gap rules)• Halation (width-dependent spacing) rules• Electrically correct, manufacturing cost-aware detailed routing

• Auto-P&R productivity• Guaranteed composability is foundation of standard-cell productivity• Library generation must support PSM layout composability• Layout on the fly (liquid library cells for performance, yield)


Other Oldies But Goodies• Sane RCX / PA flow with respect to area fill

• Area fill breaks RCX extraction• Must be modeled / predicted at timing / signal integrity signoff during auto-

P&R• Tradeoffs and correct models (grounded vs. ungrounded; synergies

between fill and printability (as opposed to planarization) must be understood

• PSM, OPC (?) and Fill must be owned by physical design, not physical verification

• PV tools have Boolean, purely geometric infrastructure• PV tools report errors (e.g., phase conflict), but are not empowered to fix

(e.g., shift/compact layout

• Miscellaneous• Hierarchy, data volume, reuse concerns• New tool integrations: compaction, on-the-fly cell synthesis, incremental

detailed routing, graph-based (verification-type) layout analyses, performance and logic optimizations


Cost of Manufacturing Test

Is this better solved with Automated Test Equipment technology, or with Design (for Test, Built-In Self-Test) ?

Is this even solvable with ATE technology alone?

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Andrew Kahng – April 2002 1 A Roadmap and Vision for Physical Design ISPD-2002 April 9, 2002...

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