ATA6824 and ATmega88
Application Note
9102A–AUTO–08/07
ATA6824 and ATmega88:DC Motor Control in High Temperature
Environment
1. IntroductionThe purpose of this document is to explain Atmel®’s High Temperature H-bridge MotorControl System. The demand for driver solutions in “under-the-hood” environments israpidly increasing, and in particular, the use of applications such as turbo chargers,EGR, or AGR calls for new solutions.
Figure 1-1. ATA6824 and ATmega88
2. H-bridge Motor Control System
Figure 2-1. Fully Integrated H-bridge Motor Control Application
The system consists of two integrated circuits: the microcontroller ATmega88 and the H-bridgeDC Motor Driver ATA6824.
The ATA6824 uses gate drivers to drive H-bridge FETs, voltage regulator, watchdog, and serialIO interface. An integrated charge pump controls the NMOS FETs for low-side and high-sideswitches. In addition, the charge pump voltage is capable of providing a low-drop inverse volt-age protection. Therefore, only a NMOS FET in the source drain direction is necessary.
The ATA6824 switches the outputs off in the event of short circuits, voltage failures, and over-temperature. Temperature prewarning and charge pump failures are also indicated. Theschematic has a current shunt, which can react at different current levels. The current signal isprepared for the microcontroller by an amplifier.
The ATmega88 generates the PWM speed signal to run various movement profiles as requiredfor the load.
SIO WD Timer
CC Timer
Gate Driver Low Side 2
Gate Driver Low Side 1
Gate Driver High Side 1
Gate Driver High Side 2
CP13V
Regulator
3.3V/5V VCC Regulator
Supervisor: Short Circuit Open Load
Over Temperature Under Voltage
Logic Control
ATA6824PCINT
Interrupt Pins
PWM Timer
I/Os
UART Input
Capture
ADC + Analog
Comparator
AVR ATmega88 VCC
DG1
DG2DG3
PWM
DIR
WD
/RESET
RX
TX
SIO
SIO RWD CC GNDPGND
L2
L1
S1
H1
S2
H2
VBAT
3.3V/5V VCC Regulator
VMODE VINT VG CPLO CPHI VRES PBAT
VBAT
+-
M
29102A–AUTO–08/07
ATA6824 and ATmega88
ATA6824 and ATmega88
2.1 Cooling Area DesignThe driver IC ATA6824 is housed in a QFN package. QFN packages are particularly suitable forpower applications because of the exposed die pad. To make use of this advantage, the heatslug must be completely soldered to the PCB.
To reduce thermal resistance, vias etched down to the soldering layer are required. An adequateground plane must be placed on the soldering layer to eliminate the thermal energy.
A via diameter of 0.3 mm to 0.4 mm with a spacing of 1 mm to 1.5 mm has proven to be mostsuitable. Care should be taken of the copper area's planarity to avoid, in particular, any solderbumps arising at the thermal vias.
3. High Ambient TemperatureThe application is designed for high temperature environments. The ATmega88 and the driverATA6824 are qualified up to an ambient temperature of 150°C. Under thermal overload condi-tions, the ATA6824 switches off. If the temperature exceeds the prewarning threshold, themicrocontroller can reduce the output power.
Capacitance material on X8R quality is necessary to ensure high ambient temperatures.
Mounted connectors, a switch, and a potentiometer on the board, enable prototyping; however,these components are not qualified for use under high temperatures. The board can be inte-grated into high-temperature environments using wires.
4. The Application BoardThe application board is run-capable when connected to nominal 12V at the battery connector(see Figure 4-1 on page 4). The board can be connected to the automotive environment over anSIO bus.
A mounted switch (DIR) for run/stop, clockwise, and counterclockwise and a a potentiometer(SPEED) for variable speed (PWM) input are available on the application board to enablestand-alone prototyping.
An optional feedback loop from the DC motor to the ATmega88 can be established using Hallsensor(s). The two Hall inputs can be linked to the connector HALL as well as the 5V supply forthe Hall sensors. There is also an on-board shunt current sensor to detect over-currents (usingATmega88’s analog comparator) and to measure motor current.
4.1 On Board FeaturesThe application board provides the following features:
• ATmega88 QFN32
– MCU
• ATA6824 QFN
– 5V/3.3V voltage regulator (fixed on-board to 5V)
– Low drop voltage protection management
– H-bridge driver with diagnostics
– Serial link transceiver to connect board to external environment
– Watchdog
39102A–AUTO–08/07
• On-Off-On switch
– Stand-alone commands interface: Run/stop, clockwise, and counterclockwise
• Potentiometer
– Standalone speed variation command (PWM ratio)
• System clock
– MCU internal RC oscillator
• Power H-bridge (4 power FET)
• Human interface
– Diagnostics signaling/latching through LED and unlatching through push button
• Connectors
– Power supply (battery voltage) and SIO
– DC motor connector
– Hall sensor inputs and supply (2 filtered inputs and 5V regulated supply voltage)
– SP/debugWire connector, for on-chip in-situ programming (ISP) and for on-chip debugging using JTAG ICE supported by AVR Studio® interface(1)
• Dimensions: 45 mm × 90 mm
Note: 1. The ATmega88 is supported by AVR Studio, version 4.12 or higher. For up-to-date information on this and other AVR® tool products, please consult our web site. The newest version of AVR Studio, AVR tools, and user guide can be found in the AVR section of the Atmel web site, http://www.atmel.com
Figure 4-1. Application Board Top View, and Connector Usage
Motor Out 1
Motor Out 2
PGND
SIO
Vbat
CWStopCCW
Speed
1 23 45 6
JP1
ISP MK2 Header
MISOSCK
NRES
MOSI
VCC 5V
GND
49102A–AUTO–08/07
ATA6824 and ATmega88
ATA6824 and ATmega88
5. Software DescriptionAll code is implemented in C language. Source code can be compiled using IAR® EWAVR 4.20Aas well as AVR-GCC (WinAVR-20060421 with AVR Studio).
HTML documentation is included in the package. Use the High_temp_brushed_DC.html file inthe root directory to start viewing the documentation.
5.1 Motor Management• Motor stopped
– PWM ratio is set to zero
– Command switch inputs are monitored to start motor or keep it stopped.
• Motor running
– ATA6824 DIR pin is set according to command direction. PWM ratio is refreshed constantly according to speed of the potentiometer ADC input.
– Command switch inputs are monitored to stop motor or keep it stopped.
• Degraded “mode”:
– ATA6824 detects a short circuit: H-bridge short-circuited and FET is switched off until next PWM rising edge. This default is reported to software through a diagnostic feature: an interrupt occurs on DG1 MCU input pin, which internally latches a failure. Apart from switching on the DG1 LED, no action is taken by the software in response to this event. In a customer application, this should be managed, eventually by the interrupt sub-routine, especially in case of a 100% PWM ratio where no rising edge appears at the ATA6824 PWM input to make a retry. Care should be taken in motor transient state (e.g. motor start-up). An accelerating curve is preferable from 0% to 100% PWM ratio transition, which may be mistaken for a short-circuit condition. Without management, in the worst case scenario, the motor will not start as the outputs are switched off, and short circuit will be shown on DG1 pin.
– ATA6824 detects an over-temperature warning: an interrupt occurs on the MCU. This diagnostic doesn’t need to be software latched as it remains high until the temperature decreases. The application software toggles an LED.
– ATA6824 detects an under-voltage, an over-voltage, or a charge pump failure. Then, an interrupt occurs on DG2 MCU input PIN. This diagnostic is latched by software and an LED is switched on.
– An over-current is detected by the analog comparator. An interrupt is generated. The output PWM is then disabled until the current decreases bellow the over-current limit.
5.2 Resources
Table 5-1. Code, Data, and CPU Resources (without Compiler Optimizations)
Compiler/Resources Code Size (Flash) Data Size (Ram) CPU Load
IAR EWAVR 4.20A 1 180 bytes 335 bytesAll routines are
constantly executed in main loop
AVR-GCC 1724 bytes 15 bytes
59102A–AUTO–08/07
The following MCU peripherals are used:
• Timer 0
– PWM generation through output compare 0B (OC0B pin)
• ADC channels 0, 6, and 7
– Resp. current, battery supply voltage and desired speed (potentiometer) value acquisitions.
• Pin change interrupts
– DG1, DG2 and DG3 diagnostic pins interrupts
– Optional hall sensors
• Analog comparator
– Generates over-current interrupts
• I/O
– LEDs, switch and push-button operations, watchdog trigger, motor direction command
• Additional (not managed by this stand-alone software)
– UART for SIO implementation (communication through high-voltage serial interface).
5.3 Caution about ATmega88 Start-up Time (Fuse Configuration)ATA6824 uses a windowed watchdog, which can reset the ATmega88 using the reset pin.
• ATmega88 is configured by default (fuse configuration) with a start-up time of 65 ms after a power-on reset. With tolerances, this value can increase up to 69 ms.
• ATA6824 waits for a watchdog trigger within 68 ms after the reset signal has been released.
Such an additional 65 ms delay is unnecessary and could cause the application not to start.ATA6824 ensures an adequate VCC through its power-on delay. ATmega88 default fuse config-uration should be over-written with a smaller start-up time. The start-up time can be set to4.1 ms or 0 ms. The start-up settings in the fuse configuration can be changed by setting theSUTx and CKSELx fuse bits. Further details about fuses can be found in ATmega88 datasheetand in the AVR Studio Help: AVR Tools user’s guide.
69102A–AUTO–08/07
ATA6824 and ATmega88
ATA6824 and ATmega88
Figure 5-1. ATmega88 Fuse Configuration Editing in AVR Studio
79102A–AUTO–08/07
5.4 Diagrams
Figure 5-2. Flowchart for Analog Comparator (Over-current) ISR
Figure 5-3. Flowchart for Optional Hall Sensors ISR
Figure 5-4. Flowchart for Diagnostic Interrupt Pins
YN
Over-current ISR (Analog Comparator ISR)
Current Over Limit?
Latch Over Current
Report Over Current
Disable Output PWM
Clear Over-current Report
Re-enable Output PWM
Pin Change Interrupt 0 (Hall Sensor ISR)
Optional Code Can Be Put in it
Y
Pin Change Interrupt 1 (Diagnostic 1, 2 and 3 ISR
DG1 set? Latch DG1 Failure
DG2 set?
DG3 set?
Clear DG3 Warning
Latch DG2 Failure
Report DG3 Warning
Y
Y
N
N
N
89102A–AUTO–08/07
ATA6824 and ATmega88
ATA6824 and ATmega88
Figure 5-5. Main Loop Flowchart
5.5 Modulesvoid ADC_Init(); (void)
Sets up ADC to acquire desired speed from potentiometer.
void Timer0_start(void)
Configures timer 1 for PWM on Output compare 0 B pin.
void AN_compare_init(void)
Configures Analog comparator to detect over-currents by interrupts.
void Hall_sensors_ISR_init(void)
Sets up pin change interrupts on hall sensors inputs.
void Diag_inputs_ISR_init(void)
Sets up interrupts on Diagnostic pins.
void ADC_task(void)
Schedules ADC acquisitions: desired speed, Vbat, and Motor current. It is called in background(main loop).
unsigned int adc_get_speed(void)
Returns last acquired desired speed from potentiometer.
unsigned int adc_get_current(void)
Returns last acquired motor current.
unsigned int adc_get_V_bat(void)
Returns last acquired supply voltage measurement.
void manage_time_base(void)
Main Loop (Background)
ADC Scheduler
Time Base Management
Watchdog Refresh Task
Motor Management
Diagnostic Display on LED
Initialize I/O, ATA6824 WD, ADC, Hall Sensors ISR, Diagnostic ISR, Timer0-PWM
99102A–AUTO–08/07
Manages a general purpose time base by monitoring Timer0 overflows (used by watchdogrefresh routine, LED toggling…).
void refresh_ATA6824_watchdog(void)
Refreshes ATA6824 according to hardware fixed period and software time base. It is called inbackground (main loop).
void clear_faults(void)
Clears software latched faults (from diagnostics pins) only when they have disappeared.
TIMER0_SET_OC0B_PWM (val)
This macro changes PWM ratio.
DISABLE_OCB0()
This macro disables PWM output by changing pin multiplexing back to general I/O configuration.
RE_ENABLE_OCB0()
This macro enables PWM output by giving pin control to Output compare 0 B (Timer 0 PWMoutput).
109102A–AUTO–08/07
ATA6824 and ATmega88
ATA6824 and ATmega88
6. Application Board Full Description
Figure 6-1. BLDC Application Board Schematic
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87V
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5V
CC
42
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119102A–AUTO–08/07
Figure 6-2. BLDC Application Board Top View and Component Placement
Figure 6-3. BLDC Application Board Bottom View
129102A–AUTO–08/07
ATA6824 and ATmega88
9102A–AUTO–08/07
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