Course Outline

Basic Concepts in RF Design

Low-Noise Amplifiers

Mixers

Oscillators

Phase-Locked Loops

Basic Concepts

Most synthesizers emply “phase locking” to achieve high

frequency accuracy.

In its simplest form, a Phase Locked Loop (PLL) is a negative

feedback loop consisting of

“phase detector” (PD)

voltage controlled oscillator (VCO)

Phase Detector

A PD is a circuit that senses two periodic inputs and produces an outputwhose average value is proportional to the difference between the phases

of the inputs.

The input/output characteristic of the PD is ideally a straight line, with aslope called the “gain” and denoted by KPD (V/rad).

In practice, the characteristic may not be linear or even monotonic.

If the two inputs have the same frequency the phase difference is constant.

An Exclusive-OR (XOR) gate can serve this purpose. It generates pulseswhose width is equal to ∆ϕ.

The circuit produces pulses at both the rising edge and the falling edge ofthe inputs.

Phase Detector

If the two inputs have different frequencies the phase difference changeswith time

The input with a higher frequency, x2(t), accumulates phase faster thanx1(t), thereby changing the phase difference, ∆Φ.

Phase Detector

The output waveform displays a “beat” behavior having a frequencyequal to the difference between the input frequencies.

Type-I PLLs: Alignment of a VCO’s Phase

For example, to null the phase difference, we must

change the frequency of the VCO (t0).

allow the VCO to accumulate phase faster (or more slowly) than thereference so that the phase error vanishes.

change the frequency back to its initial value (t1)

Consider a VCO oscillates at the same nominal frequency of an idealreference but with a phase difference subjected to fluctuations. It isdesirable to maintain fixed the phase difference

Simple PLL and Loop Filter

In such design the phase error cannot be arbitrarily small to avoid instability

The PD produces repetitive pulses at its output, modulating the VCOfrequency and generating large sidebands.

Interpose a low-pass filter (called “loop filter”) between the PD and the VCOto suppress these pulses.

We call this circuit a “Phase-Locked Loop” (PLL).

A PD comparing the VCO phase and reference phase can be used todetermine the time at which the phase error reaches zero

Simple PLL: Phase Locking

We say the loop is “locked” if ϕout(t)-ϕin(t) is constant with time.

An important and unique consequence of phase locking is that the inputand output frequencies of the PLL are exactly equal.

The phase difference ϕout(t)-ϕin(t) depends on the frequency

Due to the finite open-loop gain a “frequency-locked loop” cannot beimplemented (fout-fin=const).

In a voltage-domain buffer, if the open-loop gain is sufficiently high, theoutput tracks the input with an offset difference.

In the same way in a PLL the phase of the output tracks the phase of theinput if the open-loop gain is high

Analysis of Simple PLLs

If the loop is locked, the input and output frequencies are equal and thephase difference is constant (static phase error). the PD generates repetitivepulses, the loop filter extracts the average level, and the VCO senses thislevel so as to operate at required frequency.

If the input frequency changes by ∆ω, how much is the change in the phase error? Assume the loop remains locked.

Such a change requires that Vcont change by ∆ω/KVCO. This in turnnecessitates a phase error change of

The phase error varies with the frequency step. To minimize this variation,KPDKVCO must be maximized.

Analysis of Simple PLLs

Response of PLL to Input Frequency Step

At t=t1, ωωωωout=ωωωωin but the phase error has not reached its final value. The looplocks only after two conditions are satisfied:

(1) ωout becomes equal to ωin

(2) the difference between ϕin and ϕout settles to its proper final value

PLL as FM demodulator

An FSK waveform is applied to a PLL

the input frequency toggles between two values and so does the outputfrequency.

the control voltage must also toggle between two values providing theoriginal bit stream.

a PLL can serve as an FSK (and, more generally, FM) demodulator if Vcont isconsidered the output.

Loop Dynamics: the Meaning of Transfer Function in Phase Domain

The transfer function of a voltage-domain circuit signifies how a sinusoidal input voltage propagates to the output.

The transfer function of a PLL must reveal how a slow or a fast change in the input (excess) phase propagates to the output (low pass filtering)

The PLL produces a well defined output frequency, rejecting accidental parameter variations.

Loop Dynamics: Phase Domain Model

The open-loop transfer function

Overall closed-loop transfer function

Since the open-loop transfer function contains one pole at the origin (dueto the VCO), this system is called “type-I PLL”.

H(s) refers to phase fluctuations not to static phase difference, i.e. for slowphase fluctuations (s≈0), H≈1, but a non-zero phase difference existsbetween input and output.

Simple PLL Stability

Lower ωωωωLPF (to suppress ripple) and/or higher KPDKVCO (to reduce staticphase error) bring to lower ξξξξ which a lower phase margin.

Example: if ξξξξ=1

loop time constant loop bandwidth

( ) ( ) 112

−−==

LPFnωωτ

LPFnωω 2=∝

−±−=

2

111

ξξω

ns

ξξξξ is typically chosen to be √2/2 or largerso as to provide a well-behaved (criticaldamped or overdamped) time-domainresponse.

Frequency Multiplication

In the same way the output frequency of a PLL can be divided and then fedback.

The ÷÷÷÷M circuit is a counter that generates one output pulse for every Minput pulses. The divide ratio, M, is called the “modulus”.

The loop locks at ωωωωin=ωωωωF=ωωωωout/M ωωωωout=Mωωωωin.

The effective VCO gain is reduced to KVCO/M reducing the open-loop gain(higher static phase error).

Programming the value of M, the loop can be used as a frequencysynthesizer.

A voltage buffer can provide amplification if its output is divided beforereturning to the input.

Drawbacks of Simple PLL

Limited “acquisition range”: if the VCO frequency and the inputfrequency are very different at the start-up, the loop may never “acquire”lock.

The finite static phase error and its variation with the input frequency alsoprove undesirable in some applications.

Tight relation between the loop stability and the corner frequency ofthe low-pass filter.

Type-II PLL: Phase/Frequency Detectors

A rising edge on A sets QA (if QA=QB=0), while a rising edge on B resetsQA (if QA=1).

The circuit is symmetric with respect to A and B (and QA and QB)

The limited frequency range is due to the fact that PDs produce little info ifthey sense unequal frequencies.

It is desirable a circuit that operates as a FD if its input frequencies aredifferent, and as a PD if they are. Such circuit is called a phase/frequencydetector (PFD)

Phase/Frequency Detectors

The average value of QA-QB represents the frequency (if ωωωωA≠ωωωωB) orphase difference (if ωωωωA=ωωωωB

)

PFD: Logical Implementation

Glitches on QB appears due to finite logic gates delay.

Use of a PFD in PLL

At the beginning of a transient, the PFD acts as a frequency detector,pushing the VCO frequency toward the input frequency.

After the two are sufficiently close, the PFD operates as a phase detector,bringing the loop into phase lock.

Charge Pumps

Useful to address the trade-offbetween stability and phase error/ripple.

Switches S1 and S2 are controlled bythe inputs “UP” and “Down”,respectively. Nominally I1=I2=Ip.

A pulse of width ∆T on Up turns S1 onfor ∆T seconds, allowing I1 to chargeC1. Vout goes up by ∆T · I1/C1

Similarly, a pulse on Down yields adrop in Vout.

If Up and Down are assertedsimultaneously, I1 simply flowsthrough S1 and S2 to I2, creating nochange in Vout (I

1=I

2).

PFD/CP Cascade

an arbitrarily small (constant) phase difference between A and B turns one switch on,thereby charging or discharging C1 and driving Vout toward +∞ or -∞, i.e. a gain= ∞

if the loop time constant >> Tin, we can approximate this waveform by a ramp, as if thecharge pump continuously injected current into C1 (continuous time approximation)

The circuit behaves as an integrator

Charge Pump PLLs

The loop forces the input phase error to zero because a finite error wouldlead to an unbounded value fro Vcont (like the short-circuit approx. inopamps).

Called Type-II PLL because its open-loop transfer function contains twopoles at the origin.

The two cascading integrators produce instability.

Charge-Pump PLL

If one of the integrators becomes lossy, the system can be stabilized.

This can be accomplished by inserting a resistor in series with C1. Theresulting circuit is called a “charge pump PLL” (CP-PLL).

R1 introduces a zero

Stability of Charge-Pump PLL

As C1 increases, so does ζ --- a trendopposite of that observed in type-IPLL: trade-off between stability andripple amplitude thus removed.

A similar trend is observed for KVCO

(also in this case opposite wrt type IPLLs).

The phase margin is increased by the zero

Frequency-Multiplying CP PLL

The division of KVCO by M makes the loop less stable, requiring that Ipand/or C1 be larger.

Higher-Order Loops

The loop filter consisting of R1 and C1 proves inadequate because,even in the locked condition, it does not suppress the ripplesufficiently.

Suppose, in the locked condition, the up and down pulses arrive with asmall skew due to a propagation mismatches within the PFD

The ripple thus consists of positive ad negative pulses of amplitudeIpR1 (even higher than VDD!!!) occurring every Tin seconds.

C2 should be sufficiently high to reduce ripple.

C2 introduce an addition pole (ττττ) degrading the loop stability. The phase margin is (ξξξξ is still the damping factor of the original second-order loop)

In typical design we choose ζ = 1 and C2 ≈ 0.2C1 to maximize phase margin

R1 cannot be arbitrarily (to increase ζζζζ) high otherwise the loop filter reduces to C2

Addition of Second Capacitor to Loop Filter

A common approach to lowering the ripple is to tie a capacitor C2 directly from the control line to ground.

Alternative Second-Order Loop Filter

The ripple at node X may be large but it is suppressed as it travels throughthe low-pass filter consisting of R2 and C2

The additional pole is at (R2C2)-1

(R2C2)-1 must remain 5 to 10 times higher than ωz= (R1C1)

-1 so as to yield areasonable phase margin.

Phase Noise in PLLs: VCO Phase Noise

PLL suppresses slow variations in the phase of the VCO but cannot provide much correction for fast variations (the loop gain falls)

Two sources of noise:

the input reference oscillator phase noise (φφφφin)

the VCO phase noise (φφφφVCO)

Consider the VCO noise and set φφφφin=0

VCO Phase Noise vs. Loop Bandwidth

the bandwidth can be increased if ωn is increased by a factor of K (suppose ζis maintained constant).

both poles scale up by a factor of K.

since Φout/ΦVCO ≈ s2/ωn2 for s ≈ 0, the plot is shifted down by a factor of K2 at

low values of ω that is the response now suppresses the VCO phase noise to agreater extent.

VCO Phase Noise in PLL with feedback divide ratio

the feedback is now weaker by a factor of M. The transfer function still applies, but bothζ and ωn are reduced by a factor of √M .

to maintain the same transient behavior, ζ and ωn must be constant; e.g., the chargepump current must be scaled up by a factor of M. Thus, the poles given by previousequation simply decrease by factor of √M .

for s0, Φout/ΦVCO ≈ s2/ωn2, which is a factor of M higher than that of the dividerless

loop. The magnitude of the transfer function thus appears as depicted below on the right.

√M √M

÷÷÷÷M

VCO Phase Noise: White Noise and Flicker Noise

low offset frequencies high offset frequencies

ω is the offset frequency

The VCO phase noise is “shaped” by the PLL transfer function

(ζ =1)

(ζ =1)

Shaped VCO Noise Summary

The overall PLL output phase noise is equal to the sum of SA and SB

resulting lower wrt the VCO phase noise.

The actual shape depends (1) on the intersection frequency of α/ω3 andβ/ω2 (2) on the value of ωωωωn

(left) the intersection of α/ω3 and β/ω2 lies at a low frequency (wrt ωωωωn)

(right) the intersection of α/ω3 and β/ω2 lies at a high frequency (wrt ωωωωn)

Shaped VCO Noise Summary

high thermal noise induced phase noise

low thermal noise induced phase noise

Reference Phase Noise

Crystal oscillators providing the reference typically display a flat phase noiseprofile beyond an offset of a few kilohertz.

The output phase noise is shaped by the PLL transfer function.

The total phase noise at the output increases with the loop bandwidth, atrend opposite to that observed for VCO phase noise.

PLLs performing frequency multiplication “amplify” the low-frequencyreference phase noise by a factor M2.

Overall Phase Noise

the loop bandwidth entails a trade-off between the reference and the VCO phase noise.

Loop Bandwidth

Loop Filter Design Procedure

The loop filter is designed beginning with the two governing equations

We now have two equations and three unknowns (Ip, C1, R1). The chargepump current can be chosen in the range of few tens of µµµµA to few mA.

We choose C2=0.2C1 so as to maximize phase margin.

The loop time-constant must be much longer than the input period toensure a well behaved settling (loops that are not sufficiently slow exhibitan underdamped behavior or may simply not lock). In typical design

Loop Filter Design Example

Solution:

A PFD-CP/type II-PLL (Ip = 500 µA) must generate an output frequency of 2.4GHz from a 1-MHz reference with a symmetrical tuning range of 12.5% andVDD=1V. The input reference phase noise is -150 dBc/Hz at 100 kHz frequencyoffset, and the VCO phase noise is -70 dBc/Hz at 100 KHz frequency offset.Determine

1) the loop filter parameters2) the output phase noise at 100 kHz frequency offset

We selectζ = 12.5ωn = ωin/10 ωn = 2π(40 kHz)

KVCO= 2π×××× 0.125*2.4Ghz/1V= 2π×××× 300 MHz/V

Substituting in the above equations (M=2400)

C1 = 1 nF and R1 = 8 kΩ.

C2 =0.2C1= 0.2 nF.

PLL Phase Noise Example

The output phase noise due to the VCO is (the term in parenthesis is theVCO phase noise, i.e. -70 dBc/Hz)

The output phase noise due to the input reference is (SREF is the inputreference phase noise , i.e. -150 dBc/Hz)

The overall phase noise is due only to the VCO noise (-71.3 dBc/Hz)

= -71.3 dBc/Hz

= -153 dBc/Hz