Basic VLSI Slides

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VLSI DesignShailendra Kumar Tiwari

Assistant Professor

(Senior Scale)

Lecture 01

1.Reference Books2.Syllabus.3.What is there for me?4. What is expected ?5. Are we meeting with

expectation?6.Device generations7.Design abstraction level8.Moore’s law9.Technology generation10.Conclusion

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“Basic VLSI Design”, 3rd Ed., PHIBy: PUCKNELL DOUGLAS A.

KAMRAN ESHRAGHIAN,

“CMOS DIGITAL INTEGRATED CIRCUITS:Analysis and Design” 3rd Ed. McGraw-Hill.By:SUNG-MO (STEVE) KANG

Reference Books

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Digital Integrated Circuits – A Design Perspective”,2nd ed. by J. Rabaey, A. Chandrakasan, B. Nikolic

“CMOS LOGIC CIRCUIT DESIGN” KLUWER ACADEMIC PUBLISHERSBy: John P. Uyemura

Reference Books

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“CMOS VLSI Design:A Circuits and SystemsPerspective” 4th ed. Addison-Wesley

By: Neil H. E. Weste, David Money Harris

Reference Books

Syllabus

Course Plan

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What is there for me?

http://www.pcb007.com/pages/zone.cgi?a=87231

http://www.pcb007.com/pages/zone.cgi?a=87231

What is there for me?

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What is expected ?

1980s

1990s

2000s

What is expected ?

Power Min

MinDesign Time

Cost Min

Complexity

MinDelay

Size Min

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Are we meeting with expectation?

W=0.7, L=0.7, Tox=0.7Lateral and vertical dimensions reduce 30 %

Area Cap = C =. .

.0.7

Capacitance reduces by 30 %

Die Area = 0.7 0.7 0.5

Die area reduces by 50 %

Drain Current reduces by 30 %


Delay

Delay reduces by 30 %

Power P

power reduces by 50 %

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Device generations

Vacuum Tubes

BJT

FET

MOSFET

CMOS

Design abstraction level

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Moore’s law

As predicted by Gordon Moorein the 1960s, integrated circuit(IC) densities have beendoubling approximately every 18months, and this doubling in sizehas been accompanied by asimilar exponential increase incircuit speed (or more precisely,clock frequency)

January 3, 1929

Technology Generation

Integration level Year No. of transistors DRAM Integration

SSI 1950s Less than 102

MSI 1960s 102 103

LSI 1970s 103 105 4K, 16K, 64K

VLSI 1980s 105 107 256K, 1M, 4M

ULSI 1990s 107 109 16M, 64M, 256M

SLSI 2000s Over 109 1G, 4G and Above

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Microelectronics Technology

Micro

Electronics

Active Substrate

Silicon

MOS

NMOS

PMOS

CMOS

Bipolar

TTL

ECL

GaAsVery Fast Devices

Inert Substrate

Good resistors

MOS Vs. BipolarFactors CMOS Bipolar

Static Power Dissipation

Low High

Input Impedance

High Low

Noise Margin High Low

Packing Density High Low

Fan‐out Low High

Direction Bidirectional Unidirectional

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Delay and Power Dissipation Per Gate

MOS Capacitor

i. Accumulation ii. Depletion iii. inversion

0 0

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MOS Capacitor

N Channel MOSFET

P Substrate

P Substrate

Oxide

P Substrate

Oxide

Metal

P Substrate

Oxide

Metal

N+ N+

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N Channel MOSFET

Gate

Drain

Source

P Channel MOSFET

N Substrate

N Substrate

Oxide

N Substrate

Oxide

Metal

N Substrate

Oxide

Metal

P+ P+

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MOSFET Schematic Symbol

Operation Of N‐MOS Transistor

Depending on the relative voltages of the source,drain and gate, the NMOS transistor may operatein any of three regions viz :

•Cut_off : Current flow is essentially zero (alsocalled accumulation region)

•Linear : (Non saturated region)-It is weakinversion region drain current depends on gateand drain voltage.

•Saturation : It is strong inversion region wheredrain current is independent of drain-sourcevoltage.

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Cut‐off Region

• With zero gate bias (VGS=0) , no current flows between source and drain, only the source to drain leakage current exists.

• Current-voltage relation : IDS = 0 VGS < VT

p-type substrate (Body)

Source (S) VDS=0

n+n+ n+n+

VGS=0

Linear Region

• Formation of Depletion layer

• Small positive voltage applied to gate causes electric field to beproduced across the substrate

• This in turn causes holes in P region to be repelled. This formsthe depletion layer under the gate.

VDS=00 VGS Vt


Source (S)

n+n+ n+n+

Depletion Layer

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Linear Region• Formation of Inversion layer :

• As the gate voltage is further increased, at particular voltage VT,electrons are attracted to the region of substrate under gate thus formingconduction path between source and drain.

• This induced layer is called ‘inversion layer’. The gate voltage necessaryto form this layer is known as ‘Threshold voltage’ (VT).

• As application of electric field at gate causes formation of inversionlayer, the junction is known as field induced junction.

VDS=0VGS > Vt


Source (S)

n+n+ n+n+

Inversion Layer

Linear Region

• When VDS is applied, the horizontal component of electric field (dueto source-drain voltage) and vertical component (due to gate-substrate voltage) interact, causing conduction to occur along thechannel.

• When effective gate voltage (VGS - VT) is greater than drainvoltage, current through the channel increases. This is nonsaturated mode. ID = f (VGS,VDS)

VDS < VGS - Vt

VGS > Vt


Source (S)

n+n+ n+n+

Inversion Layer

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As VDS is increased, the induced Channel acquires a tapered shape and its resistance increases with Increase in VDS. Here VGS is kept constant at value > VT

Saturation

VDS = VGS - Vt

VGS > Vt


Source (S)

n+n+ n+n+

n- channel

Saturation

• When VDS > VGS – VT, VGD < VT, the channel becomes pinched- off & transistor is said to be in saturation.

• Conduction is brought by drift mechanism of electrons under the influence of positive drain voltage and effective channel length is modulated.

p

VDS > VGS - Vt

VGS > Vt


Source (S)

n+n+ n+n+

n- channel

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Depletion Type MOS

• In Depletion MOS structure, the source & drain are diffused on P- substrate as shown above.

• Positive voltages enhances number of electrons from source to drain.

• Negative voltage applied to gate reduces the drain current • This is called as ‘ normally ON ’ MOS.

G

D

S

NMOS

Source

Drain

Gate

PMOS

Gate

Drain

SourceNMOS

Depletion Type NMOS


n+ n+

Source (S) Gate (G) Drain (D)

L

Body (B)

Oxide (SiO2)Metal

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Drain to Source Current IDS

the gate and the channel region form a parallel platecapacitor for which the oxide layer serves as a dielectric.

consider the infinitesimal strip of the gate at distance xfromthe source. The capacitance of this strip is

CoxWdx

To find the charge stored on this infinitesimal strip of thegate capacitance, we multiply the capacitance by theeffective voltage between the gate and the channel atpoint x,

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Charge dq in the infinitesimal portion of the channel atpoint x is

Negative sign accounts for the fact that dq is a negative charge

The voltage VDS produces an electric field along thechannel in the negative x direction

The electric field E(x) causes the electron charge dq to

drift toward the drain with a velocity

Where µn is the mobility of electrons in the channel (called surface mobility).

The resulting drift current i

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Thus i must be equal to the source-to-drain current.Since we are interested in the drain-to-source current iD,we can find it as

Integrating both sides of this equation from x = 0 to x = L and, correspondingly, for V(0) = 0 to V(L) = VDS,

2

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• Current is flow of charges.• IDS=f(VGS,VDS)

Continued ……..

Velocity v is given by

μ

µ= electron or hole mobility (surface)EDS= Drain to Source Electric Field

μ


Continued ……..

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μ

µn = 650 cm2/V Secµp = 240 cm2/V Sec

The Non-Saturated Region

• Charge induced in channel due to VGS.• Voltage along the channel varies linearly with distance X

from source due to IR drop in the channel.• The average value of IR drop in the channel

2

Continued ……..


• The effective gate voltageVG= VGS-VT

Charge/unit area= EGins0

Charge induced in channel = WLEGins0

EG= Average electric field gate to channel.0= 8.85×10-14F/cm(Permittivity of free space)ins= 0×4.0

2

D= Thickness of oxide layer Continued ……..


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2

μ2

′2

′μ

′

2 Continued ……..


′μ

μ2

μ2

Continued ……..


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Saturation Region

′2

μ2

2

μ2


Drain curve for NMOS operated withVGS> VT

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ID‐VDS characteristics

52

IGS = 0

IS = ID+

-

+

-

IV characteristics of NMOS

Transconductance curve

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Determine the Region of Operation of M1

1

Off because VGS=0V

2

Saturation VGS –Vt =(1-0.4)V=0.6VVDS =1.5V; (VGS –Vt)< VDS

3

Non-Saturation VGS –Vt =(1-0.4)V=0.6VVDS =0V; (VGS –Vt)> VDS

4

Non-Saturation VGS –Vt =(1.5-.4)V=1.1VVDS =0.5V; (VGS –Vt)> VDS

4

Non-Saturation VGS –Vt =(1.5-0.4)V=1.1VVDS =0.5V; (VGS –Vt)> VDS

5

Cut-Off VGS =0V

6

Saturation VGS –Vt =(0.5-0.4)V=0.1VVDS =0.5V; (VGS –Vt)< VDS

7

Saturation VGS –Vt =(1-0.4)V=0.6VVDS =1V; (VGS –Vt)< VDS

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A 0.18-μm fabrication process is specified to havetox= 4nm, µn=450cm2/Vs and VT=0.5V. Find thevalue of µnCox(Also known as kn’ processtransconductance) For a MOSFET with minimumlength fabricated in this process, find the requiredvalue of W so that the device exhibits a channelresistance rDS of 1K at VGS=1V. Device is operatingin deep linear region.Kn’= 388μA/V2

W= 0.93μm

Consider a process technology for which Lmin = 0.4 μm,tox = 8 nm, μn = 450 cm2/V⋅ s, and Vt = 0.7 V.

(a) Find Cox and Kn’.

(b) For a MOSFET with W/L= 8 μm ⁄ 0.8 μm calculate thevalues of VOV, VGS, and VDSmin needed to operate thetransistor in the saturation region with a dc currentID = 100 μA.

(c) For the device in (b), find the values of VOV and VGS

required to cause the device to operate as a 1000-resistorfor very small vD VGS = 1.215 VVOV = 0.51 V

VDSmin = VOV = 0.32 V VGS = 1.015 V

Kn’= 194.1 μA/V2Cox =4.31x10-3F/m2

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For a 0.8-μm process technology for which tox = 15 nm andμn = 550 cm2/V⋅s, find Cox, K’n , and the overdrive voltage VOV

required to operate a transistor having W/L=20 in saturationwith ID = 0.2 mA. What is the minimum value of VDS needed?

A circuit designer intending to operate a MOSFET insaturation is considering the effect of changing the devicedimensions and operating voltages on the drain current ID.Specifically, by what factor does ID change in each of thefollowing cases?(a) The channel length is doubled.(b) The channel width is doubled.(c) The overdrive voltage is doubled.(d) The drain-to-source voltage is doubled.

Kn’= 126.5μA/V2Cox =2.301x10-3F/m2 VDSmin = VOV = .397 V≈0.4V

An enhancement type NMOS transistor with Vt = 0.7Vhas its source terminal grounded and a 1.5-V DC isapplied to the gate. In what region does the deviceoperate :for (a) VD = +0.5 V (b) VD = +0.9 V (c) VD = +3 V

If the NMOS device in µnCox = 100 µA/V2 , W = 10 µm,and L = 1 µm, find the value of drain current that resultsin each of the three cases (a), (b), and (c).

(a) Non Satn275 µA

(b) Satn320 µA

(c) Satn320 µA

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The PMOS transistor shown in Fig. has Vtp=-1V,(a) Find the range of VG for which the transistor conducts.(b) In terms of VG, find the range of VD for which the transistor

operates in the triode region.(c) In terms of VG, find the range of VD for which the transistor

operates in saturation.

Second‐order Effects

• Body Effect.

• Sub threshold conduction

• Channel length modulation

• Mobility variation

• Fowler‐Nordheim tunneling

• Drain punchthrough

• Impact Ionization‐Hot electrons.

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Body EffectWhat happens if the bulk voltage of an N-MOSFET dropsbelow the source voltage ?

2

where φMS is the difference between thework functions of the polysilicon gate andthe silicon substrateφF= Fermi potential

Sub threshold conductionFor VGS ≈ VTH, a "weak“ inversion layer still exists andsome current flows from D to S. Even for VGS < VTH, ID isfinite, but it exhibits an exponential dependence on VGS

Called "subthreshold conduction“. this effect can beformulated for VDS greater than roughly 200 m V as

ζ>1 is a nonideality factor

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Channel length modulation

λ is a process-technology parameter with the dimensions of V-1

VA is a process-technology parameter with thedimensions of V.

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Mobility variation

Mobility is the defined as the ease with which the chargecarriers drift in the substrate material. Mobility decreaseswith increase in doping concentration and increase intemperature. Mobility is the ratio of average carrier driftvelocity and electric field. Mobility is represented by thesymbol μ.

When the gate oxide is very thin there can be a currentbetween gate and source or drain by electron tunnelingthrough the gate oxide. This current is proportional to thearea of the gate of the transistor.

Fowler Nordhiem tunneling:

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Drain punchthrough

When the drain is a high voltage, the depletion regionaround the drain may extend to the source, causing thecurrent to flow even it gate voltage is zero. This is knownas Punchthrough condition.

Impact Ionization‐Hot electrons

When the length of the transistor is reduced, the electric fieldat the drain increases. The field can be come so high thatelectrons are imparted with enough energy we can term themas hot. These hot electrons impact the drain, dislodging holesthat are then swept toward the negatively charged substrateand appear as a substrate current. This effect is known asImpact Ionization.

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Pass Transistors (NMOS)

NMOS

• NMOS Pass transistor passes strong logic 0.

• NMOS Pass transistor passes weak logic 1.

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Pass Transistors (PMOS)

Pass Transistors (PMOS)

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PMOS

• PMOS Pass transistor passes weak logic 0.

• PMOS Pass transistor passes strong logic 1.

Transmission Gate

PMOS Pass transistor passes strong logic 1.NMOS Pass transistor passes strong logic 0.

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Inverters

Inverters

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Inverters

VOH: Maximum output voltage when the output level is logic " 1”VOL: Minimum output voltage when the output level is logic “0”VIL: Maximum input voltage which can be interpreted as logic "0"VIH: Minimum input voltage which can be interpreted as logic "1"

Resistive Load Inverter

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Enhancement load NMOS inverter

Depletion Load NMOS Inverter

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When the input voltage Vin is smaller than the driverthreshold voltage VT0, the driver transistor is turned offand does not conduct any drain current. Consequently,the load device, which operates in the linear region, alsohas zero drain current.

Substituting VOH for Vout

Calculation of VOH

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Depletion Load NMOS InverterCalculation of VOL

We assume that the input voltage Vin of the inverter is equal to VOH = VDD

Driver transistor linear region Depletion-type load saturation region

This second-order equation in VOL can be solved by temporarily neglecting the dependence of VT load on VOL, as follows.

Depletion Load NMOS InverterCalculation of VIL

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Depletion Load NMOS InverterCalculation of VIL

Depletion Load NMOS InverterCalculation of VIH

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Depletion Load NMOS InverterCalculation of VIH

Where

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CMOS Inverter

VOH: Maximum output voltage when the output level is logic " 1"VOL : Minimum output voltage when the output level is logic "0"VIL: Maximum input voltage which can be interpreted as logic "0"VIH: Minimum input voltage which can be interpreted as logic " 1"

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Region A• PMOS – Nonsaturation Region

• NMOS ‐ Cutoff

Vout= VDD - IDRCPMOS

Vout= VDD

Region BVILPMOS – Nonsaturation RegionNMOS – Saturation RegionThe slope of the VTC is equal to (-1), when the input voltage is V = VIL.

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To satisfy the derivative condition at VIL we differentiate both sides with respect to Vin.

Where

Region‐CVthPMOS – Saturation RegionNMOS – Saturation Region

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Where

Region‐DVIHPMOS – Saturation RegionNMOS – Non-saturation Region

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Where

when the input voltage exceeds VDD the pMOS transistor is turned off. In this case, the nMOS transistor is operating in the linear region, but its drain to- source voltage is equal to zero because

The output voltage of the circuit is

Region‐EVOL

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MOS Transistor Transconductance gmand output conductance gds


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MOS Transistor Figure of Merit

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Determination of pull‐up to pull‐down ratio (Zp.U/Zp.D.) For An Nmos Inverter Driven By Another NmosInverter

Vinv=0.5VDD

Noteμ

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substitute typical values as follows

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Pull‐up to pull‐down ratio for an Nmos inverter driven through one or more pass transistors

Vtp = threshold voltage for a pass transistor

Now, for depletion mode p.u. in saturation with VGS = 0

Noteμ

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Consider inverter 2 (Figure 2.10(b)) when input = VDD- Vtp.

This image cannot currently be displayed.



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Taking typical values

0.5

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113

Mask

Common material used for masks are Photoresist, Polysilicon, Silicon dioxide, Silicon nitride.

To create mask:(a) deposit mask material over entire surface(b) cut windows in the mask to create exposed areas(c) deposit dopant(d) remove un-required mask material

• Masks plays important role in process called selective diffusions.

• The selective diffusion involves 1. Patterning windows in a mask material on the surface of

the wafer. 2. Subjecting the exposed areas to a dopant source.3. Removing any un-required mask material.


Photolithography• The Process of using an optical image and a photosensitive

film to produce a pattern on a substrate is photolithography

• Photolithography depends on a photosensitive film called a photo-resist.

• Types of resist

• Positive resist, a resist that become soluble when exposed and forms a positive image of the plate.

• Negative resist, a resist that lose solubility when illuminated forms a negative image of the plate.

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115

Photolithography

p–type body

Substrate9/5/2015 S. K. Tiwari (Asst. Prof. ECE MIT Manipal)

116Resist application

p–type body

Photolithography


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117Exposure

p–type body

Photolithography


118Positive Resist

p–type body

Etching

Photolithography


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119Negative Resist

p–type body

Etching

Photolithography



Si(100)P‐Type

NMOS Fabrication Steps1. Selection of Substrate

2. Cleaning

3. Oxidation

Si(100)P‐Type

SiO2

Si+O2SiO2(good quality)Si+2H2OSiO2+ 2H2(poor quality)

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4.Lithography with MASK1

Si(100)P‐Type

SiO2

+VE Photoresist

UV

MASK1

A A’


Photoresist development and Oxide Etching

Si(100)P‐Type

Photoresist Etching

Si(100)P‐Type

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Gate Oxidation

Si(100)P‐Type

Poly Silicon Deposition

Si(100)P‐Type

SiH4Si+2H2


Si(100)P‐Type

Poly Si

Lithography for Gate Electrode

+VE Photoresist

MASK2

UV

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Si(100)P‐Type

Poly Patterning

Photoresist Cleaning

Si(100)P‐Type


Lithography for Source and Drain region

Si(100)P‐Type

UV

MASK 3

S D

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Si(100)P‐Type

Oxide etching (HF Cleaning)

Photoresist cleaning

Si(100)P‐Type


Si(100)P‐Type

N+ N+

Ion Implantation

Si(100)P‐Type

N+ N+

Thick Oxide Deposition

5,17,21,28,30,34,43,44,51,54,55,58,

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Lithography and Contact Opening

Si(100)P‐Type

N+ N+

UV

MASK 4

S G D


Si(100)P‐Type

N+ N+

Metallization and Patterning

SG D

Body terminal is not shown…..

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131

Fabrication of CMOS Devices

Technologies used for CMOS fabrications include

• N-well process

• P-well process

• Twin-tub process

• Silicon on insulator.


132

• In order to have both types of transistors on the same substrate, thesubstrate is divided into “well” regions (Shaded region in thestandard cells)

• Two types of wells are available - n- well and p- well

• In a p- substrate, an n- well is used to create a local region of n typesubstrate, wherein the designer can create p- transistors

• In a n- substrate, a p- well creates a local p- type substrate region, toaccommodate the n- transistors.

• Hence, every p- device is surrounded by an n- well, that must be

connected to VDD via a VDD substrate contact.

• Similarly, n- devices are surrounded by p- well connected to GNDusing a GND substrate contact.

P‐Wells and N‐Wells


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133

P‐Wells and N‐Wells

• A p- transistor is built on an n- substrate and an n- transistor is built on a p-substrate

P-well N-well

P substratecontact [P+]

N substratecontact [n+]

OUT

IN

G GD S

n+ n+ p+p+


MASK for CMOS Inverter


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N‐Well CMOS Inverter


1• Substrate Selection Si (100)

2• Cleaning of the Substrate

3• Oxidation(1µm)

4• Lithography(MASK1)

5• HF(Oxide) Cleaning & PR Etching

6• N‐Well implantation

7• Oxide Etching

8• Gate Oxide Deposition

9• Poly‐Si Deposition

10

• Lithography and Oxide Patterning

11

• Lithography (MASK‐2)

12

• Poly‐Si Patterning

13

• Lithography(MASK3)

14

• HF(Oxide) Cleaning & PR Etching

15

• Ion‐implantation NMOS

16

• Repeat 12 to 14 for PMOS

17

• Deposition of Thick Oxide

18• Metallization and Patterning

1.Selection of Substrate


Si (100)P ‐type

2. Cleaning of Substrate

The n-well CMOS process starts with a moderatelydoped (with impurity concentration typically less than1015 cm-3) P-type silicon substrate.

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3. Oxidation(1µm)


Si (100)P ‐ ‐type

SiO2

Lithography(MASK1)



SiO2

Positive PhotoresistPositive Photoresist

MASK 1

UV

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SiO2


SiO2

HF(Oxide) Cleaning & PR Etching



SiO2


N-Well Implantation


SiO2

N‐Well

N-type impurity implantation

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Oxide Cleaning



N‐Well

Gate Oxidation


N‐Well


Poly‐Silicon Deposition


N‐Well

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N‐Well

Lithography(MASK2)



N‐Well


N‐Well

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Lithography(MASK3)


N‐Well




N‐Well


N‐Well

faculty

Oval

faculty

Callout

Remove the PR

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Ion Implantation



N‐Well

N+ N+ N+

Repeat 12 to 14 for PMOS



N‐Well

N+ N+ N+P+P+P+

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N‐Well

N+ N+ N+P+P+P+




N‐Well

N+ N+ N+P+P+P+

Lithography and Oxide Patterning

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N‐Well

N+ N+ N+P+P+P+

VSSVDD

Twin‐Tub CMOS Fabrication


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1.Selection of Substrate


2. Cleaning of Substrate

The twin-tub CMOS process starts with a high resistiven-type (100) silicon substrate.

Si (100)N ‐type

Epitaxial Layer Deposition


Epitaxial layer

Si (100)N ‐type

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3. Oxidation(1µm)


Epitaxial layer

SiO2

Si (100)N ‐type

Lithography(MASK1)


SiO2

Positive PhotoresistPositive Photoresist

MASK 1

UV

90

Si (100)N ‐type

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SiO2

90


Si (100)N ‐type


SiO2

Si (100)N ‐type

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SiO2


90

Si (100)N ‐type


N-Well Implantation

SiO2

N‐Well

N-type impurity implantation

Si (100)N ‐type

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Oxide Cleaning


Gate Oxidation

N‐WellP‐Well

N‐WellP‐Well

Si (100)N ‐type

Si (100)N ‐type


Poly‐Silicon Deposition

N‐WellP‐Well

Si (100)N ‐type

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Lithography(MASK2)

N‐WellP‐Well

Si (100)N ‐type


N‐WellP‐Well

N‐WellP‐Well

Si (100)N ‐type

Si (100)N ‐type

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Lithography(MASK3)

N‐WellP‐Well

Si (100)N ‐type


N‐WellP‐Well

Si (100)N ‐type

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Ion Implantation


N‐WellP‐Well

N+ N+ N+

Si (100)N ‐type


N‐Well

N+P+P+P+

P‐Well

N+ N+P+

Si (100)N ‐type

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N‐Well

N+ N+ N+P+P+P+


Si (100)N ‐type

P‐Well

N+ N+P+


N‐Well

N+ N+ N+P+P+P+

Lithography and Oxide Patterning

P‐Well

N+ N+P+

Si (100)N ‐type

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N‐Well

N+ N+ N+P+P+P+

VSSVDD

P‐Well

N+ N+P+

Si (100)N ‐type

Latch‐Up


Tendency of CMOS chips todevelop low-resistance pathsbetween VDD and VSS CalledLatch-up

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Latch‐Up


These BJTs form a silicon-controlledrectifier (SCR) with positive feedbackand virtually short circuit the power railto-ground, thus causing excessivecurrent flows and even permanentdevice damage.

PNP transistor whose base is formedby the n-well with its base-to-collectorcurrent gain (β1) as high as severalhundreds.

NPN transistor with its base formed bythe p-type substrate. The base-to-collector current gain β2 of this lateraltransistor may range from a few tenthsto tens

Latch‐up


Rwell represents the parasitic resistance in the n-wellstructure with its value ranging from 1 kΩ to 20 kΩ.

Rsub can be as high as several hundred ohms.

Unless the SCR is triggered by an external disturbance,the collector currents of both transistors consist of thereverse leakage currents of the collector-base junctionsand therefore, their current gains are very low.

If the collector current of one of the transistors istemporarily increased by an external disturbance,however, the resulting feedback loop causes this currentperturbation to be multiplied by (β1 β2). This event is calledthe triggering of the SCR.

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Latch‐up


Once triggered, each transistor drives the other transistor withpositive feedback, eventually creating and sustaining a low-impedance path between the power and the ground rails,resulting in latch-up. It can be seen that if the condition

Technique to overcome Latch‐up


Use p+ guard-band rings connected to ground aroundnMOS transistors and n+ guard rings connected to VDDaround pMOS transistors to reduce R and RSUb and tocapture injected minority carriers before they reach thebase of the parasitic BJTs.

Place substrate and well contacts as close as possible tothe source connections of MOS transistors to reduce thevalues of Rwell and Rsub.

SOI Devices

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SOI fabrication


Refer: Principles of CMOS VLSI Design A system perspective 2nd Ed. By Neil H. E. WeKamran Eshraghian Page no. 125-129


SOI fabrication

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SOI fabrication


SOI fabrication

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SOI fabrication

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