Big Physiscs - Evento di Catania

8/14/2019 Big Physiscs - Evento di Catania

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LabVIEW FPGA unleashed: FlexRIO!

ATE & RF Systems Engineer


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LabVIEWFPGA 2009: more power CLIP Node

NI Labs Additional Features

FPGA for T&M hardware: FlexRIO

Designing custom I/O adapter modules


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-easuremen

Analog or

Digital

Bus Interface

and I/O

Control

Standard Virtual

Instrumentation

Software Hardware

DriverNI LabVIEW

10011011


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-

Open MeasurementAnalo or

Bus Interface/

ProgrammableFPGA

DriverLabVIEW

System

Model

Digital

Front End

Software NI Hardware

System intelligence and decision making can bemove rom so tware to ar ware


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Low LatencyRun algorithms at deterministic ratesown o ns

ReconfigurableCreate application-specific

personalities Hi h Performance Com utational abilities o en new

possibilities for measurement and data processing speed

,reducing test times


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FPGA for Test A lication Areas

Real-time / co- rocessin

Data reduction / in-line processing

Protocol-aware ATE

Interfacing (digital or modulated)Protocols

Response-stimulus test

Closed-Loop- - -

Complex triggers

Control


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Translation Optimization Synthesis Bit Stream

VHDL Generation Analysis

Logic Reduction

Place and Route

Timing Verification

Generation

Download / Run


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LabVIEW FPGA Histor

LabVIEWFPGA&LabVIEWFPGA&Virtex5RSeriesVirtex5RSeriesLabVIEWFPGALabVIEWFPGA

RIOIF

TransceiverRIO

IF

Transceiver

RSeriesReleasedRSeriesReleased

CompactRIOCompactRIOFlexRIOFlexRIO

sbRIOsbRIO

NIWeek

NIWeek Lotsof

cRIOstuff!

Lotsof

cRIOstuff!

97 03 04 05 06 07 08 09


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Traditional FPGA Design Flow


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LVFPGA Design Flow


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Why Use LabVIEW FPGA?

No HDL experience needed

Results comparable in size and speed to HDL

Everything in one software environment Faster code development

Easier testbench creation

Faster FPGA code simulation


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DRAMsupport

ExternalClocks*

Peerto

Peer

Streaming*

DMATransferratesupto800MB/s*

Upto16DMAchannelsperdevice*

*onselectedtargets


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What Is a CLIP?

Component Level Intellectual Property A CLIP is a concept that allows users to add

project

s are omponent eve ecause t e

code executes in parallel to the LV FPGA VI


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Com onent Level IP CLIP Goals

Run HDL code in parallel with LabVIEWcode

Including custom constraints file

Facilitate insertion of third-party IP Execute HDL in multiple clock domains

Facilitate hi h-s eed interface desi n

Access FPGA pins directly from CLIP HDL Exercise s ecific features of the FPGA SerDesblock

various differential I/O standards)

Provide flexible communication ath between CLIPnode and LVFPG


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FPGA for Test Hardware


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a ona ns rumen s ex

LabVIEW FPGA-Enabled Instrumentation


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Synchronization

Clocking/triggers

Virtex-5 FPGA

132 digital I/O lines

Interchangeable I/O

Customizable by users Power/cooling

Data streaming

128 MB of DDR2 DRAMAdapter Module

Development Kit (MDK)


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NI FlexRIO FPGA Modules for PXI

- LX30, LX50, LX85, LX110

Direct access to FPGA I/O 132 single-ended lines or 66

differential pairs

-

1 Gbps differential

2x 64 MB banks

800 MB/s per bank Adapter module required for IO


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FlexRIO - CLIPs

S Te

CLIP

CLIP

CLIP

ocket

rmin

dCLI

lBlo

SocketedCLIP Socketed

CLIP

k

DRAMDRAM DRAMDRAM


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Addin a CLIP to the LabVIEW Pro ect

entity AnalogFrontEnd is

port (

AnalogFrontEndCLIP.vhd

adcCh0_LV : out std_logic_vector(15 downto 0);

adcCh0_TB : in std_logic_vector(15 downto 0) := x"0000"

);

end AnalogFrontEnd;

begin

adcCh0_LV

LabVIEW


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Addin a CLIP to the LabVIEW Pro ect


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Demo: reuse a DDS Netlist


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ar e ge connec o

Defines I/O for NILabVIEW FPGA

Custom connectivit

Adapter Module


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NI Modulesr - ar y

Modules

us om

Modules

Complete Expands NI Requires PCB

integration withLabVIEW FPGA I/O breadth Custom and

and HDL designwork

R Series-like

experience

application-

specific modules

Supported

through MDK


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NI 6581

High-Speed Digital Adapter Module 100 MHz digital I/O

54 single-ended channels Selectable voltage levels

. , . , .

External DIO voltage reference

NI 6581

Output Enable

Data In

DDC


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-

Channel Both CLIPs Write to or read from

individual DIO lines

Internal or external

clocking (invert clock)

Port

Write to or read from an 8

nerna or exerna power

supply

bit port

level (1.8, 2.5, 3.3 V)

You can have multiple CLIPs per Adapter Module


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200 MHz LVDS Digital Instrument

200 MHz digital I/O 32 / 42 LVDS channels

,

PXI-6585R


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Gigabit Ethernet interfaces

MAC and Ethernet frames

Camera Link Interface

High-speed image processing Fault-injection software Low-latency control

IEEE-1394b interface

100 MHz vector digital I/O

. -


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Custom NI FlexRIO Adapter Module

Development Kit (MDK)

6 W Power electrical and thermal limit

. LVTTL (3.3 V), LVCMOS (1.2, 1.5, 1.8, 2.5, 3.3 V),

LVDCI 1.5 1.8 V 2.5 3.3 V LVDS 2.5 V 400 Mbps (Single-Ended), 1 Gbps (Differential)

I2C EEPROM for module identification and use -defined storage

NI Mechanical Enclosures


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Documentation Access to private email address for support

VHDL programming (good level)

High-Speed PCB layout experience


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Bring Up your Adapter Module

Create or acquire thesocketed CLIP to create

Program the IO ModuleID into the EEPROM Create the AMconfiguration (.tbc) file

Create or acquire IP Generate optional constraints

Create Declaration File

Configure the AM in aLabVIEW project


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Program EEPROM

IO Module ID

Program ID Confirm ID

Vendor ID

0xFFFF0001

NI Vendor ID: 0x1093

u

Product ID

Differentiates modules from same vendor


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Program EEPROM

Optional Parameters Serial Number

Byte Address Size (Bytes) Field Name Required?

0x0 2 Vendor I Yes

0x2 2 Product ID Yes

0x4 4 Serial Number No0x8 24 Reserved No

0x20 224 User Space No


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Adapter Module Interface Protocol

Manages safe adapter module insertion/removal At insertion:

Verifies inserted module matches FPGA bitstream

settings prevents incompatible IO directions andvoltages

Enables power supplies and then FPGA outputs

At removal: Disables FPGA outputs and all power rails


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1. Check TB_Present_n

Software forced redetect

System power up or FPGA download

2. Enable Veeprom3. Read EEPROM ID, check bitstreamfor match

. na e a power ra s

5. Wait for TB_Power_Good

. Allows CLIP to enable outputs and BUFGCE safely


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Configure VCCOA and VCCOB Ensures proper bank voltages

Used by LabVIEW project

e o urng comp a on


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Each bank is powered by VccoA

or VccoB

Consider Necessary Logic Levels When

Choosin How to Divide the Volta e Banks


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FPGA IO Standards

Xilinx FPGA IO Blocks support several IOan ar s

FlexRIO GPIO su ort a subset of these IOStandards, including:

IO Standard Vcco

.

LVCMOS__ 1.2V, 1.5V, 1.8V, 2.5V, 3.3V

LVDCI__ (DCI R = 50) 1.5V, 1.8V, 2.5V, 3.3V

LVDS_25 (inputs use internal 100) 2.5V

an ar s may e mxe w n a an ,Vccovoltages are the same

See Virtex 5 User Guide for more details


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.

[General]

= .

Manufacturer=National Instruments

Model=NI 5681

Description= National Instruments IF module

Basic adapter module info

cco eve = .

VccoBLevel=3.3

IOModuleID=0x10935681

DefaultCLIP=IFModuleClip

Set Logic Levels: must match I/O Standard constraint

Used by LV project

[Constraints]INST "*Ibufd*" DIFF_TERM = TRUE;

INST "*Ibufgd*" DIFF_TERM = TRUE;

Additional Xilinx Physical Interface Constraints

# Bank 0 & 1: 2.5V

NET "aUserGpio" IOSTANDARD = LVDS_25;

NET "aUserGpio_n" IOSTANDARD = LVDS_25;NET "aUserGpio" IOSTANDARD = LVDCI_25;

# Bank 2 & 3: 3.3V

NET "aUserGpio" IOSTANDARD = LVDCI_33;


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PXI

795x

FPGAS

Provides indirect access to

external I/O

LabVIEW

ocket

dapt

Interchangeable I/O

hardware defines the FPGA

FPGAVI

PXIBus dCLI

rM

The user definesrepresentation of hardware

Socketed

CLIP

dule

Socketed

CLIP

in LabVIEW

Allows for use of specific

DRAMDRAM DRAMDRAM

FPGA I/O features


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Create or Acquire IP

Create Constraints (if needed)

Add CLIP to LV FPGA project


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Implementing Socketed CLIPs

Create or Acquire IP Fixed hardware interface (GPIO, etc)

S S


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Ada ter Module Socket Si nals

aUserGpio Bidirectional std_logic_vector(65 downto0)

aUserGpio_n Bidirectional std_logic_vector(65 downto0)

rIoModGpioEn To CLIP std_logic

UserGClkLvds To CLIP std_logic

UserGClkLvds_n To CLIP std_logic

UserGClkLvttl To CLIP std_logic

Signal Name Direction Data TypeIoModClipClock0 From CLIP std_logic

IoModClipClock1 From CLIP std_logic


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Share bus with

Socketed CLIP

FlexRIO fixed lo i

Signal Name Direction Data Type

rLvFpgaReqI2cBus From CLIP std_logic

rLvFpgaAcqI2cBus To CLIP std_logic FlexRIO Host VIs

rLvFpgaI2cGo From CLIP std_logic

rLvFpgaI2cStart From CLIP std_logic

rLvFpgaI2cStop From CLIP std_logic

in CLIP

rLvFpgaI2cRd From CLIP std_logic

rLvFpgaI2cWtData From CLIP std_logic_vector(7 downto0)

rLvFpgaI2cAck To CLIP std_logic

synchronous to 40MHzrClktoSocket To CLIP std_logic (or boolean)

rLvFpgaI2cDone To CLIP std_logic

rLvFpgaI2cRdData To CLIP std_logic_vector(7 downto0)


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HSDIO Cable

clock DDR

NI 6581 buffer only

Demo PCB

TxDACCustom Adapter

NI 9999

U i NI Fl RIO Ad t M d l


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U comin NI FlexRIO Ada ter Modules

Digitizer Module

-

Baseband Transceiver

-, .,

AC or DC coupled

Q4 2009/ Q1 2010

, .,

100 MS/s, 2 ch., 16-bit DAC

Q4 2009

Digitizer Module

1 ch. at 3 GS/s, 8-bit, or 2 ch. at 1.5 GS/s

Camera Link Module

Single full-configuration interface Digital outputs for control


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C l i


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Conclusions

FPGAs enable some types of test applications

not prevousy poss e, an ma e ot ers aste

LabVIEW FP A smooth learnin curve fordigital desgin

ex ene s

Custom processing and decision making using

COTS platform

Suitable as co- rocessor with 2 data transfer Interchangable I/O and custom designed I/O

Date post:	30-May-2018
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Big Physiscs - Evento di Catania

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