Built-in self-repair techniques for embedded RAMs

S.K. Lu

Abstract: An efficient built-in self-repair approach, column-block-level reconfiguration method- ology, is proposed. It is based on the concept of divided bit-line (DBL) for high-capacity memories including SRAMs and DRAMs, widely used in low-power memory designs. However, the inherent characteristics (two or more memory cells are combined together to divide the hit-line into several sub bit-lines) of divided hit-line memories have not been used for fault-tolerant applications. Therefore the column-block-repair (CBR) fault-tolerant architecture is proposed based on the structure of DBL for high-capacity memories. The redundant columns of a memory array are divided into column blocks and reconfigusation is performed at the column block level instead of the traditional column level. The fault-tolerant architecture can improve the yield for memory fabrication significantly. Moreover, the characteristics of low power and fast access time of DBL memories are also preserved. The reconfiguration mechanism of the CBR architecture requires negligible hardware overhead. According to experimental results, the hardware overheads are less than 0.58% and 0.012% for 256-Khit SRAMs and 8-Mbit DRAMs, respectively. The repair rate of the approach is compared with previous memory repair algorithms. It is found that the CBR approach improves the repair rate significantly. The yield improvement over traditional column- based approaches is also analysed. Simulated results show that the present approach can significantly improve fabrication yield.

1 Introduction

High-density and high-capacity embedded memories are required for successful implementation of a system-on-a- chip (SoC) [l, 21. From the viewpoint of complexity, it is very difficult and costly to test embedded memories from an extemal memory tester as the chip density continues to grow. Moreover, the accessibility of embedded memories is low for extemal testers. A promising solution to this problem is the built-in self-test (BIST) [3-91. However, as the density of memory increases, the circuits become more complex and are prone to suffer from defects [ 101. Therefore it is difficult to keep a profitable yield model. To improve the fabrication yield, redundancies (rows and/or columns) are often added such that most faulty memory cells can be replaced. When this happens, BIST circuits are required not only to detect the presence of faults but also to specify their locations for repair. The extended techniques of BIST are builf-in self-diagnosis (BISD) [ 151 and builf-in self-repair (BISR) [11-141.

Fault-tolerant designs of memories with redundancies have been widely used in the pad. There are two possible solutions to add redundancy into a memory may:

Spare row or spare column: The memory contains spare rows or spare columns. When a fault is detected and must he repaired, the faulty rowlcolumn is replaced with one of the spare row/columus. Although it is easier to repair faulty

Q IEE, 2003 IEE Proceedingr online no. 20030687 doi: 10.1@49/ipcdt:2M)30687 Paper received 10th March 2003 and in revised form 21st May 2003 Thc author is with the Depanment of Electronic Engineering, Fu-Jen Catholic University, Taipei, Taiwan, 242. Republic of China

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cells, this approach is inefficient since a whole spare row/column would be used for repairing a single faulty cell.

Spare row and column: In this approach, spare rows and spare columns are added in the memory array. Either a spare row or a spare column can be used to replace a faulty cell. This approach is more efficient than the first approach when multiple faulty cells are detected. However, the complexity for finding the optimal spare allocation is NP-complete [16]. Moreover, owing to the high bandwidth of embedded RAMs, more spare columns and rows are required to achieve sufficient chip yield. This in turn increases the fabrication cost.

For convenience, these two repair schemes are categorised as the row-based and/or column-based replacement algor- ithms [11-18]. To cure these drawbacks new repair techniques are required for today’s SoC era.

The concept of divided hit-line (DBL) was first proposed in 1998 [19]. The main characteristic of DBL memories is that two or more RAM cells are combined together to divide the global bit-line into several sub hit-lines. These sub hit- lines can he combined to form two or more levels of hierarchy. Therefore the main advantage of DBL is that the power-down technique for unused circuits can save power consumption and reduce delay significantly. Since the inherent characteristic of DBL memories is that the global hit-lines are divided into several sub hit-lines, one can also divide redundant columns of a memory array into column blocks and reconfiguration is performed at the column block level instead of the traditional column level. The proposed approach is called the CBR fault-tolerant technique. This approach maintains the advantages of the row-based and/or column-based replacement algorithms and avoids their drawbacks,

To evaluate the fault-tolerance technique, it is assumed that there exists a mechanism to detect the presence of a faulty block, including the number of faulty cells in a

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memory block, and to locate it. The CBR scheme uses only spare memory columns as redundancy. Redundant rows are omitted here for simplicity. According to experimental results, the hardware overheads are less than 0.58% and 0.012% for 256-Kbit SRAMs and 8-Mbit DRAMS, respectively. The repair rate of the approach is compared with previous memory repair algorithms. It is found that the CBR approach improves the repair rate significantly. The yield improvement over traditional row-based andlor column-based approaches is also significant.

2 Architecture of BISR of DBL memories

Figure 1 shows the divided bit-line structure. The bit-line capacitance can he reduced by this approach, where the number of transistors connected to the hit-line is reduced by combining two or more SRAM cells. The main scenario of DBL is that each column (including the redundant columns) of the memory cell array is divided into a blocks by the bit- line segments. If the memory has n rows, IV'~ rows are included in each column bank. The sub bit-line in each column block is activated by switching transistors, which is controlled by the column bank select line. Thus, only the memory cells connected to a sub bit-line within a selected block are accessed in a given memory cycle.

The fundamental concept of the CBR scheme is shown in Fig. 2. Dividing the memory cell arrays into blocks and for any time instant, only the rows in the addressed block are selected instead of selecting all rows. A faulty block is a block, which contains faulty cells. Faulty blocks are replaced with redundant blocks in the same column hank, one column bank containing several rows. It is assumed that the memory array contains four hit-lines (BO - B3), 16 word lines, and four column hank select lines (CBS, - CBS3). In other words, the memory array is divided into 16 column blocks and there are four column blocks in a bank. In addition, the redundancy included in the memory array contains two spare columns (SCO,SCl), i.e. eight spare column blocks are used as redundancies. In this Figure, faulty blocks are dashed. As indicated by arrows, faculty blocks are repaired by replacing them with their corre- sponding spare blocks (greyed blocks). As a result, two spare columns (five spare column blocks) are required for successful replacement using our CBR approach. Since faulty blocks occur at four different columns, four redundant columns are required for traditional replacement approaches. It is evident that the approach will result in better repair efficiency and the cnst to achieve the specified yield level is minimised.

Fig. 3 shows the general built-in self-repair (BISR) architecture for DBL memories. The core memory array has

:. ............................ i memolycell i

word line

sub bn lin

I ............................ Column block

Fig. 1

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Divided bit-line (DBLJ struclure

redundant memory array mlumn ...................................... _.

bank3 i

CBS, j ..A.

bank2

CBS, ......

bank1

CBS, ......

bank0

CBS, ...... Bo B1 B, 0, SC, SC,

Fig. 2 Simple concept of column_block_repair scheme

n word lines (WO. . . Wn-,), m hit-lines, and a column bank select (CBS, . . . CBS._,) lines. Besides, the memory con- tains c spare columns (SC, ... SC,-,). In this paper, the FCB (faulty column bank) CAM (content addressable memory) block (stores and compares the column and bank addresses of faulty column blocks) is added into the DBL architecture to achieve fault tolerance for high-capacity memories. The FCB CAM block (Fig. 4) contains two fields: the FC field and the BA field. The column addresses and column bank addresses of the faulty blocks are stored in the FC field ( y bits, y = log2m) and the BA field (logza bits), respectively. Th.e FCB CAM block is divided into c sub CAM blocks (SUB,,SUB,, ... ,SUB<_,). The column address and bank address of the ith faulty block in column bank j is stored in the jth address of SUB, (FCBA,, j ) .

Therefore each subblock contains a words. A brief scenario of the BISR approach is described as follows. When a memory cell is accessed in the normal mode, the column address and bank address is sent to the FCB CAM block to check whether the memory cell is faulty or not. If a match comes from SUB,, the match spare column (MSC,) signal is used to activate the spare column X i . Moreover, these match spare column signals are ORed to generate the global match signal (GMS) used to disable the normal bit-lines. After that, the specified spare column block will replace the faulty column block, i.e. the accessed data could be read or written regularly.

If there are faulty blocks detected in a memory array, the approach assures that faulty blocks are disabled and spare blocks are enabled simultaneously. Consequently the CBR approach can be implemented easily to replace faulty blocks with spare blocks. The memory system never stops its operation during the repair operation, i.e. the replacement is transparent to the user. Since the column addresses are sent to the FCB CAM block and the original column decoder, they are decoded simultaneously. Moreover, the FCB CAM block usually has faster decoding speed then the original column decoder (e.g. tree-based decoder). Therefore, address remapping will not suffer from significant perfotn- a c e penalty. In addition, the added components for our approach can be implemented with simple circuits and the hardware overhead is relatively low.

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OBL architecture ..................................... sco

CO c, CY?

Fig. 3 BISR architecture of DBL memories

a: no. of bank select lines (BS); n: no. of word lines ( x = logn); c: no. of spare columns (SC); x: no. of row address bit: y : no. of column address bit.

column and bank addresses

SUB, SUB,

Fig. 4 FCB CAM block

3 CBR algorithm

The flow chart of the spare reconfiguration approach is shown in Fig. 5 . When the test session is activated, faulty addresses will he stored in the FCB CAM block immedi- ately after their detection during test. These include the column address and the bank address of a faulty block. At the same time, the test session is suspended temporarily. However, the algorithm will count the number of faulty blocks in the same bank to examine whether the number of faulty blocks exceeds the number of spare columns. If this situation does not occur, the column addresses and bank addresses of all faulty blocks are stored into the FCB CAM block. It means that these faults can be repaired success- fully. If this situation occurs, the error signal is activated and faulty addresses are not stored into the FCB CAM block. In other words, these faulty blocks can't he replaced with spare blocks in the same hank. The entire BIST session, storing of faulty addresses and generation of error signal are supervised by the BIST controller. In general, the BIST controller is implemented with a processor-based BIST controller [7] or a hard-coded finite-state machine [3].

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When a conventional memory access is started, the bank address and column address are both sent to the FCB CAM block and compared with the addresses in the FCB CAM block. If it matches, the memory fault has been detected and can be repaired. Therefore the match signal can he used to disable the normal bit-lines. Moreover, one can enable the spare columns to readlwrite correct data. This means that faulty blocks can he repaired successfully. If it dose not match, this situation means that there is no failure during the memory access operation. Therefore normal memory access can he executed.

3.1 An example The memory array includes eight bit-lines, 16 word lines, and four column hank select lines, as shown in Fig. 6. That is, each column of the memory m a y is divided into four column blocks. Moreover, two spare columns are added as redundant. Let FB, denote the address of a faulty block, i be the column address and j be the bank address. Fig. 6a shows the hitmap of the memory array. There are totally seven faulty blocks (containing 12 faulty cells) in the memory array, including FE,,, FB,,, FE,,, FE,,, FB,,, FB,,,

203

memory functional testing

(include spare columns). get Its

store column address and bank address into FCB CAM block

and count number of faulty blocks

faulty blocks in bank exceed no. Of

memory access v bank Selection lines activate

CAM block

are column

FCB CAM block?

I

send match signal, disable normal bit lines and enable

spare column block

repair faulty blwks successfully

activate error signal lo indicate that memory chip Cannot be repaired

Fig. 5

and FB,,. The content of FCB CAM block is presented in Fig. 6c according to the CBR algorithm. Since there are three faulty blocks in bank 2, the first two faulty blocks, FEzz and FE,,, are stored in SUB, and SUB,, respectively. Unfortunately, FB,, is unrepairable in this example. Figure 66 shows the final spare allocation. The greyed blocks in the memory array mean that spare blocks repair the faulty ones successfully.

4 Hardware overhead and repair rate

4. I Hardware overhead evaluation

N o w chart of spare allocation

Since the fault-tolerant architecture is based on the DBL architecture, most of the control circuits are available anyhow. These can be seen as the default components for the DBL architecture [I91 and will not he taken into account for hardware overhead evaluation (e.g. switching transistors).

The main hardware overhead comes from the FCB CAM block. The hardware overhead can he defined as the ratio between the extra transistor count of the FCB CAM block and the transistor count of the whole memory array (HO,,). Since the number of CAM cells in the FCB CAM block is very small as compared with the memory array. Therefore the hardware overhead is almost negligible.

In Fig. 4, y bits and logz a bits store column addresses and bank addresses of the faulty column blocks in an FCBA field, respectively. One bank has c FCBA fields, i.e. there are c x a FCBA fields in the FCB CAM block. It is assumed that nine-transistor CAM cells as shown in Fig. 7 1271 are used. One standard SRAM cell contains six transistors and one DRAM cell contains only one transistor. The hardware overhead is estimated as follows:

(1) c X a x iy + logza) x 9

n X ( m + c ) x 6 H e % =

The hardware overhead ratios of the CAM block relative to the total memory capacity are presented in Table 1.

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The symbol “n*m” denotes that a memory array consists of n rows and m columns. In this table, the memories are divided into 8 and 16 banks, respectively. From this Table the hardware overhead decreases as the number of columns increases. From the evaluated. results it is found that negligible hardware overhead is required to achieve fault tolerance. According to the simulated results, the hardware overheads are less than 0.58% and 0.012% for 256-Kbit SRAMs and 8-Mbit DRAMs, respectively.

According to the simulation results shown above, the features of the CBR algorithm based on hardware overhead are summarised as follows. First, the proposed approach is more suitable for high-capacity memories, SRAMs and DRAMs. Secondly, if there are more banks in a memoly array, that is, there are more blocks in a memory column, the hardware overhead will increase significantly. However, more memory blocks will result in higher repair rate, described subsequently. Thirdly, if the number of memory word lines is much greater than that of the bit-lines, the overhead will decrease significantly. Another advantage of this characteristic is the enhancement of repair rate. In other words, the CBR approach is more suitable for memories which have more word lines. Finally, the ratio of hardware overhead of the CAM block relative to total memory capacity is 0.58% for SRAMs and 0.012% for DRAMs. The hardware overhead is still low even taking other reconfi- guration components (such as switches for enabling and disabling of redundant columns) into account. In the future, the advantage of the CBR scheme would become more apparent in high-density memories.

4.2 Repair rate The repair rate is defined as the probability of successful reconfigurations. In the simulation, random cell faults are injected into a memory cell array. Certainly, the injected faults must be first detected by the BIST session. The number of injected faults may be too many to he repaired by the redundancies. A 64Kb memory array which has 128 word lines and 512 bit-lines was used in the simulation. Furthermore, the number of banks is assumed to be 4 and 8,

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spare Cd"!T"S

CO c, c, c, c, c, c, c, sc, sc, (a)

Spare

........................

.........................

......................... ........ mm ..........................

........

........

........ CO c, c, c, c, c, c, c, SC, sc,

(b) m r l 6

(C)

Fig. 6 Memory array a Bitmap b Spare allocaion of memory anay c Content of FRB CAM block

bit' I &- w match I I I

Fig. 7 CAM cell " x r e

respectively. Fig. 8 compares the repair rates between Repair-Most (Rh4) [16] algorithm and CBR algorithm. The RM algorithm consists of the must-repair phase and the final-repair phase. The must-repair phase repairs faulty cells that can only be repaired by redundant rows or columns, respectively. The final-repair phase repairs the remaining faulty cells which can he repaired by either redundant rows or redundant columns. Error counters for the faulty rows and columns are required during the analysis. That is, the RM algorithm repairs the faulty memories by spare rows and columns. For illustration, about 0.26 random cell faults were injected in the memory array for this analysis. In Fig. 8 the number of spares 'c (n*m)' means CBR algorithm that has c spare columns and RM algorithm that has n spare rows and m spare columns, i.e. c = n + m. Fig. 9 shows the repair efficiency of these two algorithms. The repair efficiency is defined as the number of redundancies required to achieve expected repair rate level. It is assumed that the expected repair rate level is up to 90% and inject about 0.4% random cell faults in the memory array. Simulation results are shown in Fig. 9. It is obvious that the proposed approach has high repair efficiency.

Several properties are derived during the analysis. The first is that the CBR algorithm has a higher repair rate than the RM algorithm. The second is that the repair rate of CBR (8BS) algorithm is higher than the CBR (4BS) algorithm. In other words, if there are more banks in the memory array, i.e. more blocks in a column, more faulty cells can he repaired successfully. However, increasing the number of blocks may result in the bit-line delay [20-24). In other words, it is a tradeoff between repair rate and bit-line delay.

Table 1: Hardware overhead ratios of CAM block (Hoarray, unit: X)

256K (256 x 1024) SRAM

c = 1 c = 2 c = 3 c = 4 c = 5

-

DRAM c = 1 c = 2 c = 3 c = 4 c = 5

8 BS 16 BS

0.355 0.765 0.413 0.891 0.472 1.017 0.531 1.144 0.589 1.269

8M (512x16384) 8 BS 16 BS 0.002 0.005 0.005 0.01 0.007 0.015 0.009 0.021 0.012 0.026

~ ~~

512K (512x1024) 8 BS 16 BS

0.178 0.382 0.207 0.446 0.236 0.509 0.266 0.572 0.295 0.635

16M (1024x16384) 8 BS 16 BS 0.001 0.003 0.003 0.005 0.004 0.007 0.005 0.01 0 006 0.013

512K(256x2048) 8 BS 16 BS

0.191 0.411 0.224 0.479 0.255 0.547 0.287 0.615 0.319 0.683

16M (512x32768) 8 BS 16 BS -0 0.001 0.001 0.003 0.002 0.004 0.003 0.005 0.003 0.007

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100 U R M OCBR (485) MCBR (80s)

90 8. 80 _m e 7Q

$ 60 e 50

40 6 (5'1) 7 ( 5 2 ) 8 (6.2) 9 (7'2) 10 (7.31

number of spares

Fig. 8 Repair rates of RM and CBR algorithms

expected repair rate '90%.

g, 16

Q g 8

1: 0

2.g 12

Fs 4

RM BR (485) BR (80s) repair dgorithm

Fig. 9 Repair eficiency of RM and BR algorithms

Moreover, our CBR algorithm has higher repair efficiency than the repakmost algorithm. Hence, we can use less redundancy to replace faulty memory cells. In summary, if the number of faults detected during the BIST session is large for a memory array, one can use more bank select lines to enhance the repair rate. However, more blocks in a memory column may result in higher hit-line delay and hardware overhead. Therefore one must choose the optimal number of memory banks to achieve maximal repair rate and minimal hardware overhead.

5 Yield analysis

To project the yield of a given RAM design, three assumptions are made to simplify our yield analysis. First, assume all failures on the memory chip as the results of spot defects. Secondly any single spot defect will result in the chip being inoperative unless some types of redundancy are included. The final assumption is that spot defects are randomly distributed. The memory m y used in the analysis contains n rows, m columns, and c redundant columns are added. Each column is partitioned into a blocks. In other words, each block contains d a memory cells. The reconfiguration mechanism is shown in Fig. 3. Assume that each block has an area A and the defect density function is denoted as D. Uniform distribution with magnitude l / D n between 0 and D, for the defect density is assumed. The Poisson yield model [25, 261 is used in the analysis. Therefore the yield of nonredundant memory array is computed first as

(3)

Now consider the situation where the reconfiguration is performed at the column level. That is, an entire redundant column is used to replace a faulty column. The probability of a complete column being fault free is

pco/ = e-DAa (4)

The probability that m of the m + c columns in the array will be free of fault can be expressed as

206

( 5 ) m + c

If the reconfiguration coverage C is also considered, it can be rewritten as

The area of the control circuit for the column-based approach is aA, where 01 denotes the complexity factor of the control circuit. The probability of the control circuit being fault-free is

(7) C e - D d P d =

Furthermore, the probability of obtaining a fault-free memory chip is

(8) C P!ol = P:d Pcol

Similarly, the yield of the column-based memory array can be calculated as

(9)

Now turn to the situation where reconfiguration is performed at the column block level. For the memory array to work correctly, m blocks must be reconfigured for each bank. The objective is to replace column blocks containing faulty cells with the spare blocks in the same bank so that an operational array can be obtained. The probability for a memory block to be fault-free is

Phr = KDA (10)

Next, calculate the probability that m of the m + c blocks in a bank will be fault-free. Similarly, this probability can be written as

If the reconfiguration coverage C i s also considered, then pb can be rewritten as

Finally, the probability that all the banks have sufficient blocks to make them completely operational can be written as

PZ = (pdY (13) To achieve an operational memory array, the reconfigura- tion mechanism (control circuitry) must also be fault-free. Assuming that the reconfiguration hardware has an area of PA, the probability of the reconfiguration hardware being fault free is

(14) pz ,-DM

According to the analysis, the probability to obtain a functionally correct memory array is

P i = PgPz (15)

The yield of the redundant memory array can be calculated as

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The yield improvement of the block-based approach over nonredundant and column-based memory array is expressed as YII and YI2, respectively. Then they can he evaluated as

(18) Ybr Y12 = -

The yield improvements are plotted in Figs. 10 and 11 for SRAM and DRAM, respectively. They are expressed as a function of the reconfiguration coverage C, the area complexity of the reconfiguration hardware, and the product of defect density and chip area. We also assume that the memory size is 512*128 (64K) hits, c = 8, and C = 0.9.

In Fig. 10 the yield improvement of SRAM is significant with the approach. In particular, the yield improvement increases rapidly as the defect density increases. For example, YIl = 8.26 and Y12 = 1.41 if D.Aam = 30 and a = 4. Note in Fig. IO that Y12 is less than 1 for low defect density. It means that the CBR algorithm is worse than the column-based technique. This is especially true when the defect density is very low. This is due to the reconfiguration coverage C and the extra added reconfiguration mechan- isms. It is obvious that the reconfiguration mechanisms are more complex than that for the column-based technique. When the defect density is low, the benefits of CBR algorithm will be balanced by its reconfiguration mechanisms. Therefore for high defect density, the CBR

Y,Ol

Yf1 a = 4 Yfi 8 1 8

0.91 0 5 10 15 20 25 30 Produaofdefendensity andlolalchipareaDnxAxmxa

(b)

Fig. 10 c = 8, and C = 0.9 (I YI1 b Y12

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Yield improvemem of 64K hi! (512 X 128-hit) SRAM,

' Y f l a = Z Y f l a = 4

6

E 5

B 9 4 E I! .% 3 >

.-

2

1

/----

.E \:E 0.9 , 9 F 0.8

0.7 Y f 2 a = 6 y'2a= 16

0 5 10 15 20 25 30 0.6

Prcduct Of defect density and total chip area Dnv A r m x a (b)

Fig. 11 C = 0.9 U YI1 b YIZ

Yield impruvemenf of512 x IZS-bit DRAM, c = 8, ond

algorithm will get higher yield than the column-based approach as shown in Fig. IO. Similarly, the yield improvement is YI1 = 6.64 and Y12 = 1.18 for DRAM with a = 2 as shown in Fig. 11. From the simulated results notice that the yield improvement of SRAM is superior to DRAM. This is because the control circuit of DRAM suffers from higher hardware overhead than that of SRAM. Moreover, if the hank number of DRAM increases, the yield improvement will he less than the column-based approach. In practical applications, tradeoffs should he made to find the optimal number of hanks and achieve maximum yield improvement.

6 Conclusions

A CBR fault-tolerant architecture based on the character- istics of DBL memory has been proposed for high-capacity memories. The memory cell arrays went into divided blocks and redundancies are added at the block level. The fault- tolerant architecture improved the yield for memory fabrication significantly. According to experimental results, the hardware overhead of the CBR architecture is less than 0.58% and 0.012% for 256-Khit SRAMs and 8-Mhit DRAMS, respectively. The repair rate of the approach is compared with previous memory repair algorithms. The CBR approach improved the repair rate significantly. According to the calculated results, if the number of detected faults is large for a memory array, one can use more hanks for enhancing the repair rate. However, more blocks in a memory column may result in higher bit-line delay and hardware overhead. Therefore one must choose the optimal number of hanks to achieve maximal repair rate

207

and minimal hardware overhead. The yield improvement over traditional column-based approaches was also ana- lysed. Simulation results showed that the approach could improve fabrication yield significantly.

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