IEEE CAS(M) Hi‐Tea 2013 16/7/2013

19 June 2013, Residence Hotel, Malaysia 1

Fawnizu Azmadi Hussin / Universiti Teknologi Petronas

RESEARCH THEMESFawnizu Azmadi HussinBEE (Minnesota, USA), MEngSc (UNSW, Australia), D.Eng. (NAIST, Japan)

Associate ProfessorElectrical & Electronic Engineering DepartmentUniversiti Teknologi PETRONAS

fawnizu@ieee.orgfawnizu@petronas.com.my+6010 - 226 3857

https://sites.google.com/site/fawnizu

16/7/2013 1

Fawnizu Azmadi Hussin / Universiti Teknologi Petronas

In-Situ Functional Debug of IC

WBY

WIReWSI

eWSO

MISRs

Register

Tester

iROBOT

WBR

eWSP

iWSP

MISRs

Register

WBR

WBR

WBR

Control

ALUIEEE1500 wrapper

IR

Register files

PC

Data Pathcontroller

Databus

Controlbusn

8WSP

nTestbus

iWSP

n

2Int_ext_test

Orignal Processor

Controlsn

Funded under E-Science (03-02-02-SF0141)

16/7/2013 2

IEEE CAS(M) Hi‐Tea 2013 16/7/2013

19 June 2013, Residence Hotel, Malaysia 2

Fawnizu Azmadi Hussin / Universiti Teknologi Petronas

Structural Representation of RTL Module

Fault Excitation

Response Propagation

Sequential ATPG

Test Pattern Instructions Program

Funded under E-Science (03-02-02-SF0141)

Functional Test Program Generation16/7/2013 3

Fawnizu Azmadi Hussin / Universiti Teknologi Petronas

Paths Implications

Rd[t] → (Rc[t], ‘+’[t]) P => (‘+’[t] = Rd[t])~P => (Rc[t] = Rd[t])

‘+’[t] → ( Ra[t], Rb[t])(‘+’[t] = Ra[t])( ~ Rb[t])

+(‘+’[t] = Rb[t])( ~ Ra[t])

For state S0 S0 => (P = ‘0’)

RTL Module Structural

Representation

Module Implications

I/O Rules for Response

Propagation

Boolean Constraint

Propagation (BCP) Engine

Formal Method for Testing

Test Pattern Instructions

Program

Functional Test Program Generation

Funded under E-Science (03-02-02-SF0141)

16/7/2013 4

IEEE CAS(M) Hi‐Tea 2013 16/7/2013

19 June 2013, Residence Hotel, Malaysia 3

Fawnizu Azmadi Hussin / Universiti Teknologi Petronas

Digital Architecture on FPGA

Small Area

Low Latency

High Throughput

(Min 1Gbps)

Encoder Architecture

Design

High Code Rate Encoder

• • •

●

1

Clock

(1 x K) Information bits

(s)

Reset

● ●

●

●

Parity bits

●

●

• • •

●

●

●

Row 1

Row 2

Row mP

1

1

1

1

1

1

1

1

1

● ●

BXOR

m(P '(x, y))

C O D E W O R D c

P'

Sub-matrix P

Hardware Part Software Part

Proposed H

• • •

P''

Architecture Design

Hardware

Simulation and Validation

Encoding Method and Parity Check Matrix (H)

An Example of Proposed Architecture

Results of Proposed Architecture

[5] S. Kopparthi and D. M. Gruenbacher, “Implementation of a flexible encoder for structured low-density parity-check codes,” IEEE PacificRim Conference on Communications, Computers and Signal Processing (PacRim 2007), pp. 438-441, Aug. 2007.[6] J. K. Kim, H. Yoo and M. H. Lee, “Efficient encoding architecture for IEEE 802.16e LDPC codes,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol E91-A, pp. 3607-3611, Dec. 2008.[7] Chia-Yu Lin, Chih-Chun Wei and Mong-Kai Ku, “Efficient encoding for dual-diagonal structured LDPC codes based on parity bit prediction and correction, ” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008), Macao, China, Nov.-Dec. 2008.

LDPC

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Fawnizu Azmadi Hussin / Universiti Teknologi Petronas

Bio-inspired Network on Chip (NoC)

Biological Brain BNoCNeuron PEAxon InterconnectNeuron & Axon (for information processing)

PE & Interconnect

Biological Algorithms Router, NI & Interconnects

Synaptogensis, Dynamic Brain, Synapse rearrangement Self-adopt

Sprouting, Use Redundant PE’s/Router/Interconnects Self-heal

Neuron growth factor, Synapse rearrangement, Dynamic brain Self-optimization

Funded under FRGSFRGS 2/2010/TK/UTP/02/20

16/7/2013 6

IEEE CAS(M) Hi‐Tea 2013 16/7/2013

19 June 2013, Residence Hotel, Malaysia 4

Fawnizu Azmadi Hussin / Universiti Teknologi Petronas

Android based DR Grading system

Automated DR system in Standalone Devices (Android device)

Automated DR system in PC (MATLAB)

ophthalmologists Manual Analysis

DR Severity

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Fawnizu Azmadi Hussin / Universiti Teknologi Petronas

Android Solution

Platform porting

Library optimization

Application development

Boot loader

Render-script

Kernel

4.0

2.1

4.12D

3D

Math

DR

Multi-core

Patent pending “Portable Grading Apparatus”. (MyIPO Patent File Number: PI2013700739. Filed on 07 May 2013)

Enabling Rapid Signal/Image Processing Application DevelopmentIn Android

16/7/2013 8

IEEE CAS(M) Hi‐Tea 2013 16/7/2013

19 June 2013, Residence Hotel, Malaysia 5

Fawnizu Azmadi Hussin / Universiti Teknologi Petronas

Contact• Fawnizu Azmadi Hussin • E-mail: fawnizu@ieee.org

fawnizu@petronas.com.my+6010 – 226 3857

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