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Chapter 3Chapter 3
The concept of the signalThe concept of the signal Process concurrencyProcess concurrency Delta timeDelta time Concurrent and sequential statementsConcurrent and sequential statements Process activation by a signal eventProcess activation by a signal event Signal-valued & signal-related attributesSignal-valued & signal-related attributes ExercisesExercises
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The concept of the signalThe concept of the signal
Signal functions as connection line which transfers information between circuit partsSignal properties• present and future values• timing delay• event and transaction• signal driver and signal resolution
Multiple driversMultiple drivers
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Process concurrencyProcess concurrency
NANXOR codeNANXOR code entity NANDXOR isentity NANDXOR is
port (port (
A, B : in bit;A, B : in bit;
C : in bit;C : in bit;
D : out bit);D : out bit);
end NANDXOR;end NANDXOR;
architecture RTL of NANDXOR isarchitecture RTL of NANDXOR is
signal T : bit;signal T : bit;
beginbegin
p0 : T <= A nand B after 2 ns;p0 : T <= A nand B after 2 ns;
p1 : process (T, C)p1 : process (T, C)
beginbegin
D <= T xor C after 3 ns;D <= T xor C after 3 ns;
end process p1;end process p1;
end RTL;end RTL;
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Process concurrencyProcess concurrency
Signal T:bit;Signal T:bit;
Defines T as the Defines T as the connectionconnection signal between NAND and OR gates. signal between NAND and OR gates.
Initialization: signals set to their Initialization: signals set to their defaultdefault (left most for their type) (left most for their type) valuesvalues
Each process is Each process is evaluatedevaluated and then and then suspendedsuspended
T AB and D T C
Active Suspended
Running
Select a process by a scheduler
Signal event Update signal value
Execution complete
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Process concurrencyProcess concurrency
architecture RTL of NANDXOR is signal T : bit;begin p0 : T <= A nand B after 2 ns; p1 : process (T, C) begin D <= T xor C after 3 ns; end process p1;end RTL;
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Delta timeDelta time
architecture DELTA of NANDXOR is signal T : bit;begin p0 : T <= A nand B; p1 : process (T, C) begin D <= T xor C; end process p1;end DELTA;
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Delta timeDelta time
Compare Figures 3.5 & 3.6Compare Figures 3.5 & 3.6
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Delta timeDelta time
Waveforms at time 30Waveforms at time 30
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Delta timeDelta time
Delta timeDelta time
Processes p0, p1 have no time delay, Processes p0, p1 have no time delay, but if the simulator continues to but if the simulator continues to increase the delta delay, the delta goes increase the delta delay, the delta goes up infinitely and the simulator may go up infinitely and the simulator may go into an into an infinite loopinfinite loop..
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Concurrent & sequential statementsConcurrent & sequential statements
Concurrent statementsConcurrent statements Sequential statementsSequential statementsif statement
case and loop statements
procedure call statement
assert statement
signal assignment statement
variable assignment statement
null, exit, and wait statements
return and next statements
block statementprocess statementgenerate statementprocedure call statementassert statementsignal assignmentcomponent instantiation
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Concurrent & sequential statementsConcurrent & sequential statements
VHDL coding rulesVHDL coding rules Only Only concurrent statementsconcurrent statements can be inside the can be inside the architecture architecture
statementstatement part. part. Sequential statementsSequential statements can only appear inside the procedure can only appear inside the procedure
and function body and inside the process statement.and function body and inside the process statement. SignalsSignals are used to are used to communicatecommunicate among concurrent among concurrent
processes.processes. Local variablesLocal variables can only be declared inside the procedure can only be declared inside the procedure
and function body and the process statement. They are and function body and the process statement. They are notnot visiblevisible outside of the procedure, function, and process outside of the procedure, function, and process statement.statement.
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Concurrent & sequential statementsConcurrent & sequential statements
Architecture VHDL codeArchitecture VHDL code
entity OVERALL isend OVERALL
architecture RTL of OVERALL is --architecture declarative partbegin --architecture statement partend RTL;
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Concurrent & sequential statementsConcurrent & sequential statements
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Process activation by a signal eventProcess activation by a signal event
architecture architecture SLISTSLIST of of NANDXOR isNANDXOR is
signal T : bit;signal T : bit;
beginbegin
p0 : T <= A nand B;p0 : T <= A nand B;
p1 : p1 : processprocess ( (TT))
beginbegin
D <= T xor C;D <= T xor C;
end process p1;end process p1;
end SLIST;end SLIST;
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Process activation by a signal eventProcess activation by a signal event
T is the T is the sensitivity listsensitivity list of the p1 process (line 5 of SLIST of the p1 process (line 5 of SLIST architecture). architecture).
Process is Process is activatedactivated by a signal T by a signal T event.event.
A process statement requires an explicit A process statement requires an explicit waitwait statement statement or a process or a process sensitivity listsensitivity list but not both. but not both.
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Process activation by a signal eventProcess activation by a signal event
Wrong simulation waveforms of the SLISTWrong simulation waveforms of the SLIST
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Signal-valued & signal-related attributes
Signal-valued & signal-related attributes
SIG’delayed(T)SIG’delayed(T) defines a defines a signalsignal which is the which is the signal SIGsignal SIG delayed by time T. T=0 ns is the default if parameter T delayed by time T. T=0 ns is the default if parameter T is not specified. is not specified.
SIG’stable(T)SIG’stable(T) defines a defines a BOOLEAN signalBOOLEAN signal whose value whose value is TRUE if signal SIG has not had an event for the is TRUE if signal SIG has not had an event for the length of time T. T=0 ns is the default if parameter T is length of time T. T=0 ns is the default if parameter T is not specified. not specified. SIG’stableSIG’stable would be FALSE during the would be FALSE during the simulation cycle when SIG is changed and then returns simulation cycle when SIG is changed and then returns to TRUE. to TRUE.
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Signal-valued & signal-related attributes
Signal-valued & signal-related attributes
SIG’quiet(T)SIG’quiet(T) defines a defines a BOOLEAN signalBOOLEAN signal whose value whose value is TRUE if signal SIG has not had an transaction (not is TRUE if signal SIG has not had an transaction (not active) for the length of time T. T=0 ns is the default. active) for the length of time T. T=0 ns is the default. SIG’quietSIG’quiet would be FALSE during the simulation cycle would be FALSE during the simulation cycle when SIG is assigned to and then returns to TRUE.when SIG is assigned to and then returns to TRUE.
SIG’transactionSIG’transaction defines a defines a BIT signalBIT signal whose value whose value toggles each time a transaction occurs on signal SIG.toggles each time a transaction occurs on signal SIG.
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Signal-valued & signal-related attributes
Signal-valued & signal-related attributes
SIG’eventSIG’event is a is a BOOLEAN BOOLEAN typed attribute. It is true if typed attribute. It is true if an event occurs on signal SIG during the current an event occurs on signal SIG during the current simulation cycle.simulation cycle.
SIG’activeSIG’active is a is a BOOLEANBOOLEAN typed attribute. It is true if typed attribute. It is true if a tranction occurs on signal SIG during the current a tranction occurs on signal SIG during the current simulation cycle.simulation cycle.
SIG’last_eventSIG’last_event is a is a TIME TIME typed attribute. It returns typed attribute. It returns the amount of time elapsed since the last event on the amount of time elapsed since the last event on signal SIG.signal SIG.
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Signal-valued & signal-related attributes
Signal-valued & signal-related attributes
SIG’last_activeSIG’last_active is a is a TIMETIME typed attribute.It returns typed attribute.It returns the amount of time elapsed since the last transaction on the amount of time elapsed since the last transaction on signal SIG.signal SIG.
SIG’last_valueSIG’last_value returns the returns the valuevalue of signal SIG before of signal SIG before the last event on signal SIG.the last event on signal SIG.
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ExercisesExercises
entity RUNAWAY isentity RUNAWAY is
port (port (
X : in bit;X : in bit;
Z : out bit);Z : out bit);
end RUNAWAY;end RUNAWAY;
Is it possible for a VHDL simulator to run forever without advancing simulation time? For example, Figure 3.13 shows a NAND gate with its output connecting to one of its inputs
architecture RTL of RUNAWAY isarchitecture RTL of RUNAWAY is signal T : bit;signal T : bit;beginbegin T <= X nand T;T <= X nand T; Z <= T;Z <= T;end RTL;end RTL;
