48
Characterization of SiGe Nanowire for Thermoelectric Applications KATAYOUN ZAHMATKESH ENCHEH KEIKANLOU Master of Science Thesis Stockholm, Sweden 2015
Characterization of SiGe Nanowire for
Thermoelectric Applications
KATAYOUN ZAHMATKESH ENCHEH KEIKANLOU
Master of Science Thesis Stockholm, Sweden 2015
Characterization of SiGe Nanowire for
Thermoelectric Applications
Katayoun Zahmatkesh Encheh Keikanlou
Thesis for the Degree of
Master of Science
Functional Materials Division
School of Information and Communication Technology (ICT)
Royal Institute of Technology (KTH)
Stockholm, Sweden
Dec, 2015
Postal Address Royal Institute of Technology (KTH)
Functional Materials Division, School of ICT
Electrum 229, Isafjordsgatan 22
SE-164 40 Stockholm, Sweden
Supervisor Docent Henry H. Radamson
Examiner Prof. Muhammet S. Toprak
Tutor Mohammad Noroozi
TRITA-ICT-EX-2015:247
i
Abstract
Thermoelectric devices directly convert heat into electricity or vice versa through simple structures
without moving parts. SiGe materials are promising candidates for thermoelectric energy
conversion.
This study presents the electrical characterization of p- and n-type Si0.53Ge0.47 alloy nanowires
(NWs) with an average diameter of 60 nm in the temperature range of 248 K to 473 K. The SiGe
NWs were fabricated by two methods: Sidewall Transfer Lithography (STL) and conventional I-
line lithography followed by Focus Ion Beam (FIB) thinning. A new approach was developed to
characterize the electrical and thermal properties of the NWs.
The SiGe material was grown by Reduced Pressure Chemical Vapor Deposition (RPCVD) using
SiH4 and GeH4 precursors on Silicon on Insulator substrates (SOI). These samples were then
condensed to Si0.53Ge0.47 layers. Doping of layers was performed through diffusion with two
different sources gas of B2H6 or PH3 at 800°C. The electrical conductivity and thermopower of the
SiGe NWs, fabricated by both methods, were studied and compared. The results showed an
enhancement of thermopower, electrical conductivity and power factor of SiGe NWs compared to
Si NWs, revealing their potential for thermoelectric material (TE) device applications.
ii
Acronyms
ALD Atomic Layer Deposition
Bi Bismuth
B Boron
CVD Chemical Vapor Deposition
CMOS Complementary Metal Oxide Semiconductor
CoSb3 Cobalt Triantimonide
FIB Focus Ion Beam
IrSb3 Iridium Triantimonide
Ga Gallium
Ge Germanium
NWs Nanowires
RIE Reactive- Ion –Etchin
P Phosphorus
Sb Antimony
SEM Scanning Electron Microscopy
Si Silicon
SiGe Si Germanium
SIMOX Separation by Implantation of Oxygen
SGOI SiGe-On-Insulator
SOI Silicon-On-Insulator
STL Sidewall Transfer Lithography
SVR Surface area to Volume Ratio
RIE Reactive-Ion-Etching
Te Tellurium
Ti Titanium
TMAH Tetra methyl ammonium hydroxide
XRD X-Ray Diffraction
iii
Acknowledgement
I would like to thank my supervisor Docent Henry H. Radamson for his support and discussions
around the project and for giving me a great deal of knowledge of semiconductors. He motivated
me to do my very best work.
I would like to thank Professor Muhammet S. Toprak for giving me the chance of doing my master
thesis with him and his friendly group of the Functional Material division (FNM) and for his
continuous assurance and support during my thesis.
I would like to thank my Co-supervisor Mr. Mohammad Noroozi for all the help and invaluable
guidance he provided me with. I would also like to thank my friend Bejan Hamawandi and all of
my friends who helped me from the beginning to the end of my thesis.
And finally I would like to thank my family for always being there. In addition, I thank Dr. Nader
Hozhabri for his support and encouragement during my education. I want to express my gratitude
to my husband Arash Hojabri for all his love and support.
iv
List of figure
Figure 1.TE power generation and TE refrigeration systems ............................................................................ 1
Figure 2. The carrier distribution over the cold side until an electric field (E) is established ........................... 3
Figure 3. The derived ZT of a thermoelectric device shows the thermal conductivity, Seebeck coefficient,
and electrical conductivity ................................................................................................................................. 4
Figure 4. (a) Decreasing thermal conductivity according decreasing size of NW (b) increasing Zt value for Si
NW with 37nm thickness .................................................................................................................................. 5
Figure 5. The electronic band gap shift for Si(1-x)Ge(x) NWs vs Ge content from 0 to 1 ................................... 7
Figure 6. Ge condensation at High Temperature Oxidation. ............................................................................ 10
Figure 7. Schematic of an optical lithography system. .................................................................................... 11
Figure 8. Fabrication of SiGe-On-Insulator (SGOI) by condensation technique. ............................................ 13
Figure 9. XRD rocking curve of epi-SiGe before and after condensation. ...................................................... 14
Figure 10. SEM image of the fabrication device. ............................................................................................. 14
Figure 11. (a) Shows initial NWs (b) demonstrates 34 NWs after being cut plus NWs that remained intact. . 15
Figure 12. (a) Three SiGe NWs with thickness 1000nm (b), (c) SEM image of one of the SiGe NW thinned
down to 60nm. .................................................................................................................................................. 15
Figure 13. (a-h) Schematic of process steps of NWs using STL method ........................................................ 16
Figure 14. SEM image of final NWs with 60 nm width and 22µm length. ..................................................... 17
Figure 15. Structure of device that consists of 8 contact pads, one heater and SiGe NWs that are contacted to
the pads. ............................................................................................................................................................ 18
Figure 16. (a), (b) Show the schematic of resistance measurement using four probe station (c) demonstrates
the schematic of the resistance measurements using two probe station. .......................................................... 19
Figure 17. Resistance measurements by four probe station and two probe station for contact resistance
measurement. .................................................................................................................................................... 20
Figure 18. Parallel resistance equation for identical NWs. .............................................................................. 20
Figure 19. Schematic of the power generation with thermal energy in NWs................................................... 21
Figure 20. Resistance difference for NW when heater is off and on. ............................................................... 23
Figure 21. Voltage difference at room Temperature for NW when Heater is off and on. ............................... 23
Figure 22. Cycle resistance measurement of NW in three range voltage (-1, 1), (-0.5, 0.5), (-0.1, 0.1). ......... 25
Figure 23. Decreasing resistance of SiGe NW after deposit a 20nm oxide layer. ........................................... 26
Figure 24. Resistance measurement of SiGe NW after thinned down with different current Ga beam vs time.
.......................................................................................................................................................................... 27
Figure 25. Resistance values verses 1/width of the SiGe NWs downscaled by FIB. ....................................... 27
Figure 26. Resistance measurements of SiGe NWs by changing of temperature. ........................................... 29
v
Figure 27. Conductivity for (a) P-type; (b) N-type, Seebeck for (c) P-type; (d) N-type, Power factor for (e) P-
type; (f) N-type. ................................................................................................................................................ 30
Figure 28. Schematic of a Scanning Electron Microscopy(SEM) ................................................................... 36
Figure 29. Schematic of X-ray system. ............................................................................................................ 37
Figure 30. Keithley 4200-SCS Parameter Analyzer . ....................................................................................... 38
vi
Table of Contents Abstract ............................................................................................................................................................... i
Acronyms ........................................................................................................................................................... ii
Acknowledgement ............................................................................................................................................. iii
List of figure ...................................................................................................................................................... iv
1. Introduction .................................................................................................................................................... 1
1.1 Thermoelectric phenomena and applications ........................................................................................... 1
1.2 Seebeck and Peltier Effects ...................................................................................................................... 2
1.3 Figure of merit .......................................................................................................................................... 2
1.3.1 Monitoring Seebeck coefficient and electron conductivity ............................................................... 3
1.4 Tailoring thermal conductivity ................................................................................................................. 5
1.5. Thermoelectric material .......................................................................................................................... 6
1.5.1 (Bi, Sb)2Te3 ...................................................................................................................................... 6
1.5.2 Skutterudites ...................................................................................................................................... 6
1.5.3 Semiconductor ................................................................................................................................... 6
1.5.4 SiGe alloys ........................................................................................................................................ 7
Objective of this work ........................................................................................................................................ 8
2. Fabrication and characterization method ........................................................................................................ 9
2.1 Reduced Pressure Chemical Vapor Deposition (RPCVD) ....................................................................... 9
2.1.2 Condensation Technique ................................................................................................................. 10
2.2 Lithography ............................................................................................................................................ 11
2.3 Focus Ion Beam (FIB) ............................................................................................................................ 12
2.4 Sidewall Transfer Lithography (STL) .................................................................................................... 12
3. Experimental ................................................................................................................................................ 13
3.1 Sample preparation ................................................................................................................................. 13
3.2 Fabrication of SiGe NWs ....................................................................................................................... 14
3.3 Electrical measurement set up for SiGe NWs ........................................................................................ 17
3.3.1 Electrical conductivity measurement .............................................................................................. 18
3.3.2 Seebeck measurement ..................................................................................................................... 21
4. Results and discussion .................................................................................................................................. 24
4.1 Electrical conductivity result for FIB ..................................................................................................... 25
4.2 Electrical Conductivity and Seebeck measurement for STL .................................................................. 28
4.2.1 Influence of temperature on conductivity and Seebeck measurement ............................................ 29
Conclusions ...................................................................................................................................................... 31
vii
Future Work ..................................................................................................................................................... 31
References ........................................................................................................................................................ 32
Appendix .......................................................................................................................................................... 36
Scanning Electron Microscopy (SEM) ......................................................................................................... 36
X-Ray Diffraction (XRD) ............................................................................................................................ 37
Probe Resistivity Measurement .................................................................................................................... 38
1
1. Introduction
1.1 Thermoelectric phenomena and applications
From the dawn of modern civilization, the dependency of society’s energy consumption from
natural resources has increased steadily. The rate of energy consumption has especially risen for
many developing countries. This is a dangerous trend that endangers the environment by increasing
the greenhouse gas generation. The increase of greenhouse gas generation results in global warming
with catastrophic consequences [1].
There has been a strong attempt from the scientific community to find alternative solutions to
provide clean energy and reduce the dependency on fusil fuels. Solar energy and thermoelectric
solution are the most popular examples for green energy. Thermoelectric solution functions by
harvesting waste heat energy and it is considered more attractive since the access to sunlight could
be limited in northern Europe and America. The harvesting of waste heat energy requires
development of high efficiency thermoelectric materials (TE) [2, 3]. In principal, this is based on
Seebeck effect and Peltier effect which is the heating or cooling at an electrified junction of two
different conductors.
The heat is applied to specific parts of the TE materials, a temperature gradient is generated which
results in voltage generation and consequently electric current.
Figure 1 shows a TE power generation system and a TE refrigeration system.
Figure 1.TE power generation and TE refrigeration systems [2].
2
1.2 Seebeck and Peltier Effects
Seebeck effect occurs when two dissimilar materials are joined together and junctions are held at
different temperatures; a voltage difference that is proportional to the temperature difference will
develop. The ratio of the formed voltage to temperature difference is called Seebeck coefficient
which is shown in Eq. 1 and it is an intrinsic property of materials [2].
𝛼 =∆𝑉
∆𝑇
In a similar manner, the Peltier effect (or thermopwer) occurs when an electrical current is passed
through the junction of two dissimilar materials; the heat is either absorbed or rejected at the
junction, depending of direction of the current. This effect is related to Seebeck effect. Eq. 2 shows
this relation [2].
𝛱 = 𝛼 . 𝑇
The rejected or liberated Peltier heat (𝑄𝑝) is formulated by Eq. 3:
𝑄𝑝 = 𝛼. 𝐼 𝑇
where "I" stands for the current through the junction and T is the temperature in kelvin [2].
1.3 Figure of merit
The figure of merit which measures how good a material is for thermoelectric application is a
dimensionless term, ZT (Eq. 4). This figure of merit is comprised of the Seebeck coefficient (α),
electrical conductivity (σ), and thermal conductivity (electronic thermal conductivity + lattice
thermal conductivity) (𝑘𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛 + 𝑘𝑝ℎ𝑜𝑛𝑜𝑛), where T is temperature.
𝒁𝑻 = 𝛼2.𝜎.𝑇
𝑘𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛+𝑘𝑝ℎ𝑜𝑛𝑜𝑛
Eq. 1
Eq. 2
Eq. 3
Eq. 4
3
Up until the mid -1990s, the best TE material demonstrated a value of ZT≈1. In recent years, it has
been a challenge in science to increase the ZT value. An ideal thermoelectric material should be
both superlative electrical and thermal insulator [2]. Recent reports demonstrate that reduction of
thermal conductivity with improvements in electrical conductivity is a difficult task. Two different
techniques were developed to solve this issue. One way is to develop new materials and the other is
to reduce sizes to nanostructures to enhance the ZT value for the thermoelectric devices [4].
1.3.1 Monitoring Seebeck coefficient and electron conductivity
When a temperature gradient is applied across a material, electrons move to the colder side. The
accumulation of charged particles on the colder side will create a potential energy and consequently
establishes an electric field. Hence the Seebeck coefficient can also be defined as the ratio of the
generated electric field to the temperature difference across the material. In this case, the Seebeck
coefficient is given in Eq. 5.
α =
∇𝑇
Figure 2 shows that the electric field is in the opposite direction of the temperature gradient [2].
Figure 2. The carrier distribution over the cold side until an electric field (E) i
According to Eq. 4 ZT can be improved when the Seebeck coefficient and electron conductivity are
high. Higher conductivity is associated with larger Carrier concentration. It is also important to
mention here that a single type of carrier is sought for ZT, otherwise mixture of both charge carriers
generate a lower electric field across the material due to canceling effects of generated voltages. A
more detailed expression for Seebeck coefficient can be given by Eq. 6:
𝛼 =8𝜋2𝑘𝐵
2
3𝑒ℎ2𝑚∗𝑇(
𝜋
3𝑛)2 3⁄
E
∇𝑇
Eq. 5
Eq. 6
Figure 2. The carrier distribution over the cold side until an electric field (E) is established [2].
4
where n stands for the carrier concentration and 𝑚∗ is the effective mass of the carrier. Both the
electrical conductivity (σ) and electrical resistivity (ρ), are related to carrier concentration through
the carrier mobility, µ:
1
𝜌 =σ =neµ
The interesting point is that the increase of carrier concentration will result in higher electrical
conductivity and in return, the Seebeck coefficient is decreased at a specified point. Figure 3 shows
the Seebeck coefficient and electrical conductivity and ZT graph for a good thermoelectric material,
and shows that the ZT start falling for carrier concentration between 1019 and 1020 Cm-3
[6].
Figure 3. The derived ZT of a thermoelectric device shows the thermal conductivity, Seebeck coefficient, and electrical conductivity
[6].
Eq. 7
5
1.4 Tailoring thermal conductivity
Reduction of thermal conductivity is the key to increasing ZT. The thermal conductivity is
dependent on lattice and electronic thermal conductivity. In general, the characteristic length
(Wavelength and mean free path) of phonons are larger than the corresponding parameters for
electrons in crystalline solids. This makes the lattice conductivity a more attractive component of
the thermal conductivity to concentrate on. A minimum lattice thermal conductivity could be
obtained when the phonons have a larger mean free path than both grain size and the electron mean
free path [7]. There are several methods to lower the lattice thermal conductivity such as utilization
of alloying materials and the size reduction of materials to nanoscale. However, the nanostructure
materials should be processed to sizes larger than the corresponding carrier wavelength [8]. Figure
4 (a) shows a decrease in thermal conductivity for Si NWs as their width decreases and Figure 4 (b)
shows the ZT value at about 0.6 for Si NW with 37 nm width which is 60 times larger when
compared to that of a ZT value for Si bulk [32].
Figure 4. (a) Decreasing thermal conductivity according decreasing size of NW (b) increasing Zt value for Si NW with 37nm
thickness [32].
6
1.5. Thermoelectric material
In recent decades, a series of new materials and also more advanced characterization techniques for
thermoelectric application have been discovered. The widely used TE materials include (Bi, Sb)-Te
alloys for near room temperature, materials based on group IV telluride’s that used for mid-
temperature (500-900 K), and Skutterudites for thermoelectric generators for temperature > 900K,
which have typically used Si-Ge alloys [6].
1.5.1 (Bi, Sb)2Te3
Bi2Te3 alloys are one of the most commonly known TE materials and have been studied since 1954.
They were one of the first alloys to highlight the carrier concentration in the lattice thermal
conductivity. By using mechanical milling and spark plasma sintering, their bulk structure is
developed to form bulk nanostructure materials. The ZT value has increased from ca. 1.4 to ca.1.56
at 300 K. However, decrease of grain size and micro powder lead to decrease of carrier mobility,
resulting in no more ZT enhancement [4].
1.5.2 Skutterudites
A potential material candidate for the reduction of thermal conductivity must have large void spaces
in its structure; Skutterudites such as CoSb3 and IrSb3 are therefore the best option. The materials in
this group have a cage that can be filled with rattling atoms which causes high electrical
conductivity and low thermal conductivity CoSb3 is a good option for medium–temperature
application, because both n-type and p-type materials can be obtained in CoSb3. However, filling
the cage (located at the center of a unit cell) with a small rattling atom cannot be done easily
because only atoms with electrical negativity higher than 0.8 eV can enter the cage [4].
1.5.3 Semiconductor
In last few decades, semiconductors in nanoscale have been widely investigated because of their
unique quantum confined physical properties and their potential to have main role in electronics.
Their properties have been investigated in thin films and bulk binary-alloy structures which have
7
led to improvements in thermoelectricity. In studies of semiconductors, the control of physical
properties by both doping and chemical alloy composition influences the growth parameters. While
research on other thermoelectric alloys can be expensive and toxic, elements such as Te and Pb, Si
and SiGe are cheap and non-toxic [9].
1.5.4 SiGe alloys
During the last few years, Si-based nanoscale materials have become a key material for
thermoelectric applications. This is due to the reduction of thermal conductivity by scattering
phonons with larger mean free paths than dimensions of nanostructure material and surface
roughness. The improvement of ZT for Si NWs is related to the reduction in its thermal
conductivity. This can also happen if Si is mixed with other elements in group IV such as Ge [19,
30]. Both Si and Ge have similar crystalline structures (Diamond structure). The lattice constant of
Ge is larger than that of Si and has a smaller band gap energy; 0.66 eV in comparison to 1.2 eV
respectively. The lattice mismatch between Ge and Si is about 4% resulting in compressive stress
that causes a decrease in the bandgap. Both Si and Ge bulk structures have indirect band gaps.
Decreasing dimensions of SiGe from bulk to nanowire sizes lead to the quantum confinement effect
which in turn causes the indirect band gap to be transformed into a direct band gap [19]. The band
gap of SiGe decrease with increasing Ge content as shown in Figure 5 [31].
Figure 5. The electronic band gap shift for Si(1-x)Ge(x) NWs vs Ge content from 0 to 1 [31].
8
Objective of this work
The aim of this work is to study thermoelectric properties of SiGe NWs fabricated with two
different methods: FIB and STL. The reduction of electrical conductivity according to the
deposition NW by Ga+ ions is another aim of this work that has been investigated.
9
2. Fabrication and characterization method
SiGe has many attractive characteristics that can be utilized for wavelength sensitive photonic
devices, high mobility complementary metal oxide semiconductor devices (CMOS), transistors,
electronic devices and bio sensing application [11]. Thick SiGe film is required to fabricate SiGe
layers with low stress and fewer defects.
A number of methods to produce SiGe layer on an insulator have been developed, such as
condensation technique and SMARTCUT technique. Hence for microelectronic applications,
processing on insulator has its advantages e.g. better electrical control and prevention of diffusion
of Ge into the Si substrate [12].
SiGe layers in nanoscales size (~ 100nm) have many applications in science and technology.
Methods to fabricate NWs are based on two different approaches, bottom-up and top-down. A
bottom-up method is defined when the NW structures are grown from their seed in core fashion. On
the other hand, a top-down method is defined when the NW structures are processed through
etching to trim them into a designed structure [13].
2.1 Reduced Pressure Chemical Vapor Deposition (RPCVD)
CVD is a technique to deposit materials on a substrate. The growth of mono-crystalline material on
mono-crystalline material is termed epitaxy, and CVD is one of techniques for epitaxial growth of
high quality films. CVD involves a mixture of gases (reactant gas, dilute gas and also carries gas).
The mixed gases are injected into a chamber containing a single crystalline wafer [21]. The wafer is
heated up to a specific temperature to remove the native oxide before being coated (900-1100 °C
for Si wafers). According to the variety of materials and the wide range of applications, there are
many variants of CVD such as:
1) Atmospheric Pressure CVD (APCVD)
2) Low Pressure CVD (LPCVD at ~0.2 to 20 Torr)
3) Reduced pressure CVD (RPCVD at 10-100 Torr)
4) Metall Organic CVD (MOCVD)
5) Plasma Enhance CVD [20]
10
RPCVD is the most commonly used method for industrial semiconductor fabrication since it has a
high growth rate and low maintenance compared to the other techniques.
2.1.2 Condensation Technique
This technique is based on the thermal oxidation process in high temperatures. The condensation
technique is used in the fabrication of SiGe-on-insulator. It needs a silicon-on-insulator (SOI) wafer
and an epitaxial grown SiGe layer on SOI wafer. The technique starts with a dry oxidation at high
temperature. Since Si oxidizes faster than Ge, the Ge expels from the oxide and diffuses into the
underlying SiGe layer, thereby resulting in an increase of Ge content [14].
High-Temperature Oxidation
𝑆𝑖1−𝑥𝐺𝑒𝑥 x<0.1
Si
Oxid
Si substrate
SiO2
Oxid
Si substrate
𝑆𝑖1−𝑦𝐺𝑒𝑦 y>x
Figure 6. Ge condensation at High Temperature Oxidation.
11
2.2 Lithography
Fabrication of nanostructures below 100nm takes several steps and also requires appropriate
equipment. Optical lithography is an inexpensive, fast, well-known and well-developed method for
lithography in the semiconductor industry. The resolution of an optical lithography system is
dependent on the wavelength of the light source; the formula below shows the dependency:
Lithography Resolution = 𝑘 ∗ 𝜆 /NA
The K is a constant (~ 0.6) and NA is called “numerical aperture”. Schematic diagram of an optical
lithography system is shown Figure 7.
Figure 7. Schematic of an optical lithography system.
Due to the limited capability of G-line (435 nm) and I-line (365 nm) photolithography, the FIB
technique should be used for sizes below 100 nm wires [22].
Eq. 8
12
2.3 Focus Ion Beam (FIB)
Focus Ion Beam (FIB) is one of tools that can be used for nanowire size reduction. It is as a
powerful tool for etching as well as deposition. Since the tool is developed in combination with
scanning electron microscope, the etching or deposition can be monitored in situ. The ion sources
used in FIB can be He+, Ga
+ and Xe
+. FIB consists of two separate vertical columns of electron and
ion beams, and to prevent the scattering of ions and electrons, the chamber should be under vacuum
ranging from 10−6 𝑡𝑜 10−9 Torr [15].
The fabrication of NWs by FIB is governed by different parameters which are given by the beam
profile, degree of Ion beam and electron scanning, Ion dose and energy, and also by changes
induced in the structure of the sample by Ion implantation [16].
In this study FIB equipment with Ga source was used to fabricate and dope SiGe NWs with Ga+ to
enhance their conductivity.
2.4 Sidewall Transfer Lithography (STL)
With recent advancements in the field of optical lithography in semiconductor industries, STL can
be used to pattern materials and etch them to sizes below 100 nm to be used as NWs. STL is a
widely used technique that creates NWs [17].
In this process, the designated materials are deposited on SOI, followed by optical lithography
patterning to desired sizes and then etched to form NWs [18]. The parameters involved in
controlling the NWs to correct sizes are pattern integrity, film thickness and uniformity, correct
etching process and control, and of course particulate free films and processes to avoid induced
process defects [17].
13
3. Experimental
3.1 Sample preparation
In both FIB and STL fabrication methods, SIMOX wafers with 340 nm Si and 400 nm buried oxide
layer were used to fabricate the NWs. Initially the top Si layer was thinned down to 50 nm using
dry oxidation at 1250ᵒC. Afterwards the formed oxide layer was removed and the wafers were
cleaned using standard cleaning prior to growth. On these SOI wafers, a 100 nm Si0.74Ge0.26 was
deposited at 550°C using chemical vapor deposition (CVD). The precursor gases were SiH4 and
GeH4 with partial pressures of 100 and 20 mTorr, respectively. At first, the SiGe film was oxidized
at 1150°C for 120 minutes, afterwards it was annealed at 1050°C in Nitrogen for 60 minutes in
order to decrease the defect density of the remained layer.
A schematic of this process is shown in Figure 8.
The Ge content in the as-grown and the formed SiGe-on-insulator (SGOI) layers was determined by
x-ray diffraction (XRD) technique (as shown in figure 2.2) The SGOI had a Ge content of 47% and
the strain relaxation was estimated to be close to ~ 90%.
The SGOI wafers were doped with boron and phosphorus through a diffusion step when B2H6 and
PH3 precursors were blown over the wafers at 650 C for 10 min. Dopant concentration of ~1017
cm-3
was obtained for n- and p-type wafers.
120 min in 1150 °C- O2
60 min in 1050 °C- N2
Si-substrate
200nm SiO2
50nm Si
100nm Si0.74Ge0.26
10nm Si
Si-substrate
200nm SiO2
70nm Si0.53Ge0.47
SiO2
Figure 8. Fabrication of SiGe-On-Insulator (SGOI) by condensation technique.
14
Figure 9. XRD rocking curve of epi-SiGe before and after condensation.
3.2 Fabrication of SiGe NWs
In this part, two methods, I-line lithography combined with FIB and side wall lithography were
used to fabricate NWs. The number of fabricated NWs on each device was 34 and they were
connected to eight contact pads and a heater above to introduce different temperatures as shown in
Figure 10.
Figure 10. SEM image of the fabrication device.
FIB technique was used to thin down the NWs to designated sizes as well as doping with Ga ions.
In this way, their electrical conductivity could be adjusted [23].
15
Figure 11 shows SEM image of NWs before and after cutting. In order to avoid damages from FIB
to the NWs, a low current of Ga beam was used during the thinning. No visible deformation was
observed in these NWs after FIB treatment as shown in Figure 12.
a) b)
Figure 11. (a) Shows initial NWs (b) demonstrates 34 NWs after being cut plus NWs that remained intact.
a) b)
Figure 12: a) Three SiG60nm.
1 µm
60 nm SiGe Layer
c)
60 nm
Figure 12. (a) Three SiGe NWs with thickness 1000nm (b), (c) SEM image of one of the SiGe NW thinned down to 60nm.
16
In general, there are two approaches to manufacture NWs, top-down and bottom-up. From these
two techniques, the bottom-up results in less process induced defects compare to top-down method.
In this study, all NWs fabrications were done by bottom-up process method [24]. By employing
side wall transfer lithography (STL), the NWs ‘sizes were reduced to about 60nm.
Figure 13(a-h) demonstrates the schematic view of STL process. STL technique consists of a
sequential deposition and etching steps to form spacers which can be used as hard mask to fabricate
NWs. STL technique starts by a PECVD deposition of 40 nm SiO2 layer as the first hard mask. This
is followed by deposition of 100 nm Si film as a support layer and 60 nm of Si nitride using
PECVD as a second hard mask. The next step to create the nanowire pattern is to use I-line
lithography (Figure 13 b), and then the Si3N4 nitride layer is etched using CHF3/CF4 followed by a-
Si etching using mixture of Cl2/HBr gas. These steps are followed by deposition of a Si nitride layer
using PECVD and etching back to form side wall spacers (Figure 13 d, e).
The rest of process steps are as follow: The a-Si is wet-etched by tetra-methyl-ammonium-
hydroxide (TMAH) with respect to Si3N4 spacer and SiO2 hard mask (Figure 13 f). Then 60 nm
nitride spacers are used as mask to etch SiO2 hard mask with high selectivity of 6:1 in CHF3/O2
plasma (Figure 13 g). Finally, the SiGe film is etched in RIE chamber (Reactive-ion etching) to
form well defined SiGe NWs with 60 nm widths (Figure 13 h). Afterwards, NWs are fabricated and
metal electrodes of Ti/Pt are evaporated and formed across NWs by lift-off process [33].
a-Si support material SiO2 hard mask SiGe device layer BOX Si Substrate
Si substrate
40 nm
100 nm
60 nm
Si substrate
Si substrate
Si substrate
Si substrate
Si substrate
Si substrate
Si substrate
SiN hard mask
a) b) c) d)
e) f) g) h)
Figure 13. (a-h) Schematic of process steps of NWs using STL method [33].
17
The fabricated STL technique is a good fabrication method for NWs thinner than 100 nm as showed
in SEM micrograph in Figure 14.
Figure 14. SEM image of final NWs with 60 nm width and 22µm length.
3.3 Electrical measurement set up for SiGe NWs
According Eq. 9, in order to measure the ZT value for SiGe NWs, the Seebeck coefficient, electrical
conductivity and thermal conductivities should be known.
ZT = α2.σ.T
k Eq. 9
In this work we measured the Seebeck coefficient and the electrical conductivity of the SiGe NWs
at different temperatures and voltages. To determine the Seebeck coefficient, we introduced
incremental temperature changes along the SiGe NWs and measured the induced electrical voltage
at output pads according to the schematics in Figure 15 described to calculate ∆𝑉
∆𝑇 . The conductivity
of NWs was calculated from resistivity measurements of the nanowire using the formula below:
(𝜎: 𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑣𝑖𝑡𝑦 =1
𝜌 , 𝑤ℎ𝑒𝑟𝑒 𝜌 𝑖𝑠 𝑟𝑒𝑠𝑖𝑠𝑡𝑖𝑣𝑖𝑡𝑦)
Eq. 10
18
The schematic below shows a device that consists of 34 NWs, 8 contacts pads and one heater to
generate heating along the NWs.
A Keithley 4200-SCS Parameter Analyzer was used in connection to a semi-automated probe
station for electrical measurements. To ensure that the pads were connected properly, their
resistivity were measured between pads (4, 6) and (3, 5) or (2, 8) and (1, 7) at room temperature.
Resistance was expected to be in the range of 400 Ω to 800 Ω. For the heater, the resistance
between pads (9, 10) was expected to once again be in the range of 400 Ω to 800 Ω. All tests were
in the reasonable range.
3.3.1 Electrical conductivity measurement
Electrical conductivity measurement consists of contact resistance 𝑅𝐶, electrode resistance 𝑅𝐸 and
the resistance of NWs 𝑅𝑊. Figure 16 shows the schematics for the measurements. Since electrodes
are made of metal, their resistance is much lower than the resistance of the NWs that are
semiconductor materials. To decrease the contact resistance, the contacts between metal and NWs
were made ohmic by annealing the metal. The contact resistance was measured first with a four-
probe and then by a two probe station. Figure 17 shows the result from these two techniques. As it
is evident, there is no significant difference in resistivity values from these two techniques. Either
technique will provide accurate resistivity
9
10
3
5
1
7
2
8
4
6
Figure 15. Structure of device that consists of 8 contact pads, one heater and SiGe NWs that are contacted to the pads.
19
a)
b)
c)
𝐼2
𝑉2
𝑹𝑾 𝐑𝐄
𝑉1
𝐼1
𝑹𝑪 𝑹𝑪
𝐑𝐄
SiGe
NW
𝑹𝒘 𝑹𝑪
𝑹𝑬 𝑹𝑬
𝑹𝑪
Rtotal = RW + 2RE + 2RC
𝑉2, 𝐼2
𝑅𝑊 𝑉1, 𝐼1
Rtotal = Rw+2RE
Figure 16. (a), (b) Show the schematic of resistance measurement using four probe station (c) demonstrates the schematic of the
resistance measurements using two probe station.
20
Figure 17. Resistance measurements by four probe station and two probe station for contact resistance measurement.
To find the total NWs resistance, we assume that NWs are identical. This assumption is valid due to the fact
that they are built through the same process. Slight variation in their dimensions is negligible and can be
ignored. Using parallel resistance equation, the total resistance is calculated from:
Figure 18. Parallel resistance equation for identical NWs.
𝜌 =𝑅𝐴
𝐿 𝜎 =
1
𝜌
𝑅1 = 𝑅2 = 𝑅3 = 𝑅4 = ⋯
1
𝑅 𝑡𝑜𝑡𝑎𝑙=
1
𝑅1+
1
𝑅2+
1
𝑅3+
1
𝑅4+ ⋯ →→→→ 𝑅1 = 34 𝑅 𝑡𝑜𝑡𝑎𝑙
Eq. 11
21
3.3.2 Seebeck measurement
In order to measure the Seebeck coefficient, one needs to measure “ ∆𝑉
∆𝑇” of SiGe NWs. To achieve
this, we introduce a variable power supply to the heater pads and change the power, generating heat
in the heating elements and therefore inducing heat in NWs. We measured the temperature on the
heater side (left side pad (1, 7) of the schematic, Figure 19 below) followed by temperature across
the NWs (right side pad (2, 8) of the schematic). The temperature difference between these two
measurements will be “T”. In parallel to temperature measurements, the “V” is also measured
between Pads 3 and 6.
In this study we applied different current to the heater to find best and highest power that can
influence the NWs. The power is calculated by Eq. 12. Maximum power in the heater was
generated by 0.04 amperes at 50 volts.
𝑃 = 𝐼2. 𝑅 ( 𝑅 = 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑜𝑓 ℎ𝑒𝑎𝑡𝑒𝑟)
T1 T2
4
6
9
10
3
5
7
1
8
2
C1 C2
Eq. 12
Figure 19. Schematic of the power generation with thermal energy in NWs.
22
3.3.2.1 Temperature measurement
Details of Temperature Measurements:
To measure temperature differences, the inner electrodes, designated as T1 and T2, were used.
Measurements were done in two steps, first on the left side of nanowire (heater side) and next on
the right side of nanowire. Also the heating elements resistance was measured before and after
applying power to its contacts. The applied voltage was kept between ± 1V.
On the left side, this was done by setting the probes between contact pads (9 &10) and (1 & 7). For
the right side, contact pads (9 & 10) and (2 & 8) were used.
The probes are made of platinum (Pt). The relation between resistance and different temperature
when heater is on and off is given by Eq.13. Measurement was in two steps, one step for left side of
nanowire (heater side) and another step for right side of nanowire (without heater). Both parts
consisted of measuring the resistance of the electrodes one time before power was applied to heater
and another time after applied power. Figure 20 shows the result of varied resistances of the
electrode when heater is off and on.
To measure the resistance for the heater side, we put needles on pads (9, 10) and (1, 7). For the non-
heater side, we put needles on pads (9, 10) and (2, 8).
Because the electrodes are built from Platinum (Pt) which is a metal that has a direct relationship to
temperature pursuant to Eq.13, measurements of different temperatures for each side of NWs can
easily be accomplished.
𝑅ℎ𝑒𝑎𝑡𝑒𝑟 𝑜𝑛 = 𝑅ℎ𝑒𝑎𝑡𝑒𝑟 𝑜𝑓𝑓(1 + 𝛼. ∆𝑇)
𝜶 = 𝑒𝑥𝑝𝑜𝑠𝑢𝑟𝑒 𝑒𝑓𝑓𝑒𝑐𝑡 𝑜𝑓 𝑃𝑡
After we took resistances (𝑅ℎ𝑒𝑎𝑡𝑒𝑟 𝑜𝑛 ,𝑅ℎ𝑒𝑎𝑡𝑒𝑟 𝑜𝑓𝑓) for heater side and cold side, we calculated the
∆𝑇ℎ𝑒𝑎𝑡𝑒𝑟 𝑠𝑖𝑑𝑒 , ∆𝑇𝑐𝑜𝑙𝑑 𝑠𝑖𝑑𝑒 according to Eq.13. Finally, the total difference in temperature can be
obtained from Eq.14:
∆𝑇 = ∆𝑇ℎ𝑒𝑎𝑡𝑒𝑟 𝑠𝑖𝑑𝑒 − ∆𝑇𝑐𝑜𝑙𝑑 𝑠𝑖𝑑𝑒
Eq. 14
Eq. 13
23
Figure 20. Resistance difference for NW when heater is off and on.
3.3.2.2 Measurement of Thermoelectric voltage
V consists of the measurement of voltage that is created under the inside of the NWs. This is done
in two steps: once when power is applied to the heater and another time when power is not applied
to heater.
Outer electrodes designated C1, C2 were used for this measurement. Needles were applied to pads
(3, 6) or (4, 5) to measure the voltage difference, 𝑉ℎ𝑒𝑎𝑡𝑒𝑟 𝑜𝑓𝑓, and another on pads (3, 6) or (4, 5)
with the heater on, 𝑉ℎ𝑒𝑎𝑡𝑒𝑟 𝑜𝑛. The difference between these two voltages is the total thermoelectric
voltage ∆𝑉 = 𝑉ℎ𝑒𝑎𝑡𝑒𝑟 𝑜𝑛 − 𝑉ℎ𝑒𝑎𝑡𝑒𝑟 𝑜𝑓𝑓. Figure 21 shows the result of different voltages in room
temperature for SiGe nanowire.
0 20 40 60 80 100 120 140
-0,0005
0,0000
0,0005
0,0010
0,0015
0,0020
0,0025
0,0030
Voltage(V
)
Time (s)
Heater off
Heater on
Figure 21. Voltage difference at room Temperature for NW when Heater is off and on.
24
4. Results and discussion
One of the primary interests of semiconductor technology in recent years is to reduce the size of the
electronic devices that have much faster speed as well as larger financial profit margin by
increasing the number of devices on a wafer. This requires sophisticated instruments and techniques
that will enable the researchers to achieve this goal. In that regard, numerous scientific instruments
and techniques have been developed to process and investigate those structures at nanoscales.
Techniques such as “top-down” or “bottom- up” processes have been used to fabricate devices in
nanoscale. The nanoscale materials and devices require metrology equipment that is suitable for this
purpose. NWs are among the most interesting structures to study for their extraordinary transport
properties due to nanoscale dimensions [25, 26].
In this work, we developed measurement techniques to measure thermoelectric properties of NWs.
Using this technique which was based on parameter analyzer Keithley 4200-SCS which was
equipped with temperature controller, we were able to measure the Seebeck coefficient and
electrical conductivity of NWs simultaneously in different temperatures.
The thermoelectric power factor of fabricated NWs using two different techniques, STL and FIB
was measured and compared.
25
4.1 Electrical conductivity result for FIB
For reliable electrical conductivity measurements of NWs, several criteria should be met. One is to
have a very low contact resistance to the NWs to avoid heat generation that can have adverse
impact on the NWs resistance and consequently adverse effect on the electrical conductivity
measurements.
The resistivity measurements were performed through IV measurement technique. Measurements
were carried out several times for various range of applied voltages (-1 to +1 V, -0.5 to +0.5 V and
-0.1 to +0.1 V with increment of 0.001 V for all cases) for each device. Measurements were also
carried out repeatedly for each device to explore the impact of the generated heat and resistivity of
the devices. The result for the impact of the heat generated through devices is shown in Figure 22.
As it is evident, the resistivity increases and is more pronounced when the value of applied voltage
is increased.
0 2 4 6 8 10 12
37,5
38,0
38,5
39,0
39,5
40,0
40,5
41,0
41,5
42,0
42,5
Resis
tance (
)
Number of measurements
Voltage -0,1 to0,1
Voltage -0,5 to0,5
Voltage -1 to1
Figure 22. Cycle resistance measurement of NW in three range voltage (-1, 1), (-0.5, 0.5), (-0.1, 0.1).
26
The scaling down of NWs by Ga beam can dope and cause damage to the NWs and therefore
influence the conductivity of NWs. Deposition of a thin oxide layer on the surface of NWs can
prevent or decrease the damage and doping of the NWs caused by the Ga beam [27]. Atomic layer
deposition (ALD) was used to deposit 20 nm SiO2 on the surface of NWs at 300ᵒC. Figure 23 shows
the resistance of NWs before and after oxide deposition. There are two possible explanations for the
decreasing resistance after SiO2 deposition. First the contact between needles and pads due to oxide
layer was not connected properly. Second since the deposition was done at 300ᵒC, there is a
possibility for diffusion of Ti in contact areas to NWs which can lead to lower resistance.
0 2 4
15
20
25
30
35
40
45
Re
sis
tan
ce
(M
)
Device number
resistance without oxide layer
resistance with oxide layer
Figure 23. Decreasing resistance of SiGe NW after deposit a 20nm oxide layer.
The NWs were scaled down using FIB with Ga beam voltage and a current of 30 kV and 3 nA
respectively. Figure 24 shows the exposing time and Ga beam current which was used to thin down
the NWs from 1000 nm to 100 nm. We expected that the NWs resistance according to:
R2
R1=
ρL
t.w2
ρL
t.w1
=w1
w2 =10
(R1 and R2 are respectively NWs resistance before and after thinning down)
Should have increased at least 10 times. The measured values of resistance of NWs show much
lower resistance even in comparison to initial values before cutting. The reason of such behavior is
doping of NWs with Ga atoms. The values for resistances of NWs in Figure 24 depicts that lower
current for a longer period of time can dope NWs more in comparison to higher currents and shorter
Eq. 15
27
time. In order to have a balance between time and minimization of damage due to Ga, a current of 3
nA for Ga+ ions was chosen to cut the NWs.
-10 0 10 20 30 40 50 60 70 80 90 100 110
0
4
8
12
16
20
24
28
Resis
tance(M
)
Time(1/min)
30 nA
15 nA
7 nA
3 nA
1 nA
0.5 nA0.1 nA
1.5 pA
30 pA
Figure 24. Resistance measurement of SiGe NW after thinned down with different current Ga beam vs time.
Generally according to resistance formula R= 𝜌(𝐿
𝐴) (where ρ is material resistivity, L is the length
of NW and A is cross-sectional area of NWs), resistance of NWs should increase with decreasing
width of NWS, thus conductivity should decrease. But results of resistance measurements for NWs
with different thickness (1000 nm, 100 nm, 60 nm) that were scaled down with FIB in Figure 25
shows the opposite result. Decreasing size of NW causes a decrease in resistance which in turn
increases the conductivity of NWs. Comparison of this result with another result of resistance
measurement from other works showed that resistances of NWs increase when the size of NWs
decrease [15], therefore the results show that NWs thinned down with FIB are doped with Ga+
which causes a decrease in the resistance of NWS.
0,000 0,002 0,004 0,006 0,008 0,010 0,012
5
10
15
20
25
30
35
40
45
Re
sis
tan
ce
(M
)
1/W(nm-1)
60nm
100nm
1000nm
Figure 25. Resistance values verses 1/width of the SiGe NWs downscaled by FIB.
28
4.2 Electrical Conductivity and Seebeck measurement for STL
As it was expressed in ZT equation, ZT is directly proportional to Seebeck and conductivity
coefficients. By scaling down the sizes of NWs, one can influence the NWs’ conductivity [28].
Also Seebeck coefficient can be affected by a variety of parameters, including the mobility of the
charge carriers. For SiGe materials, carrier mobility can be improved through either conductivity
improvement by doping the materials or increase in the Ge concentration [29]. In the case of SiGe
NWs process by STL method, since the resistance of NWs increases with reduction of NWs
diameters, the role of Seebeck coefficient will become more pronounced for power factor [15].
This study has shown the interesting electrical features of Si0.53Ge0.47 NWs doped with B and P.
These NWs have been studied in different conditions e.g. various temperature and doping
concentrations.
29
4.2.1 Influence of temperature on conductivity and Seebeck measurement
In order to demonstrate the impact of temperature on the Seebeck coefficient, we have measured the
resistance of the SiGe NWs at various temperatures as shown in table below and also Figure 26.
As it is expected, the resistance decreases by increasing the temperature. At the lowest temperature
of 248 K, the NW’s have the highest resistance of 37400 (MΩ) and at the highest applied
temperature of 473 K, the resistance is at its lowest value of 24 (MΩ).
Table 1. Value of NWs resistance at different temperature.
-1,5 -1,0 -0,5 0,0 0,5 1,0 1,5
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
Re
sis
tan
ce
( G
)
voltage (V)
473 K
453 K
313 K
303 K
273 K
2438 K
Figure 26. Resistance measurements of SiGe NWs by changing of temperature.
Different generated voltages of NWs in different temperatures have been measured. It demonstrates
the impact of temperature on generated potential difference generated through the SiGe NWs. As it
is evident from results, the induced voltage at 473 K has the average value of ~13-14 mV. On the
other hand, the induced voltage at 248 K is almost zero.
Temperature
(K)
248
273
303
313
453
473
Resistance
(MΩ)
SiGe NW
thickness 60nm
37400
3475
781
668
33
24
30
With help of the results from these measurements, it is possible to calculate the electrical
conductivity, Seebeck coefficient, and power factor for p-type and N-type SiGe NWs.
Figures 27a, 27b, 27c and 27d show the Seebeck and electrical conductivity of n-type and p-type
SiGe NWs as a function of temperature. The Seebeck coefficient for n-type SiGe has a maximum
value of 1.8 mV/K at 315 K. At this value, the device can generate 1000 µW/mK2 at low electrical
conductivity at 315 K. Similar behaviors for Seebeck and conductivity of p-type SiGe is observed
as demonstrated in Figure 27a and 27c. However, the power factor for p-type Si0.53Ge0.47 NWs is
almost 50% lower than the power factor for n-type Si0.53Ge0.47 (Figures 27e and 27f). The resistivity
data shows that the dopant level of boron for p-doped SiGe layer is slightly higher than the
resistivity for n-type SiGe layer (although the same diffusion process has been applied). We
conclude that the carrier mobility for p-type SiGe NWs is lower than carrier mobility for n-type
samples resulting in lower power generation for p-type SiGe NWs.
Figure 27. Conductivity for (a) P-type; (b) N-type, Seebeck for (c) P-type; (d) N-type, Power factor for (e) P-type; (f) N-type.
250 300 350 400
0,00
0,44
0,88
1,32
250 300 350 400
0,0
1,5
3,0
4,5
Conductivity (
S/c
m)
Temperature (K)
N-type
b)
Conductivity (
S/c
m)
P-type
a)
250 300 350 400
-6,9
-4,6
-2,3
0,0
250 300 350 400
0,72
1,08
1,44
1,80
Seebeck c
offis
ient (m
V/K
)
Temperture (K)
N-type
d)
Seebeck c
offis
ient (m
V/K
) P-type
c)
250 300 350 400
0
320
640
960
250 300 350 400
0
210
420
630
Pow
er
facto
r (
W/m
.K2)
Temperature (K)
N-type
f)
Pow
er
facto
r (
W/m
.K2)
P-type
e)
31
Conclusions
Si0.53Ge0.47 NWs with final dimension of 60 nm were manufactured on SGOI wafers by using either
sidewall transfer lithography or I-line lithography combined by FIB technique.
Thermal and electrical properties of SiGe NWs have been successfully measured and compared.
SiGe NW grown by FIB method have lower electrical resistance (0.4 MΩ) compare with SiGe NW
grown by STL method (4.2 MΩ). In general, the resistance of NWs should increase when they are
thinned down to 60 nm but we see lower resistance by FIB method compare with STL due to Ga
implantation. This method allows Ga implantation from the sides into the SiGe NWs.
The STL method is a Si compatible process which uses one step lithography and only by using
sequence of deposition and dry etching can provide high dense uniform NWs on wafer scale
production. The measured power factor of n-type SiGe NWs is two times higher than similar
measured p-type SiGe NWs.
Future Work
Growing SiGeSn alloy NWs and reducing the size of NWs from 60 nm to 30 nm to improve the
thermoelectric properties and take higher ZT value.
32
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35
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36
Appendix
Scanning Electron Microscopy (SEM)
SEM is used to scan and characterize the SiGe NWs and to thin down SiGe NWs in FIB method on
SOI wafer. This microscopies work is based on electrons beam that be generate at the top of
microscopy by an electron gun. The electron beam accelerates and travels between magnetics lenses
which are in vacuum, focusing beam on the sample. After beam hits to sample, two kinds of
electrons are created as backscatter electron and secondary electrons. Detectors take these electrons
and make the image of NWs [33]. (see Figure 28)
Figure 28. Schematic of a Scanning Electron Microscopy(SEM) [33].
37
X-Ray Diffraction (XRD)
X-ray diffraction technique is a well-known method to determine the structure of a crystal. A brief
description of this technique is given below.
X-rays are electromagnetic radiation with wavelengths in the range of 0.02 Å to 100 Å [27],
because X-rays have wavelengths similar to the size of atoms, they are useful to explore within
crystals.
X-rays are produced in a device called an X-ray tube. It consists of chamber under high vacuum
with a tungsten filament at one end, called the cathode, and a metal target at the other end, called an
anode. When an electrical current is run through the tungsten filament, it causes the filament it to
glow and emit electrons. Then a large voltage difference (usually in kilovolts) is placed between
the cathode and the anode, resulting in acceleration of the electrons to move at high velocity from
the filament to the anode target. Upon impinging the atoms on the target, the electrons eject the
inner shell electrons resulting in outer shell electrons to transition to a lower energy shell to replace
the ejected electrons and releasing their extra energy in form of X-ray radiation [34]. The X-rays
then move through a window in the X-ray tube and then can be used for crystallography and
providing crystal structures, using Bragg’s law (nλ=2dsinθ) [34]. In this study, X-ray technique is
used to determine SiGe NWs structure. Figure 29 shows a simple schematic diagram of X-ray
system.
Figure 29. Schematic of X-ray system [34].
38
Probe Resistivity Measurement
Electrical measurements of SiGe NWs basically measure the resistivity of NWs according of active
doping concentration. The resistivity is a measure of majority carrier concentration of the product.
There are several methods that are widely used in semiconductor industry, which the most general
method of measuring the semiconductor resistivity is with the four –point probe. In this technique,
four probes are in contact with electrodes that two probes are contacted with inner electrodes that
are used for following current and two another probes are contacted with outer electrodes that are
used for measuring difference voltage. In this study, mainly focuses was on electrical measurement
of SiGe NWs that fabricated by STL and FIB methods. The complete explanation for measurement
is presented in chapter three.
The probe station is used for this study is a Keithley 4200-SCS Parameter Analyzer (Figure 30).
The 4200-SCS is a modular that performs electrical characterization of materials, semiconductor
devices and processes. The 4200-SCS are supplied with semi-automated probe stations, temperature
controllers [35].
Figure 30. Keithley 4200-SCS Parameter Analyzer [35].
