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AbstractIn recent years, there has been concerns about the
scalability of planar CMOS technology. Various non planar
devices have been extensively explored to develop device with
better performance. GAA NWFET and GAA CNT-FET are
considered to be the most promising devices which are likely to
replace planar MOSFET. The merits and technology hurdles for
these devices are presented in this paper.
Index TermsCMOS scalability, CNT FET, GAA, NW-FET.
I. INTRODUCTIONMOShas become an important component in our human
society. It has become an important driving force in the
world economy. As a reason, a continuous progress of CMOS
technology with high performance and low power
consumption is very important. Scaling of MOSFET has
always been the driving force behind the progress of CMOS
technology. In the recent year, there has been concern over the
scalibility of CMOS. As a reason, various non-planar devices
has been extensively explored in order to achieve better
performance and replace planar MOSFET. Some of these
innovative approaches are double gated FINFET[1, 2], tri-
gated [3], -gated[4], -gated[5], nanowire FET [6-10], Gateall around (GAA)[11-13] and CNT FET [14-22]. The GAA
approach gives the best possible electrostatic gate control [10-
13, 23, 24]. The nanowire and carbon nanotube combined with
GAA structure is likely to replace the planar CMOS
technology provided the technical issue associatedwith the
device such as fabricationand contact resistivity are solved.
In this paper, the scaling limiting factor of planar CMOS
technology is described. The properties of nanowire and CNTwhich makes them the better choice are also discussed. The
merits and demerits of gate all around (GAA) nanowire (NW)
field effect transistor (FET) and carbon nanotube (CNT) FET
are also discussed.
II. SCALING OF PLANAR MOSFETThe progress in CMOS technology since the early 1970 has
been achieved by down scaling of MOSFET devices. The
scaling has been the efficient way to achieve higher
performance and lower power consumption. The scaling has
followed the Moors law aggressively. Dennard proposed theideal scaling method [25] as listed in table 1[26]. However,
the actual scaling for past 30 years from1970 to 2000 washigher than the ideal scaling as shown in figure1 [26].
Table 1 IDEAL DOWN-SCALING SCHEME.Geometry
and supply
voltage
Lg, Wg,
Tox, Vdd
Scaling
factor
K
Scaling K: K = 0.7 for
example
Drive
current in
saturation
Id K
Id = VsatWgCo(Vg _ Vth)
Co: gate C per unit area
Wg(tox-1
)(VgVth)=Wgtox
-1(Vg - Vth)
= KK-1
K= K
Id per unit
Wg Id /m 1
Id per unit Wg = Id/Wg = 1
Gate
capacitanceCg K
Cg = ooxLgWg/tox KK/K = K
Switching
speed K
= CgVdd/IdKK/K = K
Clock
frequencyf 1/K
f= 1/ = 1/K
Chip area Achip : Scaling factorIn thepast, > 1 for most cases
Integration
(# of Tr)N /K2
N/K2 = 1/K2,when = 1
Power per
chip
P fNCV
2/2K
-1(K-2)
K(K1)
2= = 1,
when = 1
It can be observed from figure 1 that scaling of the device
results in increase in power consumption. As a reason,
increasing power consumption has become one of the
important limiting factors of CMOS scaling. The most
effective way to reduce power consumption is by reducing the
supply voltage (Vdd). This requires reduction of threshold
voltage (Vth) to get a high On current. However, reduction of
Vth increases off leakage current as sub-threshold leakage
current increases with decrease in Vth. Hence, Vdd voltage
From MOSFET to GAA Nanowire and
Carbon Nanotube FET : Their Merits and
Technological Barriers.
Bishwojit Konsam,[email protected],MSc Nanaelectronics and Nanotechnology
C
mailto:[email protected]:[email protected]:[email protected]:[email protected]8/3/2019 Nanowire Logic
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and Vth cannot be reduced easily. Vdd and Vth scaling trends
is shown in figure 2 and 3and the limiting value of Vdd and
Vth are 0.9 and 0.1 V [26].
Figure 1: Actual scaling in past 30 yrs from 1970 to 2000 [26].
Figure 2: Supply Voltage scaling trends [26]
Figure 3: Threshold Voltage scaling trends [26]
Other limiting factor of CMOS scaling are channel length and
gate oxide thickness. The ITRS 2009 prediction for channel
length has been presented in figure 4 [27]. Some of the
emerging device which has the potential to replace CMOS
technology are shown in figure 5[26]. A plot of ON current
and OFF current for various device technologies is shown infigure 6 [28].
Figure 4: Channel length scaling trends (ITRS 2009) [27]
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Figure 5: Roadmap of emerging technologies [26]
Figure 6: ON and OFF currents for various technology devices [28]
III. NANOWIREFETA. Nanowire Properties
A 1.54 nm square Si nanowire passivated with H is shown in
figure 7 [29]. The performance of NWFET depends on the
band gap, valley splitting and effective masses of electron and
holes. The band structure of the 1.54 nm square Si nanometer
is shown in figure 8 [29]. The various parameters dependent
on the thickness of Si nanowire are shown in figures (9-12)
[29]. The transmission versus energy for the nanowireconduction band in full band and single band calculation is
shown in figure 13[n1]. The comparison transmission through
an ideal nanowire and nanowire on substrate is shown in
figure 14[29].
Figure 7: 1.54 x 1.54 nm Si nano unit cell (left) and octogonal
nanowire on substrate passivated with H (right).
Figure 8: Band structure of 1.54 x 1.54 nm Si NW calculated from
empirical tight binding sp3d
5s model. (a) Conduction band and (b)
Valence band (lattice constant of Si, a =5.4 A)
Figure 9: Si NW band gap verses Si wire thickness
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Figure 10: Effect of wire thickness on the (a) 2 and 4 conduction
band (b) 2 - 4 splitting (c) splitting at minimum labelled 4
conduction band in figure 9
Figure 11: Effect of Si thickness on (a) the maximum energy of the
three highest valence bands and (b) their energy splitting (labelled
from high to low, Ev1, Ev2 and Ev3)
Figure 12: Effect of NW thickness on the highest valence bands
(labelled from high to low, valence 1, valence 2 and valence 3)
Figure 13: Transmission versus energy for 1.54 nm thick wire (a)
conduction band in both full band and single band model (b) full
band calculation of the valence band transmission and (c) single-
band calculation of valence band.
Figure 14: Comparison of transmission through an ideal wire and
wire on a substrate calculated in sp3d
5s
*model for 1.15 nm
octagonal model
The average mass along the wire is reduced in conductionband due to valley splitting but quantum confinement
increases the transverse mass. This results in heavier
transverse mass in nanowire than that of the bulk. In the
valence band effective mass is 6 times heavier than that of the
bulk Si.
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B. Gate-all-around device (GAA)In the recent years, there have been many innovative non
planar device structures in order to have a better electrostatic
control of the channel potential [30, 31]. Some of the gate
structures are shown in figure 15[32]. It has already been
shown in [11-13, 23, 24] that the GAA device structure has the
best possible electrostatic control. The most common GAA
device structure is either cylindrical or quadruple gate
structure as in figure 15.
Figure 15: Some of the type of device gate structures [n4]
The DIBL effect and threshold voltage roll off for different
gate structured and different gate length SOI MOSFET is
shown in figure 16 [33]. The effect of gate length, doping
concentration of substrate, channel width and the silicon film
thickness on the short channel effects like DIBL, threshold
voltage roll up and sub-threshold slope of different gatestructured devices are shown in figures (17-27) [33].
Figure 16: Potential lines (a) tri-gate device, (b) quadruple-gate
device and (c) -gate device
Figure 17: Effect of channel length on DIBL and threshold voltage
roll-off in different gate structured devices.
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Figure 18: Effect of gate length on Sub-threshold slope in different
gate structured devices
Figure 19: Effect of doping concentration and gate length on
threshold roll-off in different gate structured devices
Figure 20: Effect of doping concentration on DIBL in different gate
structured devices
Figure 21: Effect of doping concentration on Sub-threshold slope in
different gate structured devices
Figure 22: Effect of channel width on threshold voltage in different
gate structured devices
Figure 23: Effect of channel width on DIBL in different gate
structured devices
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Figure 24: Effect of channel width on Sub-threshold slope in
different gate structured devices
Figure 25: Effect of Si film thickness on threshold voltage in
different gate structured devices
Figure 26: Effect of Si film thickness on DIBL and threshold voltage
roll up in different gate structured devices
Figure 27: Effect of Si film thickness on Sub-threshold slope in
different gate structured devices
TABLE 2: EFFECTS OF VARIATION OF GATE LENGTH, WIDTH,
THICKNESS AND DOPING CONCENTRATION ON DIBL, THRESHOLD
VOLTAGE AND SUB-THRESHOLD SLOPE
Parameter
Effect on
DIBLThreshold
voltageroll-off
Thresholdvoltage
Subthreshold
slope
Gate lengthDecreaseswith length
Decreaseswith
length
Decreaseswith length
Dopingconcentration
of the
substrate
Decreaseswith
concentration
No effect constantDecreases
with
concentration
Channelwidth
Increaseswith width
constantIncreases
with width
Si filmthickness
Increaseswith
thickness
Increaseswith
thickness
Almostconstant
Increaseswith
thickness
The advantages of GAA structure over other gate structures
are
i. Suppressed DIBL.The potential lines originating from the source and the drain as
shown in figure 16, controls the vertical potential profile
underneath the channel of the device. This potential increases
linearly with drain bias and causes back-channel conduction
and DIBL. In GAA device, the potential lines are mostly
suppressed and as a reason, the DIBL is also most effectively
suppressed as evident from figure 17,20,23 and 26
ii. Minimum threshold voltage roll-off variation.The threshold voltage and its roll-off is minimum in GAA
device as observed in figure 17, 19, 22, 25 and 26. The
threshold voltage is inversely proportional to the gate oxide
capacitance which is directly proportional to the area of the
gate. The effective area of the gate in GAA device is more
than any other multi gate device and so has the minimum
threshold voltage.
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iii. Minimum sub threshold swing/ slope.The sub threshold slope dependent on the ratio of depletion
capacitance and gate capacitance. The gate capacitance is
maximum in GAA device and so the ratio becomes the least.
This makes the sub threshold slope minimum in GAA device
(figure18, 21, 24 and 27).
iv. High transconductance
Figure 28: Transconductance of GAA device
The GAA device shows high transconductance as shown in
figure 28 [11]. The increase in the effective area of the gate is
one of the reasons for high current drive in GAA devices.
Another factor that contributes to high current drive is the
phenomenon of volume inversion [11].
C. Nanowire FETThe structure of a nanowire FET is shown in figure 29[10] and
30.The GAA NWFET excluding the common advantages of
GAA structure are:
i. 3D scalabilityThe NWFET is a non planar device and so it can be scaled in
3-D which means it will have higher density than the planar
MOSFET for the same chip area. Vertical GAA NWFET is a
good example which has 3D scalibility [34].
ii. Growth independent of lithography resolutionlimit
The nanowire can be grown chemically (bottom up approach).
This makes it possible to fabricate nanowire below the
resolution limit of the lithography process.
iii. Ballistic transportWhen the channel length of the device is scaled less than that
of free mean path of electron, the transport of the electron in
the channel will be ballistic which means the drain current will
be higher[35].
iv. High surface to volume ratioSiNW has high surface to volume ratio. This ensures easy
control of mass carriers by a weak electric field applied on the
gate[36].
Figure 29: (a) Layout of a typical nanowire, (b) SEM image
nanowire fin, (c) SiNW with 9nm oxide (d) SiNW with after gate
deposion (e) TEM image of SiNW
Figure 30: GAA Nanowire FET
D. Fabrication of NW FETThere are many techniques to synthesis nanowire and many
fabrication methods for NWFET. These methods can be
broadly divided into bottom- up, top- down and hybrid
method.
i. Top down techniqueTop down technique is based on conventional MOSFET
technique which depends on the lithography performance. The
top down technique has a very good control over the location
and morphology of the NWFET[37, 38].
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ii. Bottom up techniqueBottom up technique [39, 40, 41] is free to choose different
materials and so is considered a very promising technique for
the next generation devices. However, it has the drawback of
difficulty in accurately controlling the location of NWFET
and has a very low yield. In bottom up technique, the
nanowire are synthesise by CVD method and then transferred
randomly to the target substrate with solution dispersing
method. Then, lithography techniques are used to metal bondon the nanowire to form electrodes. Finally, it is annealed for
bonding and is passivated to get higher mobility.
iii. Hybrid techniqueHybrid technique [42-44] utilises both top down and bottom
up techniques. Lithography method is used to pattern catalyst
on the substrate on which nanowires are grown by VLS
growth. This metyhod gives a controlled size, shape and
position of NW. this has become a major technique to
fabricate NWFET.
E. Technical limitations of NWFETi. Control of surface wire properties
The nanowire surface has unbounded atoms and the control ofthe surface atom become important when the diameter of the
wire become very small. At small diameter, the number of
atoms on the surface becomes more than that of the underlying
atoms. As a result, the properties of the nanowire are mostly
dependent on the surface atom.
ii. Source drain contactThe nanowire- metal contact is usually difficult to get ohmic
contact. This will reduce the performance of the NWFET [36].
iii. Assembly and fabrication issueNWFET fabrication techniques available at the moment are
not good enough to produce reliable device and do not have a
good yield. Top down techniques has the lithographylimitation to fabricate small nanowire. While bottom up [39,
40, 41] technique is a good approach, however, it lacks the
controllability of the location of the NWFET and has very low
yield. The hybrid technique [42-44] is probably the most
promising technique in the near future but it has not matured
enough to go for a mass production.
iv. Twin boundary and defects in thicker SiNWTwin defects are formed on the nanowire larger than 16 nm
diameter. These desired are undesired and as it determine the
performance of the SiNW based devices[45].
III. CARBONNANOTUBEFETA. CNT Properties
The electronic structure of single walled CNT resembles a
strip of a graphene sheet and rolled up to a form a seamless
hollow cylinder [46-48]. The C atoms in CNT form a
hexagonal pattern as in figure. It can be single walled or
multiwalled. Its end can be capped or open and its length can
extend upto tens of micometer. The structure of the CNT is
defined by its circumference or the chirality vector, C and is
given by
where a1 and a2 are unit vectors of the hexagonal lattice as
shown in figure[49].
Figure 31: Graphene sheet and CNT parameters []
A CNT is describe by a pair of integers (n, m) defined in the
chiral vector. A unit cell of CNT is defined by Ch and the 1-D
transitional vector Ph as shown in figure. The electrical
property of a CNT depends on the chirality vector Ch or the (n,
m) pair. The CNT is metallic when n = m (arm chair) and
when n-m (zig-zag) is a multiple of 3 and the rest (chiral) are
semiconductor as shown in figure[49].
Figure 32: Armchair, zig-zag and chiral CNT
The dispersion relation of (3, 3)and (4,2) CNT is shown in
figure which shows the Fermi level [49].
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Figure 33: The dispersion relation of (3, 3)and (4,2) CNT []
The density of states (DOS) of (10, 0) and (9,0) CNT is shown
in the figure[50]. It can be observed from the figure that (10,
0) CNT shows a bandgap and (9,0) CNT shows no band gap
and hence (10, 0) CNT is semiconductor while (9,0) CNT is
metallic in nature.
Figure 34: The density of states (DOS) of (10, 0) and (9, 0) CNT
The bandgap of the semiconducting CNT is dependent on the
diameter and is given by
where Eg is the bandgap energy, is the hooping matrixelement, a = 3 dC-C (dC-C is C-C bond distance), and dCNT isthe diameter of the CNT [51]. The metallic single walled CNT
is 1D quantum conductors and its conductance is given by the
Landauer equation [52, 53]
where h is the Planks constant, 2ee /h is the quantum
conductance and Ti is the transmission of a contributing
channel. The scattering within the CNT can be described by
effective scattering length:
where el is the mean free path of the elastic scattering ac andop are mean free path for inelastic acoustic and opticalphonon scattering. The elastic and inelastic scattering in a
metallic CNT are weak which results in ballistic transport at
low field. However, at high field the inelastic scattering can be
efficient and it leads to current saturation[54]. Along with
Landauer resistance there are other source of resistance such
as electron-electron resistance [55] and contact resistance like
Schottky barrier in semiconductor CNT/ metal contact and
parasitic contact resistance [49].
B. CNT FETCarbon nanotube has been extensively explored since the first
CNT-FET was fabricated and demonstrated in 1998 [56, 57].
The merits of CNT FET arise from its structure and properties.A CNT FET is shown in figure 35[58] and 36. The band
diagram for ON and OFF state of GAA CNT FET is also
shown in figure 35. The subthreshold and output
characteristic of the CNFET in figure 35 is shown in figure 37.
Figure 35: (a) A schemetic diagram of GAA CNT FET, (b) Band
diagram in OFF state and (c ) Band diagram in ON state.
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Figure 36: A GAA CNT FET
Figure 37: Sub threshold and output characteristic of GAA CNFET
Some of the merits of GAA CNT FET in addition to the merits
of GAA device are listed below
i. Large ON currentAs discussed earlier, the 1 D quantum of conduction and low
scattering nature, CNT-FET has large ON current. The
metallic CNT can withstand very high current density due to
its strong bonding and high heat conductivity.
ii. Improved gate controlIn CNT, all the bonds are satisfied without roughness
scattering even at high gate fields which is absent in
conventional semiconductor channels. As a reson, a wide
range of gate insulator/ dielectric can be used with CNT for
improved gate control.
iii. Suppression of short channel effectsThe short channel effects are suppressed in a CNT FET
because of its small diameter. The small diameter results in
high electron confinement which ultimately suppressed the
short channel effect. This makes CNT FET an ideal device for
ultra short device.
iv. Similar effective mass of electron and holesThe effective mass of electron and holes in CNT is similar
because of its band structure. This enables CNT to for n-type
and p-type devices and ultimately CMOS type
device/technology.
v. Possible optoelectronic applicationThe semiconductor CNT is a direct gap material. This makes
CNT applicable in optoelectronic applications.
vi. Possibility of all nanotube deviceThe existence of metallic as well as semiconductor CNT
makes it a possibility to fabricate all CNT device where the
metallic acts as interconnects and semiconductor as active
devices.
vii. 3-D scalibilityThe CNT FET is a non planer devices. So it can be scaled in 3
D. A vertical GAA CnT FET is shown in figure 38[59].
Figure 38: Vertical GAA CNT FET
C. Fabrication of NW FETThe synthesis of CNT is bottom-up technology. Some of the
synthesis techniques area. Electric arc discharge[60]
This is used to synthesise ropes of SW CNT.
b. Laser vaporization[61]This is used to synthesise ropes of SW CNT.
c. Chemical vapor deposition[62]This technique is used to synthesise individual SW CNT.
d. Root-growth mechanism:This is a combnation of catalytic and VLS technique.
Fabrication of CNT FET itself is one of the biggest issue of
CNT FET. There are many techniques to assemble CNT and
integrated it to a substrate toform FET. Some of these
techniques are:a. Controlled deposition from solution.[63]b. Controlled growth of suspended network [64]c. Lattice directed growth [65]d. Vectorial growth. [66]
The buttom-up and hybrid fabrication technique describe for
NWFET fabrication can be used for CNT FET.
D. Technical limitations of NWFETi. Fabrication of CNT
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There is no standard method for fabrication of CNTFET. The
current fabrication process is very slow and lacks maturity.
ii. Growth of integration of CNTThe CNT can be synthesise by various technique. However, it
has not been possible to grow a CNT with controlled width
and chirality. Presence of one metallic CNT in a rope can
destroy the whole device.
iii. Large contact resistanceThe metal CNT contact exibit large contact resistance. This isa big problem as it affects the device performance.
iv. Seperation of individual CNT from a ropeThe seperation of individual CNT from a rope has been
difficult as they stick to one another.
IV. CONCLUSIONA collective comparison of a planar MOSFET, a bottom gate
NWFET, a GAA NWFET and top gate CNTFET is shown in
table3.
TABLE 3: COMPARISON OF A PLANAR MOSFET, NWFET, GAA
NWFET AND CNT FET
ParameterNWFET
[67]
NWFETconvert
ed data[67]
Depleted
MOSFET [68]
p-typeCNT
FET[69]
GAANWFE
T10
Gate
Length (nm
800-
200050 50 260
140-
1000
Gate OxideThickness
(nm
600 1.5 1.5 15 9
Mobility(cm2/V s
230-1350
230-1350
- -325-750
Ion (A/m 50-2002000-
5600650 2100
1000-
1500
Ioff (nA/m 2-50 4-45 9 150 1-1.5
Subthreshold Slope(mV/decade
174-609 60 70 130 63
Transcondu
ctance
(S/m
17-1002700-
7500650 2321
DIBL
mV/V50 10
The ON-OFF current ratio is maximum in the case of GAA
NWFET. The sub-threshold slope is also very low in GAA
NWFET which shows its potential towards better device
performance.
In this paper, we have discussed about the factors limiting the
scalability of CMOS technology. The emerging potential
devices are also discussed. The properties, merits and
technology limitations of GAA NWFET and GAA CNTFET
are also discussed. The fabrication limitation is one of the
major technical difficulties in both the devices. In order to
consider the use of either of these devices the technical issues
concerned need to be resolved first. GAA NWFET is the most
promising technology in the near future as most of its
properties, fabrication and technologies are similar with the
CMOS technology. The CNT FET has potential to give higher
performance device however, the assembly, characterisation,
chirality control and fabrication limitation facing at the
moment has to be resolved first. In addition, the processing
technologies of CNT is different from that of CMOStechnology which make it even more unlikely to replace
CMOS technology in the near future.
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