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Churning the Most Out of IP-XACT for Superior Design Quality
Ayon Dey
Lead Engineer, TI
Anshuman Nayak
Senior Product Director, Atrenta
Samantak Chakrabarti
Senior Manager, Atrenta
Samiullah Shaik
Applications Engineer, Atrenta
2
Introduction/Agenda
• Power/voltage domain, clock, resets, default values, port types-dft/interrupts/dma etc
What IP Metadata is useful
How can this Metadata be extracted
• Directly from IP RTL• While doing IP packaging by the module designer
How is this metadata used
• SoC Integration: Intelligent Integration • Integration quality checkers• Generators (eg CPF from IPXACT)
3
SoC Integration Challenges
Complexity
Gordon Moore
Time to Market
SoC Integration
Productivity Challenge
• Higher integration
• Power management
• Numerous clock domains
• Accelerate SoC development cycle
• Quick Spins
• Integrate SoC (IP>100) with minimum design resources
• Reduce number of IP bugs, verification cycles
• Need to do it: Correct by construction
• Need to increase: Reuse
• Do it Quickly
• Increase efficiency by Enabling Downstream flows
SoC integration is not limited to just connecting IPs
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Common Uses of IPXACT
Verification• Generate C tests• Software header files
IPXACT
Design/Integration Metadata• Component/Component Instances• Bus Interfaces/Interface connections• Ports/AdHoc connections• Design Configurations• Filesets• Registers
Documentation• Implementation Specifications• Generation of System memory map
Software• Header files
SoC Integration• Generation of RTL netlists
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What IP Metadata is Useful• A few examples of what can be added as metadata in IPXACT are below
• Supported by IPXACT 1685– Clock attribute (Mention the
port as clock and if it’s a clock the frequency/pulse width value)
– Default value– Clock driver/signal
characteristics (related clock pin for that port)
– Load/drive cell strength specification
– Constraints attribute which includes
• Timing constraints• Drive constraints• Load constraints
• Not supported in standard IPXACT– Power domain attribute– Voltage domain attribute– Reset attribute– DFT information– Interrupts– DMA
• Can be saved as IPXACT vendor extensions
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How Do I extract Metadata into IP-XACT?How do I use it?
CheckersCheckers
Error: Clock pin connected to non-clock pin!
Error: Reset pin connected to non-reset pin!
GeneratorsGenerators
Module IP1 Pin “clk” connected to Module CLK_IP Pin “clk_25_mhz”. Connection done by matching frequency
Rich IP-XACT storing packaged RTL and other design property
Rich IP-XACT storing packaged RTL and other design property
RTLRTL
Clock constraints (optional)
SpyGlass® DataSheet
Atrenta GenSys®
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Examples of Checkers and generators
• Clock and non-clock pin short error check generator• Reset and non-reset pin short error check generator• Clock ports automatic connection based on clock-
frequency property in IPXACT• Text Report generators• Clock/Reset connectivity generator• Generate verification assertions for protocol checks• CPF macro-model generator• Power Cells insertion generators
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Text Report Generators
• Reports– Audit report
• instance, port interface summary, connectivity percentage or health check
– Design difference report between two snapshots
– Design resources • black-boxes, hard
macros etc.
– Dense structures • instances with very
high pin count
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Power Cells Insertion Generator
IPXACT• Default Values for all IP outputs
IP1 IP2
IP3 IP4
IP5
Connectivity IPXACT
• SoC where all IPs are connected
Power Information• IP Instance – Power/Voltage domain association
• Power cells (isolation/levelshifters/switch cells) and their control info
top
Voltage 1 Voltage 2
Power 1 Power 2a Power 2b
Pd1_ip1
Pd1_ip2
Pd2a_ip1
Pd2a_ip2
Pd2b_ip1
Pd2b_ip2
PM
PM
PM
Power Managed SoC
• Hierarchical RTL netlist
• Power cells inserted in RTL
Generator
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Power management Generator Metrics
• No of Power Domains = 6• No of Voltage Domains = 2• No of level Shifters = 2500• No of Isolation cells = Low (26500), High (4520), Latch (260)• No of IP instances in each PD.
– PD1 = 47– PD2 = 26– PD3 = 4– PD4 = 3– PD5= 1– PD6 = 6
• Run Time = 20mins
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Other Results
Features# Designs this
feature being Used
# Issues found while SoC integration using
IPXACT checkers
If not, this issue would have been
found inRelative
Effort
Insertion of power management structures while doing SoC RTL development >10
Average of 15 per SoC RTL release
Power Aware RTL
simulations 10
Check input not connected >10Average of 12 per SoC RTL release
Lint, Verification 3
Check clock pin connected to non-clock pin 1 Total of 3 RTL simulation 2
Check reset pin connected to non-reset pin 1 0 RTL simulation 2
Active high signal connected to Active low signal 1 13 RTL simulation 5
GeneratorUsed in # of
Designs Traditional ApproachRelative
Effort
Text Report Generators to check connectivity percentage, unconnected ports, multiple drivers >10
Connectivity Percentage- Manual
Rest All - Lint 3
Clock ports automatic connection based on clock-frequency property in IPXACT 1 Manual 5
Reset Pin automatic connection based on rest attribute in IPXACT 1 Manual 5
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Conclusion• What was new?
– We have shown how IP-XACT can be used beyond the conventional way– We used a mixture of tools like SpyGlass to extract metadata into IP-
XACT automatically from RTL with minimal user inputs• Then used this IP-XACT at SoC level to develop checkers and generators
– Some of the generator outputs (like CPF macromodel, or clock constraints, etc.) can be used in other downstream flows
• E.g., verification, synthesis, static low power checks.
– These techniques ensure that metadata is captured right at the time of IP design, by the designer himself
• Ensures minimum loss of data across handoffs and saves verification time
• Some properties that are not part of IP-XACT standards currently, but can be considered in future versions of IP-XACT:
- Power domain attribute - DFT information
- Voltage domain attribute - Interrupts
- Reset attribute - DMA