WIND memory think tank - June 22, 2010 1

Magnetic memories and embedded applications

Claude CHAPPERT CNRS

"Nanospintronics" group Institut d'Electronique Fondamentale

Université Paris Sud - Orsay

SSA WIND

Mass storage Information Lifecycle Management

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Application

+ automatized migration of data from one pool to the others

Virtually unlimited capacity, extendable at will, technology robust

Memory

Fast disks

High capacity disks

Tape storage

… but not a long term « passive » archival : requires constant rewriting !

Recording : fast data rate

Backup : short recovery time/point objectives

Archival

Con

text

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Towards embedded Non Volatile STTRAM

S.H. Kang, Qualcomm, NVM Workshop, UCSD, April 11-13 (2010)

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S.H. Kang, Qualcomm, NVM Workshop, UCSD, April 11-13 (2010)

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Spin-RAM specifications “to be achieved”

Products / Demos Predicted Position vs CMOS

Cell size 20 – 80 F2 ~ 10 F2 >> NAND << SRAM

Technology Above IC embedded NVM

Speed < 40 ns (2.7 ns) ≤ ns ? ~SRAM, µP

Endurance 1015 ~ infinite >> NAND

Non volatility > 10 years

Scalability 90 nm 20 nm ? ???

Logic circuits

2009 : - new demos from Toshiba (perpendicular recording), Hitachi - agreement CROCUS-Towers for producing the TA-MRAM - large contract gov./Samsung/Hynix in South Korea to produce STT-RAM - large industry/academic contrats in Japan, France on « Magnetic logic » - many other companies : Avalanche, MagIC+IBM, GRANDIS, NEC…

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Performance assessment of memory technologies.

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Kryder+Kim, IEEE Mag45, 3406 (2009)

With CMOS technology only:

Slow communication between logic and memory

- long interconnections -complexity of interconnecting paths

-larger occupancy on wafer - large static dissipation

With hybrid CMOS/magnetic:

Fast communication between logic and memory

- numerous short vias -simpler interconnecting paths -Smaller occupancy on wafer

- instant on/off - extended possibilities for

programmation and reconfiguration

New paradigm for architecture of complex electronic circuits (microprocessors...)

Tighter integration between logic and memories

+ general trend towards programmable memory (FPGA, …)

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Low standby Power Programmable logic devices

100% 61% 0% 14%

Active Inactive

Non volatile, multi-core logic: are powered only the core that need to operate others preserve state and start « instantly » when powered on

Towards a magnetic FPGA

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

“switches” and “logic blocs” (CLB) are made: non volatile programmable by Spin- MRAM elements

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French Research Project “CILOMAG”

Towards a magnetic FPGA

CLB

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CLB

CLB

CLB

CLB

CLB

CLB

“switches” and “logic blocs” (CLB) to be made: non volatile (run-time) programmable by integrating Spin- MRAM elements

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Configuration Memory of a e-FPGA

Conf_in

CLB

TILE

SBOX

Local configuration Memory (Volatile)

Non volatile external memory to store the logic

configuration

L. Torrès, Y. Guilleminet L. Rougé

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Magnetic -TILE Design

160 µm

L. Torrès, Y. Guilleminet L. Rougé

Thermally assisted TA- MRAM (CROCUS)

New in 2010: French Research Project “SPIN”

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EETimes / June 9th, 2010 : Menta SAS and LIRMM tape out the world’s first MRAM-based FPGA enabling compact integration of MRAM and embedded-FPGA solutions :

  Menta’s eFPGA Core programmable logic architecture   CROCUS and CEA-LETI magnetic technology,   CMOS 130 nm ST Microelectronics technology   120 nm magnetic junctions   Thermally assisted writing mode (CROCUS )

Objective : customizable to use as domain specific-FPGA (dsFPGA) in a SoC with target applications features.

Same test chip: magnetic LUT, Flip-Flop, e-MRAM, by IEF and SPINTEC

First chips expected by Q4-2010

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Example of STT-RAM impact in SoC

S.H. Kang, Qualcomm, NVM Workshop, UCSD, April 11-13 (2010)

Many companies are scheduling e-MRAM powered MCU : -  Renesas (2012) -  Qualcomm/TSMC -  Grandis/NEC/Hynix -  CROCUS - …

45nm CMOS, Logic compatible e-STTRAM produced by Qualcomm/TSMC (IEDM 2009)

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S.H. Kang, Qualcomm, NVM Workshop, UCSD, April 11-13 (2010)

Summary for MRAM

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 Everspin’s MRAM is very successful, demonstrates potential and reliability of MRAM, but only on a niche market for low density/low capacity and technology not much downscalable

  CROCUS’ TA-MRAM shows higher density, speed, better downscalability (but not so much), but still remains complex. Propect: embedded MRAM, partial cache memory replacement in SoCs.

  STT-RAM technology is rapidly getting mature,BUT: to reach high densities:

- today’s current densities still too high by a factor of 3 to 5

- downscaling a uniform, high enough value of magnetic anisotropy on a large array is a problem (Toshiba: perp. magnetization, Hitachi: synthetic AF free layer, CROCUS: exchange bias to AF layer)

STT-RAM has potential for 3D stacking ! (controller area << RAM area)

STT-RAM getting adapted for mass storage ?

MLC STT-RAM has been demonstrated (Hitachi, VLSI 2010)