Abstract—This work is the extension of the work done for the

VHDL implementation of GCD processor using Xilinx 9.2 ISE. In

this work, a comparative analysis of using tools Xilinx 13.1 ISE and

Xilinx 9.2 ISE is shown for the 4-bit GCD Processor implementation

using Euclid's Algorithm. While designing any processor, processing

speed and using of resources of processor is an important part to be

taken into consideration. Processor resources are to be smartly

utilized while implementing Greatest Common Divisor Processor

using VHDL. Simulation is done on Xilinx 13.1 ISE.

Keywords— Arithmetic and Logic Unit , Built in Self

Test(BIST) , Euclid's Algorithm, Greatest Common Divisor, Xilinx

13.1 ISE.

I. INTRODUCTION

n arithmetic logic unit (ALU) is a digital circuit that

performs arithmetic and bitwise, logical operations

on integer binary numbers. Most of a processor's operations

are performed by one or more ALUs. An ALU loads data

from input registers. Then an external control unit tells the

ALU what operation to perform on that data, and then the

ALU stores its result into an output register. The control unit is

responsible for moving the processed data between these

registers, ALU and memory.

Fig. 1 ALU of a Processor

Sachin D.Kohale , Assistant Professor, Dept. of Electronics and

Telecommunication Engineering , St. John College of Engineering

Palghar, Mumbai, Maharashtra , India. Email id: sdk_pz@yahoo.com

II. GREATEST COMMON DIVISOR

A. Introduction

The greatest common divisor (gcd) of two or more integers,

when at least one of them is not zero, is the largest positive

integer that divides the numbers without a remainder. Greatest

common divisors can in principle be computed by determining

the prime factorizations of the two numbers and comparing

factors, as in the example shown in Fig. 2 below.

Fig. 2 GCD of two non-negative numbers

B. Applications

Greatest Common Divisor(GCD) can be used in various

applications such as data security, cryptography etc.

C. Euclid's Algorithm for GCD Calculations

Euclid's algorithm, is a method for computing the greatest

common divisor(GCD) of two (usually positive) integers, also

known as the greatest common factor (GCF) or highest

common factor (HCF). In its simplest form, Euclid's algorithm

starts with a pair of positive integers, and forms a new pair that

consists of the smaller number and the difference between the

larger and smaller numbers. The process repeats until the

numbers in the pair are equal. That number then is the greatest

common divisor of the original pair of integers. The main

principle is that the GCD does not change if the smaller

number is subtracted from the larger number. For example, the

GCD of 252 and 105 is exactly the GCD of 147 (= 252 − 105)

and 105. Since the larger of the two numbers is reduced,

repeating this process gives successively smaller numbers, so

this repetition will necessarily stop sooner or later — when the

numbers are equal (if the process is attempted once more, one

of the numbers will become 0).

Comparative Analysis of Implementation of

4-bit GCD Processor with Built in Self Test

Feature using Xilinx 13.1 ISE & Xilinx 9.2 ISE

Sachin D.Kohale

A

International Journal of Computer Science and Electronics Engineering (IJCSEE) Volume 3, Issue 1 (2015) ISSN 2320–4028 (Online)

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III. BUILT IN SELF TEST

A. Introduction

A built-in self-test (BIST) or built-in test (BIT) is a

mechanism that permits a machine to test itself. BIST feature

is added to GCD Processor to meet the requirements such as:

high reliability and lower repair cycle times or constraints such

as limited technician accessibility and cost of testing during

manufacture.

B. Applications

BIST is commonplace in weapons, avionics, medical

devices, automotive electronics, complex machinery of all

types, unattended machinery of all types, and integrated

circuits.

IV. SPARTAN 3 FPGA FAMILY

A. Introduction

The Spartan 3 family of Field-Programmable Gate Arrays is

specifically designed to meet the needs of high volume, cost-

sensitive consumer electronic applications. The eight-member

family offers densities ranging from 50,000 to five million

system gates. The Spartan-3 family builds on the success of the

earlier Spartan-IIE family by increasing the amount of logic

resources, the capacity of internal RAM, the total number of

I/Os, and the overall level of performance as well as by

improving clock management functions. Spartan-3 FPGAs

provide the necessary density and DSP features to enable

designers to build high performance DSP systems. These

features include:

1) Up to 104 18x18 bit embedded multipliers. These can be

used to implement customized DSP structures such as MAC

engines, fully parallel FIR filters, FEC codecs and digital

communications and imaging applications.

2) Block RAM for storing partial products and coefficients for

applications such as high-speed filtering. Fig. below shows Kit

contains Spartan 3 FPGA which was used.

Fig 3. Kit Contains Spartan 3 FPGA

B. Use of Spartan 3 for GCD Processor Designing

Fig 4. Hardware Experimental Setup of 4 –bit GCD Processor using

Spartan 3 FPGA

Fig 4. above shows hardware experimental setup of 4-bit

GCD Processor implementation using Spartan 3 FPGA. The

GCD output can be visualize on pairs of LEDs.

C. Advantages of Spartan 3

1) 3 domain-optimized platforms for lowest-cost fit to each

application.

2) SelectIO™ Technology with on-chip differential

termination and widest I/O standards compliance, including

LVDS, RSDS, mini-LVDS, PPDS and TMDS.

3) Pre- or post-processing video enhancement, LVDS TxRx

(FPDLink), and peripheral interface bridging solution.

4) TCON (timing control) and video co-processing flexibility

5) Flexible peripheral interfacing and video switching.

6) Reference designs for precise gamma correction, image

dithering, color temperature correction and other video-

enhancement functions.

V. SIMULATION RESULTS AND DISCUSSIONS

Fig. 5. Comparison of 4-bit GCD Processor design using Xilinx

13.1 ISE and using Xilinx 9.2 ISE

0

20

40

60

80

100

120

140

160

180

200

Number of Bounded

IOB's

Number of 4-input LUT's

Number of Occupied

Slices

Number of Slice

Registers

Using Xilinx 9.2 ISE

Using Xilinx 13.1 ISE

International Journal of Computer Science and Electronics Engineering (IJCSEE) Volume 3, Issue 1 (2015) ISSN 2320–4028 (Online)

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Fig. 5 above shows the comparative analysis of 4-bit

Greatest Common Divisor (GCD) processor designing using

Xilinx 13.1 and Xilinx 9.2 versions.

Looking at graph above, we can easily found out that

using Xilinx 13.1 ISE, we can smartly use of Spartan 3

Processor due to limited use of resources. As limited number

of resources are to be used , the time required for Spartan 3

processor for accessing data from the memory is less. So,

within quick time, Spartan 3 processor able to evaluate GCD

of two non-negative integers. This concept is very useful in

applications where processing time is an important factor taken

into consideration.

Table I below shows comparative parameters that are to

be found out during simulations using Xilinx 13.1 ISE and

Xilinx 9.2 ISE versions while designing 4-bit GCD

Processor using Spartan 3 FPGA Family.

TABLE I

PARAMETERS OF 4-BIT GCD PROCESSOR WITH BIST USING XILINX 13.1 ISE

AND XILINX 9.2 ISE

Parameters Xilinx 13.1 ISE Xilinx 9.2 ISE

Number of

Bounded IOB's

19

20

Number of 4-

Input LUT's

90

106

Number of

Occupied Slices

50

71

Number of

Slice Registers

10

67

Fig. 6. Snapshot of simulation output of 4-bit GCD Processor

using Xilinx 13.1 ISE

Fig. 7. Simulation output of 4-bit GCD Processor

Fig. 6 shown above shows snapshot of 4-bit GCD processor

designing using Xilinx 13.1 ISE. Also, Fig. 7 above shows

simulation output for calculating 4-bit GCD for two non-negative 4

bit numbers.

VI. CONCLUSION

From above discussions and simulation results, it is clear

that using Xilinx 13.1 ISE is having advantages in the sense

that it gives better scope for using limited resources of the

processor. Although, power consumption is the parameter that

needs to take care of while using this tool. Xilinx 13.1 ISE

also gives access for Spartan 6 FPGA, i.e. advanced of Spartan

3 FPGA family.

International Journal of Computer Science and Electronics Engineering (IJCSEE) Volume 3, Issue 1 (2015) ISSN 2320–4028 (Online)

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APPENDIX

1) Slice : Two slices form a CLB within Spartan®-II and

Virtex® families. This is a specific example of a comp type

that corresponds to the basic fabric of logic in all FPGA’s.

2) Look-Up Table (LUT) : Look-up tables (LUTs) are used to

implement function generators in CLBs. Four independent

inputs are provided to each of two function generators (F1-F4

and G1-G4). These function generators can implement any

arbitrarily defined Boolean function of four inputs. The H

function generator can implement any Boolean function of

four inputs.

3) IOB (input/output block) : A collection or grouping of basic

elements that implement the input and output functions of an

FPGA device.

4) Gate : An integrated circuit composed of several transistors

and capable of representing any primitive logic state, such as

AND, OR, XOR, or NOT inversion conditions. Gates are also

called digital, switching, or logic circuits.

5) Gate Array : It is a Part of the ASIC chip. A gate array

represents a certain type of gate repeated all over a VLSI-type

chip. This type of logic requires the use of masks to program

the connections between the blocks of gates.

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Sachin D. Kohale received Bachelor of

Engineering (B.E.) degree in Electronics from

K.D.K.College of Engineering ,Nagpur,

Maharashtra, India in 2008. He has completed

Master of Engineering(M.E.) in Embedded

System and Comput ing (ESC) from G.H.Raisoni

College of Engineering, Nagpur, Maharashtra,

India. He is now at present working as Assistant

Professor in Electronics and Telecommunication

Department in St. John College of Engineering

and Technology, Palghar, Mumbai, Maharashtra,

India. His research area includes VLSI, Signal

Processing, Embedded System.

International Journal of Computer Science and Electronics Engineering (IJCSEE) Volume 3, Issue 1 (2015) ISSN 2320–4028 (Online)

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