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Lecture21

DetectingandHandlingHazards

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PipelineHazards

Whatifthenextinstructioncannotexecuteinthefollowingclockcycle?

Structuralhazard:

Badhardwaresupport.

Wecantexecuteacombo

ofinstructionsinthesame

clockcycle.

Example: memory.

Solution:stall,design.

Controlhazard:

Theresultofoneinstructiondetermines

whathappenstootherinstructions..

Example: branch.

Solutions:stall,reorder,predict.

Datahazard:

Aninstructiondependsontheresultresultofapreviousinstruction

thatisstillinthepipeline..Example: add$s0,$t0,$t1sub$t2,$s0,$t3

Solution:stall,reorder,forwarding(orbypassing).

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DataHazardsandForwarding

sub $2, $1, $3

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

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IM Reg

IM Reg

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6

Time (in clock cycles)

su b $2, $1, $3

Program

executionorder(in instructions)

and $12, $2, $5

IM Reg DM Reg

IM DM Reg

IM DM Reg

CC 7 CC 8 CC 9

10 10 10 10 10/20 20 20 20 20

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Value of register $2:

DM Reg

Reg

Reg

Reg

DM

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sub $2, $1, $3

nop

nop

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2sw $15, 100($2)

Possiblesolution: Letthecompilerresolvethehazard

bubble

bubble

Hardwaredesign:

Registerwritesalways

happenatthefirsthalf

oftheclockcycle.

Registerreadsalways

happenatthesecondhalftheclockcycle.

Nohazardfordatathat

iswrittenandreadinthe

sameclockcycle.

Question: Whatisthedrawbackofthissolution?

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sub $2, $1, $3

nop

nop

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

bubble

bubblesub $2, $1, $3

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

nop =sll $0,$0,0

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IM Reg

IM Reg

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6

Time (in clock cycles)

su b $2, $1, $3

Program

executionorder(in instructions)

and $12, $2, $5

IM Reg DM Reg

IM DM Reg

IM DM Reg

CC 7 CC 8 CC 9

10 10 10 10

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Value of register $2:

DM Reg

Reg

Reg

Reg

DM

Hardwaredesign:*Registerwritesalwayshappenatthefirsthalfoftheclockcycle.*Registerreadsalwayshappenatthesecondhalftheclockcycle.

*Nohazardfordatathatiswrittenandreadinthesameclockcycle.

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ID/EX EX/MEM MEM/WB

IF/ID

Question: Howcanonespotahazardisinprogress?

1a.EX/MEM.Rd=ID/EX.Rs

1b.EX/MEM.Rd=ID/EX.Rt

2a.MEM/WB.Rd=ID/EX.Rs2b.MEM/WB.Rd=ID/EX.Rt

Example:

sub $2,$1,$3

and $12,$2,$5

or $13,$6,$2

*

(*)DetectablewhensubisinMEM. (**)DetectablewhensubisinWB.

**

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Constraints:

1) Notallinstructionswritetoregisters:needtoforwarddata

whichiswrittentoandthenreadfromaregister

=>lookatRegWriteinWBfieldofEXandMEM.

2) $0mustalways have0;mustbecarefulnottoforward

anythingiffoolishprogrammerused$0asdestination.This

wayprogrammersareprotectedfromtheirownmistakes.

3) Theregisterfiletakescareofinternallyforwardingdata

thatiswrittentoandreadfrominthesameclockcycle.

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IM Reg

IM Reg

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6

Time (in clock cycles)

su b $2, $1, $3

Programexecution order(in instructions)

and $12, $2, $5

IM Reg DM Reg

IM DM Reg

IM DM Reg

CC 7 CC 8 CC 9

10 10 10 10

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Value of register $2 :

DM Reg

Reg

Reg

Reg

X X X X X X X XValue of EX/MEM :

X X X X X X X XValue of MEM/WB :

DM

IM Reg

IM Reg

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6

Time (in clock cycles)

su b $2, $1, $3

Programexecution order(in instructions)

and $12, $2, $5

IM Reg DM Reg

IM DM Reg

IM DM Reg

CC 7 CC 8 CC 9

10 10 10 10

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Value of register $2 :

DM Reg

Reg

Reg

Reg

X X X X X X X XValue of EX/MEM :

X X X X

X X X XValue of MEM/WB :

DM

IM Reg

IM Reg

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6

Time (in clock cycles)

su b $2, $1, $3

Programexecution order(in instructions)

and $12, $2, $5

IM Reg DM Reg

IM DM Reg

IM DM Reg

CC 7 CC 8 CC 9

10 10 10 10

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Value of register $2 :

DM Reg

Reg

Reg

Reg

X X X X X X X XValue of EX/MEM :

X X X X X X X XValue of MEM/WB :

DM

NoticehowdataisnowforwardedfrompipelineregisterstotheALU.

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Question: Theforwardingschemeaddsalternativesources

totheinputsoftheALU.Howdoesthischangethedatapath?

PCInstructionmemory

Registers

Mux

Mux

Control

ALU

EX

M

WB

M

WB

WB

ID/EX

EX/MEM

MEM/WB

Datamemory

Mux

Forwardingunit

IF/ID

Instru

ction

Mux

RdEX/MEM.RegisterRd

MEM/WB.RegisterRd

Rt

Rt

Rs

IF/ID.RegisterRd

IF/ID.RegisterRt

IF/ID.RegisterRt

IF/ID.RegisterRs

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ControllingtheForwardingUnit

1) EXhazard:

if((EX/MEM.RegWrite)

and(!EX/MEM.RegisterRd)

and(EX/MEM.RegisterRd=ID/EX.RegisterRs))

then

ForwardA=10

if((EX/MEM.RegWrite)

and(!EX/MEM.RegisterRd)

and(EX/MEM.RegisterRd=ID/EX.RegisterRt))

then

ForwardB=10

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ControllingtheForwardingUnit

2) MEMhazard:

if((MEM/WB.RegWrite)

and(!MEM/WB.RegisterRd)

and(MEM/WB.RegisterRd=ID/EX.RegisterRs))

then

ForwardA=01

if((MEM/WB.RegWrite)

and(!MEM/WB.RegisterRd)

and(MEM/WB.RegisterRd=ID/EX.RegisterRt))

then

ForwardB=01

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2nd ALUfromdatamemoryorearlierALUresultMEM/WBForwardB=01

2nd ALUforwardedfromALUresultEX/MEMForwardB=10

2nd ALUfromRegFileID/EXForwardB=00

1st ALUfromdatamemoryorearlierALUresultMEM/WBForwardA=01

1st ALUforwardedfromALUresultEX/MEMForwardA=10

1st ALUfromRegFileID/EXForwardA=00

ExplanationSourceMUXcontrol

PCInstructionmemory

Registers

Mux

Mux

Control

ALU

EX

M

WB

M

WB

WB

ID/EX

EX/MEM

MEM/WB

Datamemory

Mux

Forwardingunit

IF/ID

Instruction

Mux

RdEX/MEM.RegisterRd

MEM/WB.RegisterRd

Rt

Rt

Rs

IF/ID.RegisterRd

IF/ID.RegisterRt

IF/ID.RegisterRt

IF/ID.RegisterRs

A

B

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Workthroughtheexampleoftheexecutionof

fourinstructionsstartinginpage485!

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Question: doesthisdatapath nowcoverforallcasesofhazard

resolutionbyforwarding?

A L U S rcRegisters

Mux

Mux

Mux

ALU

ID /E X ME M/WB

Datamemory

Mux

Forwardingunit

EX/MEM

Mux

ALUsourceselectiontodealwithsignedimmediates.

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Question: again,doesthisdatapath nowcoverforallcasesof

hazardresolutionbyforwarding?

Reg

IM

Reg

Reg

IM

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6

Time (in clock cycles)

lw $2, 20($1)

Program

executionorder(in instructions)

an d $4, $2, $5

IM Reg DM Reg

IM DM Reg

IM DM Reg

CC 7 CC 8 CC 9

or $8, $2 , $6

add $9, $4 , $2

slt $1, $6, $7

DM Reg

Reg

Reg

DM

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HazardDetectionUnit

if((ID/EX.MemRead)and((ID/EX.RegisterRt=IF/ID.RegisterRs)or

(ID/EX.RegisterRt=IF/ID.RegisterRt)))

then

stallthepipeline

stallthepipeline: deassert allcontrollinesinstages

EX,MEMandWBtoaccomplish

adonothingeffect(bubble).

Thebubblefloatsonthroughthepipeline.

ThishappensattheIDstage.Wemustalsoguaranteethatduring

thestalledcycle,PCandIF/IDdontchange.

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lw $2 , 20($1)

Program

execution

order

(in instructions)

an d $4 , $2 , $5

or $8, $2 , $6

add $9, $4 , $2

slt $1, $6, $7

Reg

IM

Reg

Reg

IM DM

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6

Time (in clock cycles)

IM Reg DM RegIM

IM DM Reg

IM DM Reg

CC 7 CC 8 CC 9 CC 10

DM Reg

RegReg

Reg

bubble

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PCInstruction

memory

Registers

Mux

Mux

Mux

Control

ALU

EX

M

WB

M

WB

WB

ID/EX

EX/MEM

MEM/WB

Datamemory

Mux

Hazarddetection

unit

Forwardingunit

0

Mux

IF/ID

Instruction

ID/EX.MemRead

IF/IDW

rite

PCWrite

ID/EX.RegisterRt

IF/ID.RegisterRd

IF/ID.RegisterRt

IF/ID.RegisterRt

IF/ID.RegisterRs

Rt

Rs

Rd

RtEX/MEM.RegisterRd

MEM/WB.RegisterRd

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Workthroughtheexampleoftheexecutionof

fiveinstructionsstartinginpage491!