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CSCM type test
Status of the preparation of the CSCM type test
MPE-TM31 January 2013
M. Bernardini, B. Bordini, K. Brodzinski, Z. Charifoulline, G. D’Angelo, A. Gorzawski,A, Perin, M. Pojer, M. Solfaroli Camillocci, J. Steckert, H. Thiesen A. Verweij, G. Willering
The CSCM type test• The CSCM type test is planned:
– In sector 23 on the three main circuits: RB.A23, RQD.A23 and RQF.A23– End of powering tests: 02/03– End of ElQA: 17/04– Warm up of the sector between 1.9 K and 20 K: 18/04 to 24/04– Powering tests including ElQA before and after: 25/04 to 10/05– Preparation of the CSCM type test must be done before ElQA: 11/03 to 03/04
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RP survey
CSCM Reparation phase (11/03 – 03/04)
M. Bernardini
TE-CRG-OA_K.Brodzinski, 30.01.2013 3
Two scenarios considered (depending on current leads cooling requirements):1. Whole sector in GHe –> arc @ 20 K within range of +/- 10 K, P=5 bara (within range of +/- 0.5 bar),
DFBs: TT891A stabilized at 50 K or lower (~35-40 K), P=~1.8 bara2. Using LHe for DFBs with normal cooling scheme, while keeping arc magnets with GHe between ~10
and ~40 K (bad homogeneity over the sector length).
Scenario 1 – relatively elegant and feasible (cold part of main cold box OFF, 20 K GHe in main supply line for tunnel cooling)Scenario 2 – complicated because of requirements of LHe in DFBs and GHe in arc at the same time, re-cooling of arc magnets up to 20 K with supply helium at 4.5 K is difficult, bus bars between DFB and first Q10 or Q11 will be probably in supra state ...
Recovery after the test (between the tests) can be done during the night (CCC cryo shift available 24/24 h), rough estimated time recovery ~5 hours +/- … (depending on introduced energy and chosen scenario)
The cryogenic status for CSCM type test 1/2TE
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TE-CRG-OA_K.Brodzinski, 30.01.2013 4
The total related energy introduced to the magnet system will be at max. ~300 MJ (part of that going to the magnets material and other part going to helium causing increase of pressure in the cold mass).
Because of the equipment safety reasons two precautions have to be considered for the test:• Test to be started with small steps of circuits powering to understand the pressure response of the
system especially in DFBs and cold mass volumes, then progressively increased.• The cold mass pressure of ~15 bara should not be exceeded (no fast discharge of helium via the QVs).
The cryogenic interlocks CS and CM will be simulated no protection for circuits powering will be guarantied from the cryogenic side.
The specific procedures will be put in place to prepare and perform the tests. We need to know ASAP which scenario will be applied for the first test (DFBs at 4.5 or 20 K)?
The required configuration was never done – strong prudence is to be applied !
The cryogenic status for CSCM type test 1/2TE
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The Power Converter status
• The connection in parallel of the two output chokes has be decided (avoid the saturation of the chokes)
• Grounding of the circuit under test will be done at the level of the power converter (avoid earth modification)
• No real difference with the tested configuration in P-Hall• The power converter will be limited at 8 kA for the type test (no time to valid the operation at 12
kA)
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(+)
(-)
The Power Converter status
• This “new” configuration will be tested in P-Hall in February (1 week)• The modification of the RB.23 power converter and its IST will be done in
March (2 weeks)• “Modification and IST procedure” of the RB.A23 power converter (including
the 13kA-EE system and the PIC recabling) will be ready for approval at the end of February
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The circuit protection system status
• mDQQBS hardware status– 60 boards for rework (extended range) with TE-MPE-EM (Betty)– Production tester operational, 2nd to be re-activated– All boards have to be re-programmed with latest firmware and tested
• mDQQBS firmware status– Firmware development ongoing– Watch dog feature still pending– Simulation results can be re-played in tester software– Changed behavior of dvdt threshold:
active after activation with elevated threshold (sunglasses) normal dvdt threshold after fixed time
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7Z. Charifoulline and J. Steckert
The circuit protection system status
• Firmware testing
Simulated run-away data
mDQQBS logging output, triggers at dvdt (20mV/s), voltage threshold set to 1V
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8Z. Charifoulline and J. Steckert
No thermal runaway Thermal runaway
Defect size (mm)MIIt's I_max t_wait 7.5 9 12 15 21 30 A: VTHRES B: VTHRES A: dVTHRES B: dVTHRES
[A] [s]
771 4000 2 X X X X X X1060 4000 20 X X X CS-263 80 120 10 201860 4000 70 X X X CS-261 120 180 10 201775 6000 2 X X X X CS-153 CS-163 110 170 10 202570 6000 24 X X X CS-250 CS-262 220 300 10 203360 6000 46 X X CS-251 X 200 300 10 204220 6000 70 X CS-231 CS-241 CS-260 350 500 10 203180 8000 2 X X CS-132 CS-142 CS-152 CS-162 200 300 20 305740 8000 42 CS-210 CS-230 CS-240 750 950 20 304983 10000 2 X CS-110 CS-131 CS-141 CS-151 X 500 650 30 407187 12000 2 CS-120 CS-111 CS-130 CS-140 X X 1300 1700 40 50
The test sequence for CSCM:QP3 simulations for 40m RB bus bar (as example).mDQQBS default thresholds and settings - ongoing
mDQQBS Thresholds
The circuit protection system status
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Z. Charifoulline
Current Cycles
Voltages
dV/dt
QP3 simulations for 40m RB bus bar
dV/dt -thresholddelayed or elevated
The circuit protection system status
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Z. Charifoulline
• mDQQBS <-> Labview– QP3 simulations for RB (40m) and RQ (120m) test runs (done)– Thresholds estimations from simulations for all lengths (ongoing)– Thresholds loading and verification (done but with one crate in b281)– mDQQBS buffers manipulations (done but with one crate in b281)– Splice Monitor modification to analyse CSCM data from TIMBER or
buffers (ongoing)– EXCEL analysis tools of buffers data (???)
Desktop <-> b281
The circuit protection system status
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Z. Charifoulline
CSCM automated data/commands workflow
• mBS cards produce ~300 files /sector for RB and ~108 files /sector for RQ– clear need for automation processing of them.
• Originally buffer is recorded at 2*16.65Hz (total buffer length 6000 points)• No regular PM is sent in that case, only internal buffer contains the recorded
signals.• Triggerd to record and send buffer will be done by gateway macro (Jens to
specify this to EN/ICE) • Buffer is sent to Logging DB with 5Hz sampling, hence has to be processed
and treated in order to restore it’s original sampling rate (due to known problem with field bus controller, some of data has to be interpolated as well).
• After each sequence: (…), buffer recording, buffer send from board A, buffer send from board
B(…)software tool has to be called In order to readout and process both buffers coming from Logging DB. (see next two slides)
• Output data will be stored as (standard) PM data object (or CSV files)
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12A. Gorzawski
Signal life cycle pt.1
• mBS ‘treatment’ (possible for ALL signals in one sector!, here only 2 sets of 2 signals during noise test)
Extracted from LoggingDB
Resampled (5Hz -> 33Hz)
Rescaled to original values.
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13A. Gorzawski
Signal life cycle pt.2
• For each markers found, special search algorithm is started to find:– What was the time (as absolute time tamp, when the signal was recorded). – What was actual board selected (both search are based on state change of corresponding signal associated with one crate when request for recording is sent)
• Results are stored as PM data (if needed raw CSV files format is provided)
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14A. Gorzawski
Sequencer and ACCTEST framwwork
• Reuse HWC tool to realize the CSCM powering test from the CCC– HWC Sequencer– ACCTEST
• HWC Sequencer– 1st draft of the specification has been sent to Markus– Reuse PIC sequence for interlock tests before powering tests– Missing: Script for data triggering (Z. Charifoulline and J. Steckert)
• ACCTEST– All the test will be tracked in ACCTEST framework not recorded in MTF and not automatically
analyzed
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# Action Description Parameters Criteria FGC commande1 PC Ok Ask PC team to check the
CSCM_I_limit[i]limits.i.hardware = CSCM_I_limit[i]limits.i.pos[0] = CSCM_I_limit[i]
g limits.i.hardwareg limits.i.pos[0]
2 Cryo OK Ask cryo team the Cryo_OK Cryo_Ok change from NOK to OK3 Ppermit Reset the circuit faults
Give the PPermitPPermit change from NOK to OK s pc of
4 Start up the PC Turn on the PC and wait untilthat the PC is in Stand By state
PC state in SBI_Meas = I_CSCM_min
s pc sbg meas.i
5 Wait CSCM_SB_timeat SB
When the PC is at SB,Reset the PC maximum earth currentwait CSCM_SB_timeread PC maxmium earth current
i_earth < i_earth_max g meas.max.i_earth zerog meas.max.i_earth
6 Ramp to I_CSCM_Flat_Bottom Ramp the current toI_CSCM_Flat_Bottom withCSCM_d2idt2 and CSCM_didt
s pc ils ref now,{i_final},{d2idt2\},{didt}
7 Wait CSCM_Bottom_timeat I_CSCM_Flat_Bottom
When the PC is at I_CSCM_Flat_BottomReset the PC maximum earth currentwait CSCM_Bottom_timeread PC maximum earth current
i_earth < i_earth_max g meas.max.i_earth zerog meas.max.i_earth
8 QPS trigger Ask QPS team to lunch the acquisition9 Ramp to I_CSCM_Flat_Top[i] Ramp the current to
I_CSCM_Flat_Top[i] withCSCM_d2idt2 and CSCM_didt
s ref now,{i_final},{d2idt2},{didt}
10 Wait CSCM_Top_time[i]at I_CSCM_Flat_Top[i]
When the PC is at I_CSCM_Flat_Top[i]Reset the PC max. earth currentwait CSCM_Top_time[i]Read the PC max. earth current
i_earth < i_earth_max g meas.max.i_earth zerog meas.max.i_earth
11 Ramp down to I_CSCM_minwith exponential decay
Ramp down the current toI_CSCM_min with CSCM_d2idt2 andCSCM_time_constant
s ref plep,{i_final},{d2idt2},{didt},{tau}s ref.run
12 turn off the PC when the PC is at I_CSCM_minturn off the PC
s pc sbs pc of
ElQ
A te
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CRYO
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QPS
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EE te
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MP3
CSCM_CRYO_ISTCSCM_QPS_ISTCSCM_EE_ISTCSCM_PC_IST
CSCM_ElQA 4/19/2013
CSCM_PIC_1.1:PpermitCSCM_PIC_1.2:QPS_CLCSCM_PIC_1.3:QPS_SpliceCSCM_PIC_1.4:QPS_MagnetCSCM_PIC_1.5:EECSCM_PIC_1.6:PCCSCM_PIC_1.7:PIC
CSCM_PCC
CSCM_PIC_2.5:EE
CSCM_Power_Cycle_1CSCM_Power_Cycle_2CSCM_Power_Cycle_3CSCM_Power_Cycle_4CSCM_Power_Cycle_5CSCM_Power_Cycle_6CSCM_Power_Cycle_7CSCM_Power_Cycle_8CSCM_Power_Cycle_9CSCM_Power_Cycle_10CSCM_Power_Cycle_11
CSCM_ElQA_After
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i_PC
Current Lead tests in SM18
• Test in planned at the end of February (priority to the diodes)• No needed if the DFBAs will be at nominal condition for the type test
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B. Bordini
Documentation
• First Draft of the “CSCM type test procedure” has been written (on my public).• Several parameters must be fixed
– DFBA conditions: 20K or 4.5 K– Maximum current: 8 kA or less– Maximum safe energy: 4 TeV or more
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Documentation
• First draft of the “Risk Analysis” document will be written for the mid of February
• First draft of the “IST” will be written for the end of February– Power converter (including EE system and PIC recabling)– Circuit protection system– Cryogenic configuration
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Showstopper and next steps
• Showstopper– CCC will be in maintenance during CSCM type tests
• Next steps– Finalise the tests procedures
• CSCM type test procedure• IST (power converter, QPS and CRYO)• Risk analysis
– Define a realistic detailed planning of the type test• Type test can be done only by the experts• Time is mainly spent by data reading and analysis and by cryo recovery specially
if the DFBAs are operated at nominal conditions
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Parameter SpecificationInput channels 1 (U_Splice)ADC resolution nominal
24 bit
Input range +/-2.56VLSB 305nVSampling speed 16.65Hz, 33.3HzFiltering Hardware sinc3 filter with first notch on 50HzDetection algorithm Dual, absolute value and dv/dt (delayed) both bipolarAbsolute threshold 8bit in 10mV steps (0..2.56V), in case of extended range x4dV/dt threshold 4bit in 10mV steps (0..150mV), in case of extended range x4DAQ buffer 6000points @ 24bit 360s at f=16.65Hz or 180s at f=33.3HzDetection speed sample – sample 60ms + computing time, overall <100ms
DQQBS value mDQQBS function/valueL_COMP ThresholdU_RES dvdt(Ubus)U_MAG UbusD_PARAM command/threshold dv/dt
DQQBS command hex mDQQBS functionSend Logging 0x01 Send Logging (goes into logging state)Test_mode_EQ1 0x05 Triggers Test modeZero_Calibrate_ON 0x03 Disarm dv/dt detectionSend_Temperature 0x04 Resets trigger Set_Parameter_DQQBS 0x0B Sets the D_PARAM see below for encodingSet_Compensation_DQQBS 0x0A Sets the threshold see below for encoding
Bit Function7 Buffer records if set, switches back to 0
when buffer is full6 mBS returns buffered values on U_mag
and U_res when set, switches back to 0 if buffer has been fully transmitted (buffer contains artificial start (- full scale) and end marker (+ full scale)
5 RESERVED4 RESERVED3:0 dv/dt threshold: 4 bit (16 values) *
10mV 0..150 mV/s
mDQQBS: Specification, commands, control parameters
The circuit protection system statusTE
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Z. Charifoulline
