DIPARTIMENTO DI ELETTRONICA E INFORMAZIONE

Novel,EmergingComputing System Technologies

Smart Technologies Smart Technologies for Effective Reconfiguration:for Effective Reconfiguration:The FASTER approachThe FASTER approach

May 29th – 31st 2013International Conference on IC Design and Technology

Pavia, Italy

M. D. Santambrogio, C. Pilato, D. Pnevmatikatos, K. Papadimitriou, D. Stroobandt, D. Sciuto

http://www.fp7-faster.eu/

Reconfigurable TechnologyReconfigurable Technology

• Technology for adaptable hardware systems Can add/remove components at

run-time/product lifetime Flexibility at hardware speed (not quite ASIC) Parallelism at hardware level (depending on

application) Ideally: alter function & interconnection of

blocks• Implementation in:

FPGAs: fine grain, complex gate plus memory and DSP blocks

Coarse Grain (custom) chips: multiple ALUs, multiple (simple) programmable processing blocks, etc.

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An issue as a new opportunityAn issue as a new opportunity

• Programming has become very difficult Impossible to balance all constraints manually

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• More computational horse-power than ever before Cores are free, reconfigurable logic available on chip,

cores can be heterogeneous• Energy is new constraint

Software must become energy and space aware

• Modern computing systems need to be flexible and adaptive To optimize and meet their requirements taking

advantage as much as possible of the underlying complex heterogeneous architectures

FASTER MotivationFASTER Motivation

• Creating reconfigurable systems is not straightforward! Reconfiguration cost is substantial (use wisely) Tool support for these tasks is still quite basic Resource management is up to the user

The designer has to: Identify portions to be reconfigured Establish a schedule that (a) respects

dependencies (b) achieves performance and other constraints

Manage the system resources (also at run-time) Verify a changing system!

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FASTER Goals and InnovationFASTER Goals and Innovation

• Include reconfigurability as an explicit design concept in computing systems design, along with methods and tools that support run-time reconfiguration in the entire design methodology Provide a framework for analysis, synthesis

and verification of a reconfigurable system Provide efficient and transparent runtime

support for partial and dynamic reconfiguration, including micro-reconfiguration

• Demonstrate usability & performance on commercial applications and platforms (Maxeler, ST Microelectronics, Synelixis)

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FASTER PlatformsFASTER Platforms

• Bridging the gap between HPC and embedded systems Opportunities and challenges of reconfiguration

in both the domains

• High-Performance Computing Systems Maxeler MPC MaxWorkstation

• FPGA-based Embedded Systems Xilinx University Program Board (XUPV5-

LX110T) AVNET Zedboard (SoC XC7Z020)

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FASTER: Overall MethodologyFASTER: Overall Methodology

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Design Phase and Runtime Design Phase and Runtime SupportSupport

• Define a reconfiguration-aware design methodology that exploits FPGAs: Generate hardware and software components (including runtime support) on the

top of existing vendor flows• Exploit dynamic reconfigurability for different target reconfigurable

architectures. Both HPC and embedded systems

• Define and implement a new generation of self reconfigurable architectures based on Linux

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System analysis and designSystem analysis and design

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.c

Task Graph Generation

High Level Analysis

DFG Extraction

Static Baseline Scheduling

Partitioningand Optimizations

Run-time Support and Verification

.xml

.c .xml

- Architecture- Additional application

information

- Annotated source code(C+OpenMP)

- Source code for CPU- DFGs for HW blocks- Mapping Configurations

Mapping and Floorplanning

- HLS- System generation

.xml

Identifying Level of Identifying Level of ReconfigurabilityReconfigurability

• Assigning each task of the application to the “best” processing element Reconfiguration is implicitly considered

• Based on a metaheuristic iterative algorithm

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Objectives: function of occupation area, execution time, power, number of reconfigurations etc...

T1

T2 T3 T4

T5

Architectural TemplateXML

MAP MappingMAP

Iterative, multi objectives:-Runtime-Power-Area-…

Convergence

Library XML

Micro-reconfiguration Micro-reconfiguration OptimizationOptimization

• In some applications we can identify hardware accelerators with slow‐changing “parameters” Filter coefficients

• Parameters trigger a small-scale reconfiguration

• Design of cores based on Tunable FPGA blocks: Identify parameters Create bitfile with “holes” Parameter values => reconfiguration bits for

missing “holes” Fine grain, faster reconfiguration time!

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Verifying Reconfigurable Verifying Reconfigurable SystemsSystems

• Study design validation approaches: simulation, emulation and formal verification

• Extend symbolic simulation to dynamic aspects of reconfigurable design

• In some cases static approaches may not be able to verify the entire RC system We use run‐time verification. Address and

minimize impact on:• Speed, area and power• Light‐weight architectural support

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Run-time SystemRun-time System

• Evaluate reconfiguration overhead

• Propose advanced mechanisms to support Scheduling Dynamic reconfiguration (including micro-

reconfiguration) Run-time verification

• Provide run-time support for dynamic reconfiguration based on static analysis Extension of OS capabilities Efficient on-line scheduling and placement of

task modules

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OS-based ManagementOS-based Management

• Provide software support for dynamic partial reconfiguration on a Linux-based operating systems Reconfiguration process managed from the

OS in a transparent way

• Hardware-independent interface for software developers based on the GNU/Linux Addition and removal of reconfigurable

components

• Easier programming interface for specific drivers OS customization for specific architectures

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Expected Results and ConclusionsExpected Results and Conclusions

• FASTER is a focused project that builds on combined partners expertise as well as on past research work and projects

• We focus on (and hope to demonstrate): productivity improvement in

implementation and verification of dynamically changing systems

total ownership cost reduction (NIDS and RTM systems)

performance improvement under power constraints for Global Illumination and Image Analysis application

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Challenges & Challenges & OpportunitiesOpportunities

• Tool support for analysis and system definition

• Specification of changing system(s)• Reconfigurable granularity:

influenced by tools and applications• Architectural support for

reconfiguration (vendor?)• Metrics: include design effort/time,

total ownership cost

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