Image Signal Processor (ISP) Deserializer DS90UB933-Q1 Serializer FPD-Link III Bidirectional Control Channel DS90UB934-Q1 or DS90UB964-Q1 Bidirectional Control Bus Bidirectional Control Bus Parallel Data In Parallel Data Out 10 or 12 2 2 HD Image Sensor 10 or 12 GPO GPIO 4 4 2 HSYNC, VSYNC 2 HSYNC, VSYNC Product Folder Sample & Buy Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS90UB933-Q1 SNLS546A – AUGUST 2016 – REVISED DECEMBER 2016 DS90UB933-Q1 FPD-Link III Serializer for 1-MP/60-fps Cameras 10/12 Bits,100 MHz 1 1 Features 1• AEC-Q100 Qualified for Automotive Applications With the Following Results: – Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature • 37.5-MHz to 100-MHz Input Pixel Clock Support • Robust Power-Over-Coaxial (PoC) Operation • Programmable Data Payload: – 10-Bit Payload up to 100 MHz – 12-Bit Payload up to 100 MHz • Continuous Low Latency Bidirectional Control Interface Channel with I2C Support at 400 kHz • Embedded Clock with DC-Balanced Coding to Support AC-Coupled Interconnects • Capable of Driving up to 15-m Coaxial or Shielded Twisted-Pair (STP) Cables • 4 Dedicated General Purpose Input/Output (GPIO) • 1.8-V, 2.8-V or 3.3-V-Compatible Parallel Inputs on Serializer • Single Power Supply at 1.8 V • ISO 10605 and IEC 61000-4-2 ESD Compliant 2 Applications • Automotive – Surround View Systems (SVS) – Front Cameras (FC) – Rear View Cameras (RVC) – Sensor Fusion – Driver Monitor Cameras (DMS) – Remote Satellite RADAR, ToF, and LIDAR Sensors • Security and Surveillance • Machine Vision Applications 3 Description The DS90UB933-Q1 device offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single coaxial cable or differential pair. The DS90UB933-Q1 device incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer/deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This device is ideally suited for driving video data requiring up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical-bidirectional control channel information. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) DS90UB933-Q1 WQFN (32) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic
Transcript
Image Signal Processor
(ISP)
Deserializer
DS90UB933-Q1
Serializer
FPD-Link III
Bidirectional Control Channel
DS90UB934-Q1or
DS90UB964-Q1
Bidirectional Control Bus
Bidirectional Control Bus
Parallel Data In
Parallel Data Out10 or 12
2 2
HD Image Sensor
10 or 12
GPO GPIO
4 4
2
HSYNC,VSYNC
2
HSYNC,VSYNC
Product
Folder
Sample &Buy
Technical
Documents
Tools &
Software
Support &Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UB933-Q1SNLS546A –AUGUST 2016–REVISED DECEMBER 2016
DS90UB933-Q1 FPD-Link III Serializer for 1-MP/60-fps Cameras 10/12 Bits,100 MHz
1
1 Features1• AEC-Q100 Qualified for Automotive Applications
With the Following Results:– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature• 37.5-MHz to 100-MHz Input Pixel Clock Support• Robust Power-Over-Coaxial (PoC) Operation• Programmable Data Payload:
– 10-Bit Payload up to 100 MHz– 12-Bit Payload up to 100 MHz
• Continuous Low Latency Bidirectional ControlInterface Channel with I2C Support at 400 kHz
• Embedded Clock with DC-Balanced Coding toSupport AC-Coupled Interconnects
• Capable of Driving up to 15-m Coaxial or ShieldedTwisted-Pair (STP) Cables
• 4 Dedicated General Purpose Input/Output(GPIO)
• 1.8-V, 2.8-V or 3.3-V-Compatible Parallel Inputson Serializer
• Single Power Supply at 1.8 V• ISO 10605 and IEC 61000-4-2 ESD Compliant
2 Applications• Automotive
– Surround View Systems (SVS)– Front Cameras (FC)– Rear View Cameras (RVC)– Sensor Fusion– Driver Monitor Cameras (DMS)– Remote Satellite RADAR, ToF, and LIDAR
Sensors• Security and Surveillance• Machine Vision Applications
3 DescriptionThe DS90UB933-Q1 device offers an FPD-Link IIIinterface with a high-speed forward channel and abidirectional control channel for data transmissionover a single coaxial cable or differential pair. TheDS90UB933-Q1 device incorporates differentialsignaling on both the high-speed forward channel andbidirectional control channel data paths. Theserializer/deserializer pair is targeted for connectionsbetween imagers and video processors in anelectronic control unit (ECU). This device is ideallysuited for driving video data requiring up to 12-bitpixel depth plus two synchronization signals alongwith bidirectional control channel bus.
Using TI’s embedded clock technology allowstransparent full-duplex communication over a singledifferential pair, carrying asymmetrical-bidirectionalcontrol channel information. This single serial streamsimplifies transferring a wide data bus over PCBtraces and cable by eliminating the skew problemsbetween parallel data and clock paths. Thissignificantly saves system cost by narrowing datapaths that in turn reduce PCB layers, cable width,and connector size and pins. Internal DC-balancedencoding/decoding is used to support AC-coupledinterconnects.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)DS90UB933-Q1 WQFN (32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum atthe end of the data sheet.
9 Power Supply Recommendations ...................... 4210 Layout................................................................... 43
10.1 Layout Guidelines ................................................. 4310.2 Layout Example .................................................... 44
11 Device and Documentation Support ................. 4611.1 Documentation Support ........................................ 4611.2 Receiving Notification of Documentation Updates 4611.3 Community Resources.......................................... 4611.4 Trademarks ........................................................... 4611.5 Electrostatic Discharge Caution............................ 4611.6 Glossary ................................................................ 46
12 Mechanical, Packaging, and OrderableInformation ........................................................... 46
4 Revision History
Changes from Original (August 2016) to Revision A Page
• Changed Product Preview to Production Data release. ......................................................................................................... 1
Parallel data Inputs. For 10-bit MODE, parallel inputs DIN[0:9] are active. DIN[10:11] areinactive and should not be used. Any unused inputs (including DIN[10:11]) must be NoConnect. For 12-bit MODE, parallel inputs DIN[0:11] are active. Any unused inputs must beNo Connect.
HSYNC 1Input,
LVCMOSw/ pulldown
Horizontal SYNC input. Note: HS transition restrictions: 1. 12-bit mode: No HS restrictions(raw) 2. 10-bit mode: HS restricted to no more than one transition per 10 PCLK cycles.Leave open if unused.
VSYNC 2Input,
LVCMOSw/ pulldown
Vertical SYNC input. Note: VS transition restrictions: 1. 12-bit mode: No VS restrictions (raw)2. 10-bit mode: VS restricted to no more than one transition per 10 PCLK cycles. Leave openif unused.
PCLK 3Input,
LVCMOSw/ pulldown
Pixel clock input pin. Strobe edge set by TRFB control register 0x03[0].
General-purpose output pins can be configured as outputs, used to control and respond tovarious commands. GPO[1:0] can be configured to be the outputs for input signals comingfrom GPIO[1:0] pins on the deserializer or can be configured to be outputs of the localregister on the serializer. Leave open if unused.
GPO[2]/CLKOUT 17 Output,
LVCMOS
GPO[2] pin can be configured to be the output for input signal coming from the GPIO[2] pinon the deserializer or can be configured to be the output of the local register on theSerializer. It can also be configured to be the output clock pin when the DS90UB933-Q1device is used in the external oscillator mode. See Device Functional Modes for a detaileddescription of External Oscillator mode. Leave open if unused.
GPO[3]/CLKIN 18 Input/Output,
LVCMOS
GPO[3] can be configured to be the output for input signals coming from the GPIO[3] pin onthe deserializer or can be configured to be the output of the local register setting on theserializer. It can also be configured to be the input clock pin when the DS90UB933-Q1serializer is working with an external oscillator. See Device Functional Modes for a detaileddescription of external oscillator mode. Leave open if unused.
BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE
SCL 4 Input/Output,Open Drain
Clock line for the bidirectional control bus communicationSCL requires an external pullup resistor to V(VDDIO).
SDA 5 Input/Output,Open Drain
Data line for the bidirectional control bus communicationSDA requires an external pullup resistor to V(VDDIO).
MODE 8 Input, analog
Device mode selectResistor (Rmode) to ground and 10-kΩ pullup to 1.8 V rail. MODE pin on the serializer canbe used to select whether the system is running off the PCLK from the imager or an externaloscillator. See details in Table 2.
IDX 6 Input, analogDevice ID Address SelectThe IDX pin on the serializer is used to assign the I2C device address. Resistor (RID) toGround and 10-kΩ pullup to 1.8 V rail. See Table 6.
CONTROL AND CONFIGURATION
PDB 9Input,
LVCMOSw/ pulldown
Power-down mode input pinPDB = H, Serializer is enabled and is ON.PDB = L, Serializer is in power down mode. When the serializer is in power down, the PLL isshut down, and IDD is minimized. Programmed control register data is NOT retained andreset to default values.
RES 7Input,
LVCMOSw/ pulldown
ReservedThis pin MUST be tied LOW.
FPD–Link III INTERFACE
DOUT+ 13 Input/Output,CML
Non-inverting differential output, bidirectional control channel input. The interconnect must beAC coupled with a 0.1-µF capacitor.
DOUT- 12 Input/Output,CML
Inverting differential output, bidirectional control channel input. The interconnect must be ACcoupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect,place a 0.047-µF AC-coupling capacitor in series with a 50-Ω resistor before terminating toGND.
POWER AND GROUND (1)
VDDPLL 10 Power,Analog PLL power, 1.8 V ±5%.
VDDT 11 Power,Analog Tx analog power, 1.8 V ±5%.
VDDCML 14 Power,Analog CML and bidirectional channel driver power, 1.8 V ±5%.
VDDD 28 Power,Digital Digital Power, 1.8 V ±5%.
VDDIO 25 Power,Digital
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V(VDDIO).VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%.
VSS DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at thecenter of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNITSupply voltage – V(VDD_n) (V(VDDPLL), V(VDDT), V(VDDCML), V(VDDD)) –0.3 2.5 VSupply voltage – V(VDDIO) −0.3 4 VLVCMOS input voltage −0.3 V(VDDIO) + 0.3 VFPD-Link III I/O voltage – V(VDD_n) –0.3 V(VDD_n) + 0.3 VJunction temperature 150 °CStorage temperature, Tstg −65 150 °C
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.2 ESD RatingsVALUE UNIT
V(ESD)Electrostaticdischarge
Human body model (HBM), per AEC Q100-002 (1) ±8000VCharged device model (CDM), per AEC
(1) Supply noise testing was done with minimum capacitors (as shown on Figure 36, Figure 32 on the PCB. A sinusoidal signal is ACcoupled to the V(VDD_n) (1.8 V) supply with amplitude = 25 mVp-p measured at the device V(VDD_n) pins. Bit error rate testing of input tothe serializer and output of the deserializer with 10-meter cable shows no error when the noise frequency on the serializer is less than 1MHz. The deserializer, on the other hand, shows no error when the noise frequency is less than 750 kHz.
6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNITSupply voltage, V(VDD_n) 1.71 1.8 1.89 VLVCMOS supply voltage (V(VDDIO)= 1.8 V) OR 1.71 1.8 1.89
VLVCMOS supply voltage (V(VDDIO)= 3.3 V) OR 3 3.3 3.6LVCMOS supply voltage (V(VDDIO)= 2.8 V) 2.52 2.8 3.08
Supply noise (1)
V(VDD_n) = 1.8 V 25mVp-pV(VDDIO) = 1.8 V 25
V(VDDIO) = 3.3 V 50
Power-Over-Coax SupplyNoise
ƒ = 30 Hz - 1 KHz, trise > 100 µsMeasured differentially between DOUT+ and DOUT–(coax mode only)
35 mVp-p
ƒ = 1 KHz - 50 MHzMeasured differentially between DOUT+ and DOUT-(coax mode only)
35 mVp-p
Operating free air temperature, TA –40 25 105 °CPCLK clock frequency - 10-bit mode 50 100 MHzPCLK clock frequency - 12-bit mode 37.5 100 MHz
(1) The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwisemodified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are notverified.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to groundexcept VOD and ΔVOD which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operating Conditions atthe time of product characterization and are not verified.
6.5 Electrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITLVCMOS DC SPECIFICATIONS 3.3 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)VIH High level input voltage VIN = 3 V to 3.6 V 2 VIN VVIL Low level input voltage VIN = 3 V to 3.6 V GND 0.8 VIIN Input current VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V –20 ±1 20 µAVOH High level output voltage V(VDDIO) = 3 V to 3.6 V, IOH = −4 mA 2.4 V(VDDIO) VVOL Low level output voltage V(VDDIO) = 3 V to 3.6 V, IOL = 4 mA GND 0.4 V
IOS Output short-circuit current VOUT = 0 V SerializerGPO outputs –15 mA
IOZ Tri-state output current PDB = 0 V,VOUT = 0 V or V(VDDIO)
SerializerGPO outputs –20 20 µA
CGPO Pin capacitance GPO [3:0] 1.5 pFLVCMOS DC SPECIFICATIONS 1.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)VIH High level input voltage VIN = 1.71 V to 1.89 V 0.65 VIN VIN VVIL Low level input voltage VIN = 1.71 V to 1.89 V GND 0.35 VIN
IIN Input current VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V –20 ±1 20 µA
VOH High level output voltage V(VDDIO) = 1.71 V to 1.89 V, IOH = −4 mA V(VDDIO) –0.45 V(VDDIO) V
VOL Low level output voltage V(VDDIO) = 1.71 V to 1.89 V IOL = 4 mA GND 0.45 V
IOS Output short-circuit current VOUT = 0 V SerializerGPO outputs –11 mA
IOZ Tri-state output current PDB = 0 V,VOUT = 0 V or V(VDDIO)
Electrical Characteristics (continued)Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(4) The back channel frequency (MHz) listed is the frequency of the internal clock used to generate the encoded back channel data stream.The data rate (Mbps) of the encoded back channel stream is the back channel frequency divided by 2.
LVCMOS DC SPECIFICATIONS 2.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)VIH High level input voltage VIN = 2.52 V to 3.08 V 0.7 VIN VIN VVIL Low level input voltage VIN = 2.52 V to 3.08 V GND 0.3 VIN
IIN Input current VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V –20 ±1 20 µA
VOH High level output voltage V(VDDIO) = 2.52 V to 3.08 V, IOH = −4 mA V(VDDIO) -0.4 V(VDDIO) V
VOL Low level output voltage V(VDDIO) =2.52 V to 3.08V IOL = 4 mA GND 0.4 V
IOS Output short-circuit current VOUT = 0 V SerializerGPO outputs –11 mA
IOZ Tri-state output current PDB = 0 V,VOUT = 0 V or V(VDDIO)
(1) Recommended input timing requirements are input specifications and not tested in production.(2) T is the period of the PCLK.(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at Recommended Operating Conditions at the
time of product characterization and are not verified.(4) ƒPCLK denotes input PCLK frequency to the device.(5) ƒOSC denotes input external oscillator frequency to the device (GPO3/CLKIN).
6.6 Recommended Serializer Timing For PCLKOver recommended operating supply and temperature ranges unless otherwise specified. (1) (2)
PARAMETER TEST CONDITIONS PIN / FREQ MIN NOM MAX UNIT
tf SCL and SDA fall timeStandard mode 300 nsFast mode 300 ns
(1) Specification is verified by design.(2) FPD-Link device was designed primarily for point-to-point operation and a small number of attached slave devices. As such the
minimum IOL pullup current is targeted to lower value than the minimum IOL in the I2C specification.
6.8 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-CompatibleOver recommended supply and temperature ranges unless otherwise specified (1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNITRECOMMENDED INPUT TIMING REQUIREMENTSVIH Input high level SDA and SCL 0.7 × V(VDDIO) V(VDDIO) V
(1) tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.(2) Specification is verified by design.(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at Recommended Operating Conditions at the
time of product characterization and are not verified.(4) Specification is verified by characterization and is not tested in production.(5) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(6) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at Recommended Operating Conditions at thetime of product characterization and are not verified.
(7) Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input.
6.9 Serializer Switching CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specified.
7.1 OverviewThe DS90UB933-Q1 is optimized to interface with the DS90UB934-Q1 or DS90UB964-Q1 using a 50-Ω coaxinterface. The DS90UB933-Q1 also works with the DS90UB934-Q1 or DS90UB964-Q1 using an STP interface.
The DS90UB933/934 FPD-Link III chipsets are intended to link mega-pixel camera imagers and videoprocessors in ECUs. The Serializer/Deserializer chipset can operate from 37.5 MHz to 100 MHz pixel clockfrequency. The DS90UB933-Q1 device transforms a 10/12-bit wide parallel LVCMOS data bus along with abidirectional control channel control bus into a single high-speed differential pair. The high-speed serial bitstream contains an embedded clock and DC-balanced information which enhances signal quality to support ACcoupling. The DS90UB934-Q1 device receives the single serial data stream and converts it back into a 10/12-bitwide parallel data bus together with the control channel data bus. The DS90UB933/934 chipsets can accept upto:• 12-bits of DATA + 2 SYNC bits for an input PCLK range of 37.5 MHz to 100 MHz in the 12-bit mode. Note:
No HS/VS restrictions (raw).• 10-bits of DATA + 2 SYNC bits for an input PCLK range of 50 MHz to 100 MHz in the 10-bit mode. Note:
HS/VS restricted to no more than one transition per 10 PCLK cycles.
The DS90UB933/934 chipset offer customers the choice to work with different clocking schemes. TheDS90UB933/934 chipsets can use an external oscillator as the reference clock source for the PLL (seeDS90UB933/934 Operation With External Oscillator as Reference Clock) or PCLK from the imager as primaryreference clock to the PLL (see DS90UB933/934 Operation With Pixel Clock From Imager as Reference Clock).
7.3.1 Serial Frame FormatThe high-speed forward channel is composed of 28 bits of data containing video data, sync signals, I2C, andparity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,balanced and scrambled. The 28-bit frame structure changes in the 12-bit mode and 10-bit mode internally and isseamless to the customer. The bidirectional control channel data is transferred over the single serial link alongwith the high-speed forward data. This architecture provides a full-duplex low-speed forward and backward pathacross the serial link together with a high-speed forward channel without the dependence on the video blankingphase.
7.3.2 Line Rate Calculations for the DS90UB933/934The DS90UB933-Q1 device divides the clock internally by divide-by-2 in the 10-bit mode and by divide-by-1.5 inthe 12-bit mode. Conversely, the DS90UB934-Q1 multiplies the recovered serial clock to generate the properpixel clock output frequency. The following are the formulae used to calculate the maximum line rate in thedifferent modes:• For the 12-bit mode, Line rate = ƒPCLK × (2/3) × 28; for example, ƒPCLK = 100 MHz, line rate = (100 MHz) ×
(2/3) × 28 = 1.87 Gbps• For the 10-bit mode, Line rate = ƒPCLK/2 × 28; for example, ƒPCLK = 100 MHz, line rate = (100 MHz/2) × 28 =
1.40 Gbps
7.3.3 Error DetectionThe chipset provides error detection operations for validating data integrity in long distance transmission andreception. The data error detection function offers users flexibility and usability of performing bit-by-bit datatransmission error checking. The error detection operating modes support data validation of the following signals:• Bidirectional control channel data across the serial link• Parallel video/sync data across the serial link
The chipset provides 1 parity bit on the forward channel and 4 cyclic redundancy check (CRC) bits on the backchannel for error detection purposes. The DS90UB933/934 chipset checks the forward and back channel seriallinks for errors and stores the number of detected errors in two 8-bit registers in the serializer and thedeserializer, respectively.
To check parity errors on the forward channel, monitor registers 0x55 and 0x56 on the DS90UB934. The parityerror counter registers return the number of data parity errors that have been detected on the FPD3 receiver datasince the last detection of valid lock or last read of these registers (0x55 and 0x56). These registers are clearedon read.
To check CRC errors on the back channel, monitor registers 0x0A and 0x0B on the serializer.
Feature Description (continued)7.3.4 Synchronizing Multiple CamerasFor applications requiring multiple cameras for frame-synchronization, TI recommends using the general purposeinput/output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To synchronize thecameras properly, the system controller must provide a field sync output (such as a vertical or frame syncsignal), and the cameras must be set to accept an auxiliary sync input. The vertical synchronize signalcorresponds to the start and end of a frame and the start and end of a field. Note this form of synchronizationtiming relationship has a non-deterministic latency. After the control data is reconstructed from the bidirectionalcontrol channel, there is a time variation of the GPIO signals arriving at the different target devices (between theparallel links). The maximum latency (t1) of the GPIO data transmitted across the link is 32 µs.
NOTEThe user must verify that the timing variations between the different links are within theirsystem and timing specifications.
See Figure 13 for an example of this function.
The maximum time (t2) between the time the GPIO signal arrives at Camera A and Camera B is 23 µs.
Feature Description (continued)7.3.5 General Purpose I/O (GPIO) DescriptionsThere are 4 GPOs on the serializer and 4 GPIOs on the deserializer when the DS90UB933/934 chipsets are runoff the pixel clock from the imager as the reference clock source. The GPOs on the serializer can be configuredas outputs for the input signals that are fed into the deserializer GPIOs. In addition, the GPOs on the serializercan behave as outputs of the local register on the serializer. The GPIOs on the deserializer can be configured tobe the input signals feeding the GPOs (configured as outputs) on the serializer. In addition the GPIOs on thedeserializer can be configured to behave as outputs of the local register on the deserializer. The DS90UB933-Q1serializer GPOs cannot be configured as inputs for remote communication with deserializer. If theDS90UB933/934 chipsets are run off the external oscillator source as the reference clock, then GPO3 on theserializer is automatically configured to be the input for the external clock and GPO2 is configured to be theoutput of the divide-by-2 clock which is fed into the imager as its reference clock. In this case, the GPIO2 andGPIO3 on the deserializer can only behave as outputs of the local register on the deserializer. The GPIOmaximum switching rate is up to 66 kHz when configured for communication between deserializer GPIO toserializer GPO.
7.3.6 LVCMOS V(VDDIO) Option1.8 V/2.8 V/3.3 V Serializer inputs are user configurable to provide compatibility with 1.8 V, 2.8 V, and 3.3 Vsystem interfaces.
7.3.7 Pixel Clock Edge Select (TRFB / RRFB)The TRFB/RRFB selects which edge of the pixel clock is used. For the SER, this register determines the edgethat the data is latched on. If TRFB register is 1, data is latched on the rising edge of the PCLK. If TRFB registeris 0, data is latched on the falling edge of the PCLK. For the DES, this register determines the edge that the datais strobed on. If RRFB register is 1, data is strobed on the rising edge of the PCLK. If RRFB register is 0, data isstrobed on the falling edge of the PCLK.
Figure 15. Programmable PCLK Strobe Select
7.3.8 Power DownThe SER has a PDB input pin to ENABLE or power down the device. Enabling PDB on the SER disables the linkto save power. If PDB = HIGH, the SER operates at its internal default oscillator frequency when the input PCLKstops. When the PCLK starts again, the SER locks to the valid input PCLK and transmit the data to the DES.When PDB = LOW, the high-speed driver outputs are static HIGH. See Power-Up Requirements and PDB Pin forpower-up requirements.
7.4.1 DS90UB933/934 Operation With External Oscillator as Reference ClockIn some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance ofthe DS90UB933/934/964 chipsets. In this case, operate the DS90UB933-Q1 device by using an external clocksource as the reference clock for the DS90UB933/934/964 chipsets. This is the recommended operating mode.The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB933-Q1 serializer, and thisdivided clock output is used as the reference clock for the imager. The output data and pixel clock from theimager are then fed into the DS90UB933-Q1 device. Figure 16 shows the operation of the DS90UB33/934chipsets while using an external automotive grade oscillator.
Figure 16. DS90UB933-Q1/934-Q1 Operation in the External Oscillator Mode
When the DS90UB933-Q1 device is operated using an external oscillator, the GPO3 pin on the DS90UB933-Q1is the input pin for the external oscillator. In applications where the DS90UB933-Q1 device is operated from anexternal oscillator, the divide-by-2 circuit in the DS90UB933-Q1 device feeds back the divided clock output to theimager device through GPO2 pin. The pixel clock to external oscillator ratios must be fixed for the 12–bit modeand the 10–bit mode. In the 10-bit mode, the pixel clock frequency divided by the external oscillator frequencymust be 2. In the 12-bit mode, the pixel clock frequency divided by the external oscillator frequency must be 1.5.For example, if the external oscillator frequency is 48 MHz in the 10-bit mode, the pixel clock frequency of theimager must be twice of the external oscillator frequency, that is, 96 MHz. If the external oscillator frequency is48 MHz in the 12-bit mode, the pixel clock frequency of the imager must be 1.5 times of the external oscillatorfrequency, that is, 72 MHz.
When PCLK signal edge is detected, and 0x03[1] = 0, the DS90UB933-Q1 switches from internal oscillator modeto an external PCLK. Upon removal of PCLK input, the device switches back into internal oscillator mode. Inexternal oscillator mode, GPO2 and GPO3 on the serializer cannot act as the output of the input signal comingfrom GPIO2 or GPIO3 on the deserializer.
Table 1. Device Functional Mode With Example XCLKIN = 48 MHz
MODE GPIO3 XCLKIN GPIO2 XCLKOUT =XCLKIN / 2 RATIO INPUT PCLK FREQUENCY =
7.4.2 DS90UB933/934 Operation With Pixel Clock From Imager as Reference ClockThe DS90UB933/934/964 chipsets can be operated by using the pixel clock from the imager as the referenceclock. Figure 17 shows the operation of the DS90UB933/934/964 chipsets using the pixel clock from the imager.If the DS90UB933-Q1 device is operated using the pixel clock from the imager as the reference clock, then theimager uses an external oscillator as its reference clock. There are 4 GPIOs available in this mode (PCLK fromimager mode).
Figure 17. DS90UB933-Q1/934-Q1 Operation in PCLK mode
7.4.3 MODE Pin on SerializerThe MODE pin on the serializer can be configured to select if the DS90UB933-Q1 device is to be operated fromthe external oscillator or the PCLK from the imager. The pin must be pulled to V(VDD_n)(1.8 V, not V(VDDIO)) with aresistor R1 and a pulldown resistor R2 to create the ratio shown in Figure 18. Suggested resistor values are givenin Table 2. The recommended maximum resistor tolerance is 1%. Other resistor values can be used as long asthe ratio is met under all conditions.
7.4.4 Internal OscillatorWhen a PCLK is not applied to the DS90UB933-Q1, the serializer establishes the FPD-III link using an internaloscillator. During normal operation (not BIST) the frequency of the internal oscillator can be adjusted fromDS90UB933-Q1 register 0x14[2:1] according to Table 3. In BIST mode, the internal oscillator frequency shouldonly be adjusted from the DS90UB934-Q1. The BIST frequency can be set by either pin strapping (Table 4) orregister (Table 5). In BIST DS90UB933-Q1 register 0x14[2:1] is automatically loaded from the DS90UB934-Q1through the bi-directional control channel.
Table 3. Clock Sources for Forward Channel Frame on the Serializer During Normal OperationDS90UB933-Q1Reg 0x14 [2:1]
7.4.5 Built-In Self TestAn optional at-speed built-in self test (BIST) feature supports the testing of the high-speed serial link and low-speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also forsystem diagnostics.
7.4.6 BIST Configuration and StatusThe chipset can be programmed into BIST mode using either pins or registers on the DES only. By default, BISTconfiguration is controlled through pins. BIST can be configured via registers using BIST Control register (0xB3).Pin-based configuration is defined as follows:• BISTEN = HIGH: Enable the BIST mode, BISTEN = LOW: Disable the BIST mode.• Deserializer GPIO0 and GPIO1: Defines the BIST clock source (PCLK vs various frequencies of internal
OSC)
Table 4. BIST Pin ConfigurationDESERIALIZER GPIO[0:1] OSCILLATOR SOURCE BIST FREQUENCY
BIST mode provides various options for the PCLK source. Either external pins (GPIO0 and GPIO1) or registerscan be used to program the BIST to use external PCLK or various OSC frequencies. Refer to Table 4 for pinsettings. The BIST status can be monitored real-time on the PASS pin. For every frame with error(s), the PASSpin toggles low for one-half PCLK period. If two consecutive frames have errors, PASS toggles twice to allowcounting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BISTrun only for one PCLK cycle. The status can also be read through I2C for the number of frames in errors. BISTstatus register retains results until it is reset by a new BIST session or a device reset. To evaluate BIST inexternal oscillator mode, both the external oscillator and PCLK must be present. For all practical purposes, theBIST status can be monitored from the BIST Error Count register 0x57 on the DS90UB934 deserializer.
7.4.7 Sample BIST Sequence• Step 1: For the DS90UB933/934 FPD-Link III chipset, BIST mode is enabled via the BISTEN pin of
DS90UB934-Q1 FPD-Link III deserializer. The desired clock source is selected through the deserializerGPIO0 and GPIO1 pins as shown in Table 4.
• Step 2: The DS90UB933-Q1 serializer BIST pattern is enabled through the back channel. The BIST pattern issent through the FPD-Link III to the deserializer. Once the serializer and deserializer are in the BIST modeand the deserializer acquires lock, the PASS pin of the deserializer goes high, and BIST starts checking theFPD-Link III serial stream. If an error in the payload is detected, the PASS pin switches low for one half of theclock period. During the BIST test, the PASS output can be monitored and counted to determine the payloaderror rate.
• Step 3: To stop the BIST mode, the deserializer BISTEN pin is set LOW. The deserializer stops checking thedata. The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BISTError Count register, 0x57 on the deserializer.
• Step 4: The link returns to normal operation after the deserializer BISTEN pin is low. Figure 20 shows thewaveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one withmultiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differentialdata transmission, etc.); thus, they may be introduced by greatly extending the cable length, faulting theinterconnect, or by reducing signal condition enhancements (Rx equalization).
7.5.1 Programmable ControllerAn integrated I2C slave controller is embedded in the DS90UB933-Q1 serializer. It must be used to configure theextra features embedded within the programmable registers or it can be used to control the set of programmableGPIOs.
7.5.2 Description of Bidirectional Control Bus and I2C ModesThe I2C-compatible interface allows programming of the DS90UB933-Q1, DS90UB934-Q1, DS90UB964-Q1, oran external remote device (such as image sensor) through the bidirectional control channel. Registerprogramming transactions to/from the DS90UB933/934/964 chipset are employed through the clock (SCL) anddata (SDA) lines. These two signals have open drain I/Os, and both lines must be pulled up to V(VDDIO) by anexternal resistor. Pullup resistors or current sources are required on the SCL and SDA busses to pull them highwhen they are not being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH istransmitted by releasing the output and allowing it to be pulled up externally. The appropriate pullup resistorvalues depend upon the total bus capacitance and operating speed. The DS90UB933-Q1 I2C bus data ratesupports up to 400 kbps according to I2C fast mode specifications.
For further description of general I2C communication, refer to the Understanding the I2C Bus application note .For more information on choosing appropriate pullup resistor values, see the I2C Bus Pullup Resistor Calculationapplication note .
7.5.3 I2C Pass-ThroughI2C pass-through provides a way to access remote devices at the other end of the FPD-Link III interface. Thisoption is used to determine if an I2C instruction is transferred over to the remote I2C bus. For example, when theI2C master is connected to the deserializer and I2C pass-through is enabled on the deserializer, any I2C traffictargeted for the remote serializer or remote slave is allowed to pass through the deserializer to reach thoserespective devices.
If the master controller transmits an I2C transaction for address 0xA0, the DES A with I2C pass-through enabledtransfers I2C commands to remote Camera A. The DES B (with I2C pass-through disabled) will NOT pass I2Ccommands on the I2C bus to Camera B.
Figure 25. I2C Pass-Through
7.5.4 Slave Clock StretchingThe I2C-compatible interface allows programming of the DS90UB933-Q1, DS90UB934-Q1, DS90UB964-Q1, oran external remote device (such as image sensor) through the bidirectional control. To communicate andsynchronize with remote devices on the I2C bus through the bidirectional control channel/MCU, the chipsetutilizes bus clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls theSCL line low on the 9th clock of every I2C transfer (before the ACK signal). The slave device does not controlthe clock and only stretches it until the remote peripheral has responded. The I2C master must support clockstretching to operate with the DS90UB933/934/964 chipset.
Programming (continued)7.5.5 IDX Address Decoder on the SerializerThe IDX pin on the serializer is used to decode and set the physical slave address of the serializer (I2C only) toallow up to five devices on the bus connected to the serializer using only a single pin. The pin sets one of the 4possible addresses for each serializer device. The pin must be pulled to V(VDD_n) (1.8 V, not V(VDDIO)) with aresistor, R3, and a pulldown resistor R4. Suggested resistor values are given in Table 6. The recommendedmaximum resistor tolerance is 1%. Other resistor values can be used as long as the ratio is met under allconditions.
7.5.6 Multiple Device AddressingSome applications require multiple camera devices with the same fixed address to be accessed on the same I2Cbus. The DS90UB933-Q1 provides slave ID matching/aliasing to generate different target slave addresses whenconnecting more than two identical devices together on the same bus. This allows the slave devices to beindependently addressed. Each device connected to the bus is addressable through a unique ID by programmingof the slave alias register on deserializer. This remaps the slave alias address to the target SLAVE_ID address;up to 8 ID aliases are supported in sensor mode when slaves are attached to the DS90UB933-Q1 serializer. Indisplay mode, when the external slaves are at the deserializer the DS90UB933-Q1 supports one ID alias. TheECU controller must keep track of the list of I2C peripherals in order to properly address the target device.
See Figure 27 for an example of this function.• ECU is the I2C master and has an I2C master interface.• The I2C interfaces in DES A and DES B are both slave interfaces.• The I2C protocol is bridged from DES A to SER A and from DES B to SER B.• The I2C interfaces in SER A and SER B are both master interfaces.
If master controller transmits I2C slave 0xA0, DES A (address 0xC0), with pass-through enabled, forwards thetransaction to remote Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 recognizes that0xA4 is mapped to 0xA0 and is transmitted to the remote Camera B. If controller sends command to address0xA6, the DES B (address 0xC2), with pass-through enabled, forwards the transaction to slave device 0xA2.
Clear CRC error countersThis bit is NOT self-clearing.1: Clear counters0: Normal operation
4I2C Remote WriteAutoAcknowledge
RW 0
Automatically acknowledge I2C remote writeThe mode works when the system is LOCKed.1: Enable: When enabled, I2C writes to thedeserializer (or any remote I2C Slave, if I2C PASSALL is enabled) are immediately acknowledgedwithout waiting for the deserializer to acknowledge thewrite. The accesses are then remapped to addressspecified in 0x06.0: Disable
3 I2C Pass-Through All RW 0
1: Enable Forward Control Channel pass-through of allI2C accesses to I2C IDs that do not match theserializer I2C ID. The I2C accesses are thenremapped to address specified in register 0x06.0: Enable Forward Control Channel pass-through onlyof I2C accesses to I2C IDs matching either the remotedeserializer ID or the remote I2C IDs.
2 I2C Pass-Through RW 1
I2C Pass-through mode1: Pass-through enabled. DES alias 0x07 and slavealias 0x090: Pass-through disabled
0x03 GeneralConfiguration
1 OV_CLK2PLL RW 0
1:Enabled : When enabled this register overrides theclock to PLL mode (External Oscillator mode or DirectPCLK mode) defined through MODE pin and allowsselection through register 0x35 in the serializer.0: Disabled : When disabled, Clock to PLL mode(External Oscillator mode or Direct PCLK mode) isdefined through MODE pin on the Serializer.
0 TRFB RW 1
Pixel clock edge select1: Parallel interface data is strobed on the rising clockedge0: Parallel interface data is strobed on the falling clockedge
0x04 Reserved
0x05 Mode Select
7 RSVD Reserved6 RSVD Reserved
5 MODE_OVERRIDE RW 0
Allows overriding mode select bits coming from back-channel.1: Overrides MODE select bits0: Does not override MODE select bits
4 MODE_UP_TO_DATE R 0
1: Status of mode select from deserializer is up-to-date.0: Status is NOT up-to-date.
3 Pin_MODE_12–bit mode R 0 1: 12-bit mode is selected.
0: 12-bit mode is not selected.
2 Pin_MODE_10–bit mode R 0 1: 10-bit mode is selected.
Register Maps (continued)Table 7. DS90UB933-Q1 Control Registers (continued)
Addr(Hex) Name Bits Field TYPE Default Description
0x06 DES ID
7:1 DeserializerDevice ID RW 0x00
7-bit deserializer Device ID Configures the I2C SlaveID of the remote deserializer. A value of 0 in this fielddisables I2C access to the remote deserializer. Thisfield is automatically configured by the bidirectionalcontrol channel once RX Lock has been detected.Software may overwrite this value, but should alsoassert the FREEZE DEVICE ID bit to preventoverwriting by the bidirectional control channel.
0 Freeze Device ID RW 0
1: Prevents auto-loading of the deserializer Device IDby the bidirectional control channel. The ID is frozen atthe value written.0: Update
0x07 DES Alias7:1 Deserializer
ALIAS ID RW 0x00
7-bit remote deserializer device alias ID Configures thedecoder for detecting transactions designated for anI2C deserializer device. The transaction is remappedto the address specified in the DES ID register.A value of 0 in this field disables access to the remotedeserializer.
0 RSVD Reserved
0x08 SlaveID7:1 SLAVE ID RW 0x00
7-bit remote slave device ID Configures the physicalI2C address of the remote I2C slave device attachedto the remote deserializer. If an I2C transaction isaddressed to the slave alias ID, the transaction isremapped to this address before passing thetransaction across the bidirectional control channel tothe deserializer and then to remote slave. A value of 0in this field disables access to the remote I2C slave.
0 RSVD Reserved
0x09 Slave Alias7:1 SLAVE ALIAS ID RW 0x00
7-bit remote slave device alias ID Configures thedecoder for detecting transactions designated for anI2C slave device attached to the remote deserializer.The transaction is remapped to the address specifiedin the slave ID register. A value of 0 in this fielddisables access to the remote I2C slave.
0 RSVD Reserved
0x0A CRC Errors 7:0 CRC Error Byte 0 R 0x00 Number of back-channel CRC errors during normaloperation. Least significant byte.
0x0B CRC Errors 7:0 CRC Error Byte 1 R 0x00 Number of back-channel CRC errors during normaloperation. Most significant byte
0x0C General Status
7:5 Rev-ID R 0x0 Revision ID0x0: Production Revision ID
4 RX Lock Detect R 0 1: RX LOCKED0: RX not LOCKED
3 BIST CRCError Status R 0 1: CRC errors in BIST mode
0: No CRC errors in BIST mode
2 PCLK Detect R 0 1: Valid PCLK detected0: Valid PCLK not detected
1 DES Error R 0
1: CRC error is detected during communication withdeserializer.This bit is cleared upon loss of link or assertion ofCRC ERROR RESET in register 0x03[5].0: No effect
0 LINK Detect R 0
1: Cable link detected0: Cable link not detectedThis includes any of the following faults:— Cable open— '+' and '-' shorted— Short to GND— Short to battery
Register Maps (continued)Table 7. DS90UB933-Q1 Control Registers (continued)
Addr(Hex) Name Bits Field TYPE Default Description
0x0DGPO[0]
and GPO[1]Configuration
7 GPO1 OutputValue RW 0
Local GPIO output value. This value is output on theGPIO pin when the GPIO function is enabled. Thelocal GPIO direction is output, and remote GPIOcontrol is disabled.
6 GPO1 RemoteEnable RW 1
Remote GPIO Control1: Enable GPIO control from remote deserializer. TheGPIO pin must be an output, and the value is receivedfrom the remote Deserializer.0: Disable GPIO control from remote deserializer
5 RSVD Reserved
4 GPO1 Enable RW 1 1: GPIO enable0: Tri-state
3 GPO0 OutputValue RW 0
Local GPIO output value. This value is output on theGPIO pin when the GPIO function is enabled. Thelocal GPIO direction is output, and remote GPIOcontrol is disabled.
2 GPO0 RemoteEnable RW 1
Remote GPIO Control1: Enable GPIO control from remote deserializer. TheGPIO pin must be an output, and the value is receivedfrom the remote Deserializer.0: Disable GPIO control from remote deserializer.
1 RSVD Reserved
0 GPO0 Enable RW 1 1: GPIO enable0: Tri-state
0x0EGPO[2]
and GPO[3]Configuration
7 GPO3 OutputValue RW 0
Local GPIO output value. This value is output on theGPIO pin when the GPIO function is enabled. Thelocal GPIO direction is output, and remote GPIOcontrol is disabled.
6 GPO3 RemoteEnable RW 0
Remote GPIO vontrol1: Enable GPIO control from remote Deserializer. TheGPIO pin must be an output, and the value is receivedfrom the remote deserializer.0: Disable GPIO control from remote Deserializer.
5 GPO3 Direction RW 1 1: Input0: Output
4 GPO3 Enable RW 1 1: GPIO enable0: Tri-state
3 GPO2 OutputValue RW 0
Local GPIO output value. This value is output on theGPIO pin when the GPIO function is enabled. Thelocal GPIO direction is output, and remote GPIOcontrol is disabled.
2 GPO2 RemoteEnable RW 1
Remote GPIO Control1: Enable GPIO control from remote deserializer. TheGPIO pin must be an output, and the value is receivedfrom the remote deserializer.0: Disable GPIO control from remote deserializer.
Register Maps (continued)Table 7. DS90UB933-Q1 Control Registers (continued)
Addr(Hex) Name Bits Field TYPE Default Description
0x0F I2C MasterConfig
7:5 RSVD Reserved
4:3 SDA OutputDelay RW 00
SDA output delay This field configures output delay onthe SDA output. Setting this value increases outputdelay in units of 50 ns. Nominal output delay valuesfor SCL to SDA are:00: ~350 ns01: ~400 ns10: ~450 ns11: ~500 ns
2 Local WriteDisable RW 0
Disable remote writes to local registers setting this bitto a 1 prevents remote writes to local device registersfrom across the control channel. This prevents writesto the serializer registers from an I2C master attachedto the deserializer. setting this bit does not affectremote access to I2C slaves at the serializer.
1 I2C Bus TimerSpeed up RW 0
Speed up I2C bus watchdog timer1: Watchdog timer expires after approximately 50microseconds.0: Watchdog timer expires after approximately 1second.
0 I2C Bus TimerDisable RW 0
1. Disable I2C bus watchdog timer when the I2Cwatchdog timer may be used to detect when the I2Cbus is free or hung up following an invalid terminationof a transaction. If SDA is high and no signalingoccurs for approximately 1 second, the I2C bus isassumed to be free. If SDA is low and no signalingoccurs, the device attempts to clear the bus by driving9 clocks on SCL.0: No effect
0x10 I2C Control
7 RSVD Reserved
6:4 SDA Hold Time RW 0x1Internal SDA hold time. This field configures theamount of internal hold time provided for the SDAinput relative to the SCL input. Units are 50 ns.
3:0 I2C Filter Depth RW 0x7I2C glitch filter depth. This field configures themaximum width of glitch pulses on the SCL and SDAinputs that will be rejected. Units are 10 ns.
0x11 SCL High Time 7:0 SCL High Time RW 0x82
I2C master SCL high time This field configures thehigh pulse width of the SCL output when the serializeris the master on the local I2C bus. Units are 50 ns forthe nominal oscillator clock frequency. The defaultvalue is set to provide a minimum (4 µs + 1 µs of risetime for cases where rise time is very fast) SCL hightime with the internal oscillator clock running at 26MHz rather than the nominal 20 MHz.
0x12 SCL LOW Time 7:0 SCL Low Time RW 0x82
I2C SCL low time This field configures the low pulsewidth of the SCL output when the serializer is themaster on the local I2C bus. This value is also used asthe SDA setup time by the I2C slave for providing dataprior to releasing SCL during accesses over thebidirectional control channel. Units are 50 ns for thenominal oscillator clock frequency. The default value isset to provide a minimum (4.7 µs + 0.3 µs of fall timefor cases where fall time is very fast) SCL low timewith the internal oscillator clock running at 26 MHzrather than the nominal 20 MHz.
0x13 General PurposeControl 7:0 GPCR[7:0] RW 0x00 1: High
Register Maps (continued)Table 7. DS90UB933-Q1 Control Registers (continued)
Addr(Hex) Name Bits Field TYPE Default Description
0x14 BIST Control
7:3 RSVD Reserved
2:1 Clock Source RW 0x0
Allows choosing different OSC clock frequencies forforward channel frame.OSC clock frequency in functional mode when OSCmode is selected or when the selected clock source isnot present, for example, missing PCLK/ externaloscillator. See Table 3 for oscillator clock frequencieswhen PCLK/ external clock is missing.
0 RSVD Reserved0x15 -0x1D Reserved
0x1E BCC WatchdogControl
7:1 BCC WatchdogTimer RW 0x7F
The watchdog timer allows termination of a controlchannel transaction if it fails to complete within aprogrammed amount of time. This field sets thebidirectional control channel watchdog timeout value inunits of 2 ms. This field should not be set to 0.
0x29 OSC Divider 7:6 RSVD RW 0x0 Reserved5 OSC Divider RW 0 Selects the OSC frequency to drive out on GPO2 in
external oscillator mode.0: Divide by 2 (default)1: Divide by 4
4:0 RSVD RW 0x06 Reserved
0x2A CRC Errors 7:0 BIST Mode CRCErrors Count R 0x00 Number of CRC errors in the back channel when in
BIST mode0x2B -0x2C Reserved
0x2D Inject ForwardChannel Error
7 Force ForwardChannel Error RW 0
1: Forces 1 (one) error over forward channel frame innormal operating mode. Self-clearing bit.0: No error
6:0 Force BIST Error RW 0x00
N: Forces N number of errors in BIST mode. Thisregister MUST be set BEFORE BIST mode is enabled.BIST error count register on the deserializer must beread AFTER BIST mode is disabled for the correctnumber of errors incurred while in BIST mode.0: No error
0x2E -0x34 Reserved
0x35 PLL ClockOverwrite
7:4 RSVD Reserved
3PIN_LOCK toExternalOscillator
RW 0
Status of mode select pin1: Indicates external oscillator mode is selected bymode-resistor0: External oscillator mode is not selected by mode-resistor
2 RSVD Reserved
1 LOCK to ExternalOscillator RW 0
Affects only when 0x03[1] =1 (OV_CLK2PLL) and0x35[0] = 01: Routes GPO3 directly to PLL0: Allows PLL to lock to PCLK
0 LOCK2OSC
RW 1 Affects only when 0x03[1] = 1 (OV_CLK2PLL)1: Allows internal OSC clock to feed into PLL0: Allows PLL to lock to either PCLK or external clockfrom GPO3
NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.
8.1 Application InformationThe DS90UB933-Q1 was designed as a serializer to support automotive camera designs. Automotive camerasare often located in remote positions such as bumpers or trunk lids, and a major component of the system cost isthe wiring. For this reason it is desirable to minimize the wiring to the camera. This chipset allows the video data,along with a bidirectional control channel, and power to all be sent over a single coaxial cable. The chipset isalso able to transmit over STP and is pin-to-pin/backwards compatible with the DS90UB913A-Q1 andDS90UB913Q-Q1.
8.1.1 Power Over CoaxSee application report Sending Power Over Coax in DS90UB933 Designs for more details.
8.1.2 Power-Up Requirements and PDB PinThe PDB pin on the device must be ramped after the V(VDDIO) and V(VDD_n) supplies have reached their requiredoperating voltage levels. TI recommends asserting PDB = HIGH with an RC filter network to help ensure propersequencing of the PDB pin after settling of the power supplies. Refer to Power Down for device operation whenpowered down.
Common applications tie the V(VDDIO) and V(VDD_n) supplies to the same power source of 1.8 V typically. This is anacceptable method for ramping the V(VDDIO) and V(VDD_n) supplies. The main constraint here is that the V(VDD_n)supply does not lead in ramping before the V(VDDIO) system supply. This is noted in Figure 28 with therequirement of t1 ≥ 0. V(VDDIO) must reach the expected operating voltage earlier than V(VDD_n) or at the sametime.
8.1.3 AC CouplingThe SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in Figure 29.For applications utilizing single-ended 50-Ω coaxial cable, the unused data pin (DOUT–, RIN–) must utilize a0.047-µF capacitor and must be terminated with a 50-Ω resistor. For high-speed FPD–Link III transmissions, thesmallest available package should be used for the AC-coupling capacitor. This helps minimize degradation ofsignal quality due to package parasitics.
Figure 29. AC-Coupled Connection (STP)
Figure 30. AC-Coupled Connection (Coaxial)
8.1.4 Transmission MediaThe DS90UB933/934/964 chipset is intended to be used in a point-to-point configuration through a shieldedcoaxial cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities.The interconnect (cable and connectors) must have a differential impedance of 100 Ω, or a single-endedimpedance of 50 Ω. The maximum length of cable that can be used is dependent on the quality of the cable(gauge, impedance), connector, board(discontinuities, power plane), the electrical environment (for example,power stability, ground noise, input clock jitter, PCLK frequency, etc.). The resulting signal quality at the receivingend of the transmission media may be assessed by monitoring the differential eye opening of the serial datastream. A differential probe should be used to measure across the termination resistor at the CMLOUTP/N pins.
Contact TI for a channel specification regarding cable loss parameters and further details on adaptive equalizerloss compensation.
8.2.2.2 Detailed Design ProcedureFigure 36 shows a typical connection of a DS90UB933-Q1 Serializer using an STP interface.
Figure 36. STP Application Block Diagram
Eye diagrams in STP applications have roughly double the swing as with coax (Figure 33 and Figure 34).
9 Power Supply RecommendationsThis device is designed to operate from an input core voltage supply of 1.8 V. Some devices provide separatepower and ground terminals for different portions of the circuit. This is done to isolate switching noise effectsbetween different sections of the circuit. Separate planes on the PCB are typically not required. Pin descriptiontables typically provide guidance on which circuit blocks are connected to which power terminal pairs. In somecases, an external filter may be used to provide clean power to sensitive circuits such as PLLs. The voltageapplied on V(VDDIO) (1.8 V, 2.8 V, 3.3 V) or other power supplies making up V(VDD_n) (1.8 V) must be at the inputpin - any board level DC drop must be compensated (that is, ferrite beads in the path of the power supply rails).
10.1 Layout GuidelinesDesign circuit board layout and stack-up for the serializer/deserializer devices to provide low-noise power feed tothe device. Good layout practice also separates high frequency or high-level inputs and outputs to minimizeunwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved byusing thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitancefor the PCB power system with low-inductance parasitics, which has proven especially effective at highfrequencies, making the value and placement of external bypass capacitors less critical. External bypasscapacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in therange of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of thetantalum capacitors should be at least 5× the power supply voltage being used.
TI recommends surface mount capacitors due to their smaller parasitics. When using multiple capacitors persupply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of powerentry. This is typically in the 50-µF to 100-µF range and smooths low frequency switching noise. TI recommendsconnecting power and ground pins directly to the power and ground planes with bypass capacitors connected tothe plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypasscapacitor increases the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body sizereduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency ofthese external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiplecapacitors are often used to achieve low impedance between the supply rails over the frequency of interest. Athigh frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducingthe impedance at high frequency.
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noiseeffects between different sections of the circuit. Separate planes on the PCB are typically not required. PinDescription tables typically provide guidance on which circuit blocks are connected to which power pin pairs. Insome cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four-layer board with a power and ground plane. Locate LVCMOS signals away from thedifferential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differentiallines of 100 Ω are typically recommended for differential interconnect. The closely coupled lines help to ensurethat coupled noise appears as common-mode and thus is rejected by the receivers. The tightly coupled lines alsoradiate less.
Information on the WQFN package is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401).
10.1.1 Interconnect GuidelinesSee Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines for full details.• Use 100-Ω coupled differential pairs• Use the S/2S/3S rule in spacings
– – S = space between the pair– – 2S = space between pairs– – 3S = space to LVCMOS signal
• Minimize the number of Vias• Use differential connectors when operating above 500-Mbps line speed• Maintain balance of the traces• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TexasInstrument web site at: www.ti.com/lvds.
10.2 Layout ExampleStencil parameters such as aperture area ratio and the fabrication process have a significant impact on pastedeposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improveboard assembly yields. If the via and aperture openings are not carefully monitored, the solder may flowunevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in the following:
Figure 37. No Pullback WQFN, Single Row Reference Diagram
Table 11. No Pullback WQFN Stencil Aperture Summary for DS90UB933-Q1
Figure 38 and Figure 39 are derived from the layout design of the DS90UB933-Q1 evaluation module (EVM).The EVM is designed for coax operation. The trace carrying high-speed serial signal DOUT+ is critical and mustbe kept as short as possible. Burying this trace in an internal PCB layer may help reduce emissions. If Power-over-Coax is used, the stub must be minimized by placing the filter network as close as possible to the coaxconnector. These graphics and additional layout description are used to demonstrate both proper routing andproper solder techniques when designing in this serializer.
11.1.1 Related DocumentationFor related documentation see the following:• Understanding the I2C Bus• I2C Bus Pullup Resistor Calculation• Soldering Specifications Application Report,• IC Package Thermal Metrics Application Report,• AN-1187 Leadless Leadframe Package (LLP) Application Report• LVDS Owner's Manual
11.2 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.
11.3 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.
11.4 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
11.6 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
DS90UB933TRTVRQ1 ACTIVE WQFN RTV 32 2500 Green (RoHS& no Sb/Br)
CU SN Level-3-260C-168 HR -40 to 105 UB933Q
DS90UB933TRTVTQ1 ACTIVE WQFN RTV 32 250 Green (RoHS& no Sb/Br)
CU SN Level-3-260C-168 HR -40 to 105 UB933Q
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
DS90UB933TRTVRQ1 WQFN RTV 32 2500 367.0 367.0 35.0
DS90UB933TRTVTQ1 WQFN RTV 32 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-May-2017
Pack Materials-Page 2
MECHANICAL DATA
RTV0032A
www.ti.com
SQA32A (Rev B)
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to itssemiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyersshould obtain the latest relevant information before placing orders and should verify that such information is current and complete.TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integratedcircuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products andservices.Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and isaccompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduceddocumentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statementsdifferent from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for theassociated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designersremain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers havefull and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI productsused in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, withrespect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerousconsequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm andtake appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer willthoroughly test such applications and the functionality of such TI products as used in such applications.TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended toassist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in anyway, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resourcesolely for this purpose and subject to the terms of this Notice.TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TIproducts, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specificallydescribed in the published documentation for a particular TI Resource.Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications thatinclude the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISETO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTYRIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationregarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty orendorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES ORREPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TOACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OFMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUALPROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OFPRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES INCONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEENADVISED OF THE POSSIBILITY OF SUCH DAMAGES.Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, suchproducts are intended to help enable customers to design and create their own applications that meet applicable functional safety standardsand requirements. Using products in an application does not by itself establish any safety features in the application. Designers mustensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products inlife-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., lifesupport, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, allmedical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applicationsand that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatoryrequirements in connection with such selection.Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-compliance with the terms and provisions of this Notice.
![DS90UR90xQ-Q1 5- to 65-MHz, 24-bit Color FPD-Link II ...7:0] HS VS PCLK PDB Serializer Deserializer DE RGB Display QVGAto XGA RGB Digital Display Interface 24-bit color depth HOST](https://static.documents.pub/doc/80x56/5b47aff07f8b9a501f8cfc25/ds90ur90xq-q1-5-to-65-mhz-24-bit-color-fpd-link-ii-70-hs-vs-pclk-pdb-serializer.jpg)
