dvanced Packaging Technologies for MiniaturizedModules
Vinayak Pandey
VP, Product Technology Marketing, STATS ChipPAC
Form Factor Performance
Integration Low Cost
Analog Package Requirements
Analog Package Trends
fcQFN – FCOL/MIS
QFN-dr/mr
2L WB laminate/ 1L(Single Metal Su
eWLB – 1L RDL
QFN
QFP1L WB - MIS
1/2L FC - MIS
MIS can be used for leaded/laminate wirebond & flip chip packaging
eWLB drives superior performance and integration
Flip chip
Wirebond
Single Metal Substrate
Flip Chip on LeadFrame
Molded Interconnect Substrate/system
Embedded Wafer Level Ball Grid Array
MIS (Molded Interconnect System/Substrate)
Carrier
4
Pre-mold compound
Finish plating: NiPdAu, NiAu, Cu+OSP
Surface finish(Cu+OSP / NiAu/ NiPdAu)
1LMIS substrate 4B 250x70mm (0.11mm thickness)
Cross section view
Routable
External lead
Trace
1L MIS Process Flow
OR
MIS Design & Application
1LMIS 3.5x4.5-28L
(PM Application)Package thickness: 0.55mm
Lead pitch: 0.4mm
Bumping pitch: 0.25mm
Bump structure: Cu pillar bump with tin cap
Bump height: 90um (65um copper + 25um solder)
Bump size: 110um
Bump material: Sn/Ag 1.8
Cross section
fcQFN-1L MIS 3.5x4.5-28L
No delaminationPost MSL 1 / TCT 1500 cycles / uHAST 4
3D MIS Packaging
Characteristics• Passive components• Multi-chip module• 3D MIS substrate• Large area metal and
partial fine line/space
AdvantagesSuperior electrical and thermal performance
High reliability performance
Cross section view of
3D MIS packagingFlip chip on 3D MIS
Passive components
mounted on package top
3D MIS package for wearable
communication device
fcMISStructure:
Substrate thickness 0.12mmMin. Bump Pitch : 90 umCu column interconnectMolded Underfill
Readout point Le
TC’B’ 1000x w/ MSL3
SATImage
O/S test Passed (
TC’B’ 1000x w/ MSL2aa
SATImage
O/S test Passed (
Reliability Results:
Structure:substrate thickness 0.11mmMin. Bump Pitch : 80 umCu column interconnectMolded Underfill
Conventional Fan-in WLP (WLCSP)
Interconnect is limited to die size
Compact package size
Higher performance
Lower cost than BGAs or laminate based
CSPs
Silicon die Silicon die
Fan-out WLP (eWLB
Interconnect is independent of d
• Small package size
• Dramatically higher I/O count
• Strong thermal & electrical perform
• Able to integrate die from diverse
silicon nodes
• Cost effective advanced package
Wafer Level Packaging
Silicon die
eWLB provides the o
performance solu
increased I/O densit
Fine Cu Plated RDL 5/5um LW/LS
10µm
Ultra Th~0.3mm with
Integration with discrete and RDL inductor
• Small form factor
• Increased performance
• 2.5D/3D integration
• Cost effective solution
Si
3-L R
eWLB Capabilities
FOWLP is a versatile technology platformsemiconductor industry’s evolution from designs to 2.5D interposers and 3D IC in
Single chip eWLBeWLL
Flip Chip eWLB
3D eWLB with Interposer 3D Face-to-F
2.5D / Extended eWLB
eWLB-PoP (1.5S)
Multi-chip
FOWLP/eWLB Evolution
FOWLP breaks into New Frontiers!
by-Side: Multi-die and SiP applicationsAnalog + Logic package level integration HVM from 2012)
Functional partitioning -scale side-by-side Multichip
Alternative solution of 2.5D Interposer
Thinner Profile System Integra
Wide Range of SiP Offerings
1.5S Inverted FOWLP, a Disruptive Solution
Assembly Summary:
MEMS• Individually bumped and singulated
ASIC• Individually singulated and reconstituted with thru-vias• Followed by backgrind, redistribution and singulation
Pre-stack: ASIC and MEMS modules pre-stack and reflow
MEMS
ASIC
Thank You