EE365 Adv. Digital Circuit Design Clarkson University Lecture #3 Combinational Logic.

EE365Adv. Digital Circuit Design

Clarkson University

Lecture #3

Combinational Logic

Combinational-Circuit Analysis

• Combinational circuits -- outputs depend only on current inputs (not on history).

• Kinds of combinational analysis:– exhaustive (truth table)– algebraic (expressions)– simulation / test bench (example in lab #2)

• Write functional description in HDL• Define test conditions / test vecors, including corner cases• Compare circuit output with functional description (or

known-good realization)• Repeat for “random” test vectors

Rissacher EE365Lect #3

Combinational-Circuit Design

• Sometimes you can write an equation or equations directly using “logic” (the kind in your brain).

• Example (alarm circuit):

• Corresponding circuit:


Alarm-circuit transformation

• Sum-of-products form– Useful for programmable logic devices (next lec.)

• “Multiply out”:


Sum-of-products form

AND-OR

NAND-NAND


Product-of-sums form

OR-AND

NOR-NOR

P-of-S preferred in CMOS, TTL (NAND-NAND)


Brute-force design

• Truth table --> canonical sum (sum of minterms)

• Example:prime-number detector– 4-bit input, N3N2N1N0

row N3 N2 N1 N0 F 0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 0 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 0 9 1 0 0 1 010 1 0 1 0 011 0 0 1 1 112 1 1 0 0 013 1 1 0 1 114 1 1 1 0 015 1 1 1 1 0

F = (1,2,3,5,7,11,13)


Minterm list --> canonical sum


Algebraic simplification

• Theorem T8,

• Reduce number of gates and gate inputs


Resulting circuit


Visualizing T10 -- Karnaugh maps


3-variable Karnaugh map


Example: F = (1,2,5,7)


Karnaugh-map usage

• Plot 1s corresponding to minterms of function.• Circle largest possible rectangular sets of 1s.

– # of 1s in set must be power of 2– OK to cross edges

• Read off product terms, one per circled set.– Variable is 1 ==> include variable– Variable is 0 ==> include complement of variable– Variable is both 0 and 1 ==> variable not included

• Circled sets and corresponding product terms are called “prime implicants”

• Minimum number of gates and gate inputs


Prime-number detector (again)


Prime-number detector (again)

• When we solved algebraically, we missed one simplification -- the circuit below has three less gate inputs.


Another example


Yet another example

• Distinguished 1 cells• Essential prime implicants


POS

• Circle ‘0’s• Use DeMorgans to

invert the equation


F’ = (W’•Y•X)+(X’•Z’)

F = ((W’•Y•X)+(X’•Z’))’

F = (W’•Y•X)’•(X’•Z’)’

F = (W+Y’+X’)•(X+Z)

POS


• Note that the textbook author likes to draw the Karnaugh map for the F’ function, thus you would circle the ‘1’s (where my examples show the F function and ‘0’s are cirlced).

In-Class Practice Problem


Using Karnaugh maps, find the minimal SOP and POS terms for:

F=ΣW,X,Y,Z(0,2,5,7,8,10,13,15)



SOP: POS:

Z • X’

X • Z’

Quine-McCluskey algorithm

• This process can be made into a program, using appropriate algorithms and data structures.– Guaranteed to find “minimal” solution

• Required computation has exponential complexity (run time and storage)-- works well for functions with up to 8-12 variables, but quickly blows up for larger problems.

• Heuristic programs (e.g., Espresso) used for larger problems, usually give minimal results.


Lots of possibilities

• Can follow a “dual” procedure to find minimal products of sums (OR-AND realization)

• Can modify procedure to handle don’t-care input combinations.

• Can draw Karnaugh maps with up to six variables.


Real-World Logic Design

• Some applications have lots more than 6 inputs– can’t use Karnaugh maps

• Design correctness more important than gate minimization– Use “higher-level language” to specify logic

operations

• Use programs to manipulate logic expressions and minimize logic.

• PALASM, ABEL, CUPL -- developed for PLDs• VHDL, Verilog -- developed for ASICs


VHDL

• We will be using VHDL for all design projects• We generally won’t be using VHDL to help with

minimization, rather as a method to simulate simple logic circuits built with MSI components

• The following slides will cover the basic syntax of using VHDL for our purposes

• Program usage (e.g., Xilinx Modelsim) and program/circuit testing will be covered in a separate tutorial


VHDL Topics

• Objectives• VHDL History• Application Areas• Design Units• Entity Descriptions• Architecture Descriptions• Package and Package Body• Configuration• A Range of Design Examples


VHDL Topics

• Levels of Abstraction• Architecture Types• Modeling Behavior• Modeling Structure• Examples• Test Benches• Design Process – overview and summary


Objectives

• Introduce the basics of VHDL.• Gain a level of understanding that allows you

to write VHDL code for any design that you could enter using a schematic editor and standard parts.

• Develop an appreciation for the ability of VHDL to handle “mixed” designs (structural, dataflow, and behavioral).

• Learn VHDL at a level that would allow you to realize your designs in CPLD or FPGA circuits and to test them.


VHDL History

• VHSIC Hardware Design Language– Very High Speed Integrated Circuit– DoD sponsored development, thus

non-proprietary language

• Standardized by the IEEE in 1987• IEEE Standard Logic Package (1164) added

to handle simulation of practical digital signal values (e.g. high impedance, pull-ups, etc.)

• VHDL standard extended in 1993• Additional standards and enhancements

continue


Application Areas for VHDL

• System Specification• Design Entry (capture)• Simulation• Synthesis (and fitting)• Test Development• Timing Verification• Documentation


VHDL Design Unit

• A set of VHDL statements that can be compiled separately and stored in a library for later use.

• Five types of design units:– Entity description– Architecture description– Package– Package body– Configuration


Entity Description

• Describes the input and output of one module in a system.

• Hides the detailed “inner workings” of the module

• May be used to describe modules at a very low level (e.g. gate level) as well as an entire system, and all levels in between


Modeling Interfaces

• Entity declaration– describes the input/output ports of a module

entity reg4 isport ( d0, d1, d2, d3, en, clk : in

bit;q0, q1, q2, q3 : out bit );

end entity reg4;

entity name port names port mode (direction)

port typereserved words

punctuation


VHDL-87

• Omit entity at end of entity declaration

entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;

q0, q1, q2, q3 : out bit );end reg4;


Architecture Description

• Provides a functional or structural description of an entity.

• Each architecture is bound to only one entity – but an entity may be associated with multiple architectures (only one during any given simulation or synthesis).

• Multiple architectures allow for early descriptions of module performance without having to design everything in order to begin functional testing.


Package and Package Body

• Provides a common place to gather globally used declarations of constants, signals, functions, procedures, components, etc.

• Package body contains the VHDL code for any functions or procedures declared in the package.

• Contents of a package are made available to other design units via the use statement.


Configuration

• Specifies which architectures are to be used for entities.

• Always optional; a default configuration is always provided.

• Generally not used for synthesis, but for functional simulation.


A Range of Design Examples

• A simple, single part design:– One VHDL source file with an

entity – architecture pair and a reference to a standard library (e.g. IEEE Standard Logic).

• A more complex design:– Multiple source files, each with an entity

architecture pair or with a package declaration.– User as well as standard libraries.– May include a configuration file.


Levels of Abstraction

• An important characteristic of VHDL that is not shared by earlier, PLD type languages (such as ABEL, CUPL, etc.) is the ability to represent designs at multiple levels of abstraction.

• Example – a 16 bit adder could be represented as:– Interconnections of gates– Interconnections of modules (e.g. full adder or 4-

bit adder)– A function that performs binary addition on two

vectors of bits


Architecture Types

• Behavioral– Describes module performance over time, typically

in the form of an algorithm.– Ability to synthesize directly is limited.

• Dataflow (Register Transfer)– Specifies registers and combinational logic in

terms of data flowing from one function to another.

• Structural– Specifies the components and their

interconnections– HDL equivalent of a schematic


Modeling Behavior

• Architecture body– describes an implementation of an entity– may be several per entity

• Behavioral architecture– describes the algorithm performed by the module– contains

• process statements, each containing• sequential statements, including• signal assignment statements and• wait statements


Behavior Example

architecture behav of reg4 isbegin

storage : process isvariable stored_d0, stored_d1, stored_d2, stored_d3 : bit;

beginif en = '1' and clk = '1' then

stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3;

end if;q0 <= stored_d0 after 5 ns;

q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns;

wait on d0, d1, d2, d3, en, clk;end process storage;

end architecture behav;


VHDL-87

• Omit architecture at end of architecture body• Omit is in process statement header

architecture behav of reg4 isbegin

storage : process...

begin...

end process storage;end behav;


Modeling Structure

• Structural architecture– implements the module as a composition of

subsystems– contains

• signal declarations, for internal interconnections– the entity ports are also treated as signals

• component instances– instances of previously declared entity/architecture

pairs• port maps in component instances

– connect signals to component ports• wait statements


Structural Architecture

• Components declared in an architecture must be defined elsewhere.

• Components may defined as:– an entity-architecture pair in the same VHDL

source file,– an entity-architecture pair in another VHDL source

file,– an object in another design tool and supplied in a

standard file format,– an object in a technology library



• Each component type must be declared using a component declaration.

• The component declaration must match the entity declaration of the module being used.

component component-name

port ( signal-names : mode signal-type;

signal-names : mode signal-type;

…

signal-names : mode signal-type );

end component;



• Each instance of a component must be instantiated by a component statement.

• First form uses order of signals matched to the component declaration.

• Second form uses port names as listed in the component declaration.

label: component-name port map (signal1, signal2, …, signaln);

OR

label: component-name port map (port1=>signal1, port2=>signal2, portn=>signaln):


Structure Example

int_clk

d0

d1

d2

d3

en

clk

q0

q1

q2

q3

bit0

d_latch

d

clk

q

bit1

d_latch

d

clk

q

bit2

d_latch

d

clk

q

bit3

d_latch

d

clk

q

gate

and2

a

b

y


Structure Example

• Include component declarations in structural architecture body

• templates for entity declarations

– instantiate components– write a configuration declaration

• optional, only if more than one architecture is specified for a given entity.

• binds entity/architecture pair to each instantiated component


• First declare D-latch and and-gate entities and architectures

entity d_latch isport ( d, clk : in bit; q : out bit );

end d_latch;

architecture basic of d_latch isbegin

latch_behavior : processbegin

if clk = ‘1’ thenq <= d after 2 ns;

end if;wait on clk, d;

end process latch_behavior;

end basic;

entity and2 isport ( a, b : in bit; y : out bit );

end and2;

architecture basic of and2 isbegin

and2_behavior : processbegin

y <= a and b after 2 ns;wait on a, b;

end process and2_behavior;

end basic;

Structure Example


• Declare corresponding components in register architecture body

architecture struct of reg4 is

component d_latchport ( d, clk : in bit; q : out bit );

end component;

component and2port ( a, b : in bit; y : out bit );

end component;

signal int_clk : bit;

...

Structure Example


Structure Example

• Now use them to implement the register

...

begin

bit0 : d_latchport map ( d0, int_clk, q0 );




gate : and2port map ( en, clk, int_clk );

end struct;


Mixed Behavior and Structure

• An architecture can contain both behavioral and structural parts– process statements and component instances

• collectively called concurrent statements

– processes can read and assign to signals

• Example: register-transfer-level model– data path described structurally– control section described behaviorally



• We want to write VHDL code for a buffer.• Write an Entity for an Architecture that would

take a single binary value, A, as an input, then pass it to the output, W, after 20ns.



entity buffer is

port (A : in bit;

W : out bit);

end buffer;



• Now write the behavioral Architecture• Write an Architecture that would take a single

binary value, A, as an input, then pass it to the output, W, after 20ns.



architecture basic of buffer is

begin

W <= A after 20 ns;

end basic;



• Now create another instance of the same entity by writing a similar Architecture that only has a 5ns delay.



architecture fast of buffer is

begin

W <= A after 5 ns;

end fast;


Test Benches

• Testing a design by simulation• Use a test bench model

– an architecture body that includes an instance of the design under test

– applies sequences of test values to inputs– monitors values on output signals

• either using simulator• or with a process that verifies correct operation


Test Bench Example

entity test_bench isend entity test_bench;

architecture test_reg4 of test_bench is

signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;

begin

dut : entity work.reg4(behav)port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );

stimulus : process isbegin

d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns;en <= ’1’; wait for 20 ns;clk <= ’1’; wait for 20 ns;d0 <= ’0’; d1 <= ’0’; d2 <= ’0’; d3 <= ’0’; wait for 20 ns;en <= ’0’; wait for 20 ns;…wait;

end process stimulus;

end architecture test_reg4;


Regression Testing

• Test that a refinement of a design is correct– that lower-level structural model does the same as

a behavioral model

• Test bench includes two instances of design under test– behavioral and lower-level structural– stimulates both with same inputs– compares outputs for equality

• Need to take account of timing differences


Design Processing

• Analysis• Elaboration• Simulation• Synthesis


Analysis

• Check for syntax and semantic errors– syntax: grammar of the language– semantics: the meaning of the model

• Analyze each design unit separately– entity declaration– architecture body– …– best if each design unit is in a separate file

• Analyzed design units are placed in a library– in an implementation dependent internal form– current library is called work


Elaboration

• “Flattening” the design hierarchy– create ports– create signals and processes within architecture

body– for each component instance, copy instantiated

entity and architecture body– repeat recursively

• bottom out at purely behavioral architecture bodies

• Final result of elaboration– flat collection of signal nets and processes


Elaboration Example

int_clk

d0

d1

d2

d3

en

clk

q0

q1

q2

q3

bit0

d_latch

d

clk

q

bit1

d_latch

d

clk

q

bit2

d_latch

d

clk

q

bit3

d_latch

d

clk

q

gate

and2

a

b

y

reg4(struct)


Elaboration Example

int_clk

d0

d1

d2

d3

en

clk

q0

q1

q2

q3

bit0

bit1

bit2

bit3

gate

reg4(struct)d_latch(basic)

d

clk

q

d_latch(basic)

d

clk

q

d_latch(basic)

d

clk

q

d_latch(basic)

d

clk

q

and2(basic)

a

b

yprocess with variables

and statements


Simulation

• Execution of the processes in the elaborated model

• Discrete event simulation– time advances in discrete steps– when signal values change—events

• A processes is sensitive to events on input signals– specified in wait statements– resumes and schedules new values on output

signals• schedules transactions• event on a signal if new value different from old value


Simulation Algorithm

• Initialization phase– each signal is given its initial value– simulation time set to 0– for each process

• activate• execute until a wait statement, then suspend

–execution usually involves scheduling transactions on signals for later times


Simulation Algorithm

• Simulation cycle– advance simulation time to time of next transaction– for each transaction at this time

• update signal value– event if new value is different from old value

– for each process sensitive to any of these events, or whose “wait for …” time-out has expired

• resume• execute until a wait statement, then suspend

• Simulation finishes when there are no further scheduled transactions


Synthesis

• Translates register-transfer-level (RTL) design into gate-level netlist

• Restrictions on coding style– Some constructs are not synthesizable– Some constructs are synthesized in inefficient ways

– better to force the design to a lower, simpler level


Basic Design Methodology

Requirements

SimulateRTL Model

Gate-levelModel

Synthesize

Simulate Test Bench

ASIC or FPGA Place & Route

TimingModel Simulate


How we’ll Simulate


• We won’t worry about writing test benchs• We’ll be using a program called “Wave” (within

Xilinx Modelsim) to look at inputs and outputs of the systems we build

• A GUI is provided to edit input patterns

More VHDL Help

• Link on course website

Rissacher EE365Lect #3 Rissacher EE365Lect #3

Next time

• VHDL tutorial in Computer Lab• Quiz

• Transistor-Level Logic Circuits• CMOS• TTL

Rissacher EE365Lect #3 Rissacher EE365Lect #3

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EE365 Adv. Digital Circuit Design Clarkson University Lecture #3 Combinational Logic.

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