EE4800 CMOS Digital IC Design & Analysis · 2011-10-11 · Outline Introduction to SPICE DC...

EE4800 CMOS Digital IC Design & Analysis

Lecture 7 Spice SimulationZhuo Feng

Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis7.7.11

Outline■ Introduction to SPICE■ DC Analysis■ DC Analysis■ Transient Analysis■ Subcircuits■ Subcircuits■ Optimization■ Power Measurement■ Power Measurement■ Logical Effort Characterization


Introduction to SPICE■ Simulation Program with Integrated Circuit Emphasis

► Developed in 1970’s at Berkeley► Many commercial versions are available► HSPICE is a robust industry standard

▼Has many enhancements that we will usey

■ Written in FORTRAN for punch-card machines► Circuits elements are called cards► C l t d i ti i ll d SPICE d k► Complete description is called a SPICE deck


Writing Spice Decksg■ Writing a SPICE deck is like writing a good program

► Plan: sketch schematic on paper or in editor▼Modify existing decks whenever possible

► Code: strive for clarity▼Start with name, email, date, purpose▼Generously comment

► Test:▼Predict what results should be▼Compare with actual▼Garbage In, Garbage Out!


Example: RC Circuit* rc.sp* [email protected] 2/2/03* Find the response of RC circuit to rising input

R1 = 2K*------------------------------------------------* Parameters and models*------------------------------------------------.option post

R1 2K

C1 =100fF

Vin+

Vout-

*------------------------------------------------* Simulation netlist*------------------------------------------------Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8R1 in out 2kR1 in out 2kC1 out gnd 100f

*------------------------------------------------* Stimulus*------------------------------------------------.tran 20ps 800ps.plot v(in) v(out).end


Result (Textual)legend:

a: v(in)b: v(out)

time v(in)(ab ) 0. 500.0000m 1.0000 1.5000 2.0000

+ + + + + 0 0 2 + + + + + + + +0. 0. -2------+------+------+------+------+------+------+------+-

20.0000p 0. 2 + + + + + + + + 40.0000p 0. 2 + + + + + + + + 60.0000p 0. 2 + + + + + + + + 80.0000p 0. 2 + + + + + + + + 100.0000p 0. 2 + + + + + + + + 120.0000p 720.000m +b + + a+ + + + + + 140.0000p 1.440 + b + + + + + a + + + 160.0000p 1.800 + +b + + + + + +a + 180 0000p 1 800 + + b + + + + + +a +180.0000p 1.800 + + b + + + + + +a + 200.0000p 1.800 -+------+------+b-----+------+------+------+------+a-----+-220.0000p 1.800 + + + b + + + + +a + 240.0000p 1.800 + + + +b + + + +a + 260.0000p 1.800 + + + + b + + + +a + 280.0000p 1.800 + + + + b+ + + +a + 300.0000p 1.800 + + + + +b + + +a + 320.0000p 1.800 + + + + + b + + +a + 340.0000p 1.800 + + + + + b + + +a + 360.0000p 1.800 + + + + + b + +a + p380.0000p 1.800 + + + + + +b + +a + 400.0000p 1.800 -+------+------+------+------+------+--b---+------+a-----+-420.0000p 1.800 + + + + + + b + +a + 440.0000p 1.800 + + + + + + b + +a + 460.0000p 1.800 + + + + + + b+ +a + 480.0000p 1.800 + + + + + + b +a + 500.0000p 1.800 + + + + + + +b +a + 520.0000p 1.800 + + + + + + +b +a + 540.0000p 1.800 + + + + + + + b +a + 560.0000p 1.800 + + + + + + + b +a + 580.0000p 1.800 + + + + + + + b +a + 600.0000p 1.800 -+------+------+------+------+------+------+---b--+a-----+-620.0000p 1.800 + + + + + + + b +a + 640.0000p 1.800 + + + + + + + b +a + 660.0000p 1.800 + + + + + + + b +a + 680.0000p 1.800 + + + + + + + b +a + 700.0000p 1.800 + + + + + + + b+a + 720.0000p 1.800 + + + + + + + b+a +


740.0000p 1.800 + + + + + + + b+a + 760.0000p 1.800 + + + + + + + b+a + 780.0000p 1.800 + + + + + + + ba + 800.0000p 1.800 -+------+------+------+------+------+------+------ba-----+-

+ + + + +

Result (Graphical)

2.0 v(in)

1.5

v(out)

1.0

0.5

t(s)0.0 100p 200p 300p 400p 500p 600p 700p 800p 900p

0.0


t(s)

Sources■ DC Source

Vdd vdd gnd 2.5

■ Piecewise Linear SourceVin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8

■ Pulsed SourceVck clk gnd PULSE 0 1.8 0ps 100ps 100ps 300ps 800ps

PULSE v1 v2 td tr tf pw per

v2

td tr tfpw

v1 per


SPICE Elements

Letter ElementR ResistorC CapacitorL InductorK Mutual Inductorutua ductoV Independent voltage sourceI Independent current sourceM MOSFETD Di dD DiodeQ Bipolar transistorW Lossy transmission lineX SubcircuitE Voltage-controlled voltage sourceG Voltage-controlled current sourceH Current-controlled voltage sourceF Current controlled current source


F Current-controlled current source

Units

Letter Unit Magnitudea atto 10-18

f fempto 10-15

p pico 10-12p pico 10n nano 10-9

u micro 10-6

m mili 10-3

k kilo 103

x mega 106x mega 106

g giga 109

Ex: 100 femptofarad capacitor = 100fF, 100f, 100e-15


Ex: 100 femptofarad capacitor 100fF, 100f, 100e 15

DC Analysisy* mosiv.sp

*------------------------------------------------* Parameters and models Ids*------------------------------------------------.include '../models/tsmc180/models.sp'.temp 70.option post

ds

4/2

*------------------------------------------------* Simulation netlist*------------------------------------------------*nmosVgs g gnd 0

Vgs Vds

Vgs g gnd 0Vds d gnd 0M1 d g gnd gnd NMOS W=0.36u L=0.18u

*------------------------------------------------* Stimulus Stimulus*------------------------------------------------.dc Vds 0 1.8 0.05 SWEEP Vgs 0 1.8 0.3.end


I-V Characteristics■ NMOS I-V

►Vgs dependence

200

250

Vgs = 1.8

►Vgs dependence►Saturation

Ids(A)

150

Vgs = 1.5

Vgs = 1.2

50

100gs

Vgs = 0.9

Vds

0.0 0.3 0.6 0.9 1.2 1.5 1.80

Vgs = 0.6


MOSFET ElementsM element for MOSFET

Mname drain gate source body type+ W=<width> L=<length>+ AS=<area source> AD = <area drain> + PS=<perimeter source> PD=<perimeter drain>


Transient Analysisy* inv.sp

* Parameters and models*------------------------------------------------

SUPPLY 1 8

8/2.param SUPPLY=1.8.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post

a y

4/2* Simulation netlist*------------------------------------------------Vdd vdd gnd 'SUPPLY'Vin a gnd PULSE 0 'SUPPLY' 50ps 0ps 0ps 100ps 200psM1 y a gnd gnd NMOS W=4 L=2 + AS=20 PS=18 AD=20 PD=18M2 y a vdd vdd PMOS W=8 L=2+ AS=40 PS=26 AD=40 PD=26

* Stimulus*------------------------------------------------.tran 1ps 200ps.end


Transient Results■ Unloaded inverter

► Overshoot

v(a)

v(y)

► Very fast edges

(V) 1 0tf = 10ps

1.44

1.8

(V) 1.0tpdr = 15pstpdf = 12ps

tr = 16ps

0.36

0.0

0.0 50p 100p 150p 200p


t(s)p p p p

Subcircuits■ Declare common elements as subcircuits

.subckt inv a y N=4 P=8yM1 y a gnd gnd NMOS W='N' L=2 + AS='N*5' PS='2*N+10' AD='N*5' PD='2*N+10'M2 y a vdd vdd PMOS W='P' L=2+ AS 'P*5' PS '2*P+10' AD 'P*5' PD '2*P+10'+ AS='P*5' PS='2*P+10' AD='P*5' PD='2*P+10'.ends

■ Ex: Fanout-of-4 Inverter Delay► Reuse inv► Shaping

S

DeviceUnder Load on► Shaping

► Loadinga b c d eX1 X2 X3 X4

1

2

4

8

16

32

64

128 fX5256

512

Shape input Test Load Load


1 4 16 64 256

FO4 Inverter Delayy* fo4.sp

* Parameters and models*----------------------------------------------------------------------*.param SUPPLY=1.8.param H=4.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post

* Subcircuits*----------------------------------------------------------------------.global vdd gnd.include '../lib/inv.sp'

* Simulation netlist*----------------------------------------------------------------------Vdd vdd gnd 'SUPPLY'Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000psX1 a b inv * shape input waveformX2 b c inv M='H' * reshape input waveform


FO4 Inverter Delay Cont.yX3 c d inv M='H**2' * device under testX4 d e inv M='H**3' * loadx5 e f inv M='H**4' * load on load

* Stimulus*----------------------------------------------------------------------.tran 1ps 1000ps.measure tpdr * rising prop delay+ TRIG v(c) VAL='SUPPLY/2' FALL=1 + TARG v(d) VAL='SUPPLY/2' RISE=1.measure tpdf * falling prop delay+ TRIG v(c) VAL='SUPPLY/2' RISE=1+ TARG v(d) VAL='SUPPLY/2' FALL=1+ TARG v(d) VAL SUPPLY/2 FALL 1 .measure tpd param='(tpdr+tpdf)/2' * average prop delay.measure trise * rise time+ TRIG v(d) VAL='0.2*SUPPLY' RISE=1+ TARG v(d) VAL='0.8*SUPPLY' RISE=1

tf ll * f ll ti.measure tfall * fall time+ TRIG v(d) VAL='0.8*SUPPLY' FALL=1+ TARG v(d) VAL='0.2*SUPPLY' FALL=1.end


FO4 Results2.0 a

b

1.5 c

d

(V)1.0

e

ftpdf = 66ps tpdr = 83ps

0 0

0.5

0.0

t(s)0.0 200p 400p 600p 800p 1n


t(s)

Optimization■ HSPICE can automatically adjust parameters

► Seek value that optimizes some measurement

■ Example: Best P/N ratio► We’ve assumed 2:1 gives equal rise/fall delays► But we see rise is actually slower than fall► But we see rise is actually slower than fall► What P/N ratio gives equal delays?

■ Strategies► (1) run a bunch of sims with different P size► (2) let HSPICE optimizer do it for us


P/N Optimization* fo4opt.sp

* Parameters and models*----------------------------------------------------------------------.param SUPPLY=1.8.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.temp 70.option post

* Subcircuits*----------------------------------------------------------------------.global vdd gnd.global vdd gnd.include '../lib/inv.sp'

* Simulation netlist*----------------------------------------------------------------------Vdd vdd gnd 'SUPPLY'Vdd vdd gnd SUPPLYVin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000psX1 a b inv P='P1' * shape input waveformX2 b c inv P='P1' M=4 * reshape inputX3 c d inv P='P1' M=16 * device under test


P/N OptimizationX4 d e inv P='P1' M=64 * loadX5 e f inv P='P1' M=256 * load on load

* Optimization setup*----------------------------------------------------------------------.param P1=optrange(8,4,16) * search from 4 to 16, guess 8.model optmod opt itropt=30 * maximum of 30 iterations

/ /.measure bestratio param='P1/4' * compute best P/N ratio

* Stimulus*----------------------------------------------------------------------.tran 1ps 1000ps SWEEP OPTIMIZE=optrange RESULTS=diff MODEL=optmod

d * i i i d l.measure tpdr * rising propagation delay+ TRIG v(c)VAL='SUPPLY/2' FALL=1 + TARG v(d) VAL='SUPPLY/2' RISE=1.measure tpdf * falling propagation delay+ TRIG v(c) VAL='SUPPLY/2' RISE=1( ) /+ TARG v(d) VAL='SUPPLY/2' FALL=1 .measure tpd param='(tpdr+tpdf)/2' goal=0 * average prop delay.measure diff param='tpdr-tpdf' goal = 0 * diff between delays.end


P/N Results■ P/N ratio for equal delay is 3.6:1

► tpd = tpdr = tpdf = 84 ps (slower than 2:1 ratio)p p p

► Big pMOS transistors waste power too► Seldom design for exactly equal delays

■ What ratio gives lowest average delay?■ What ratio gives lowest average delay?

.tran 1ps 1000ps SWEEP OPTIMIZE=optrange RESULTS=tpd MODEL=optmod

► P/N ratio of 1.4:1► tpdr = 87 ps, tpdf = 59 ps, tpd = 73 ps


Power Measurement■ HSPICE can measure power

► Instantaneous P(t)( )►Or average P over some interval

print P(vdd).print P(vdd).measure pwr AVG P(vdd) FROM=0ns TO=10ns

■ Power in single gate►Connect to separate VDD supply►Be careful about input power


Logical Effortg■ Logical effort can be measured from simulation

► As with FO4 inverter, shape input, load output

Device

Shape input

DeviceUnderTest Load

Load onLoad

X1 X2 X3 X4 X5

a b c d efM=1 M=h X5 fM=h M=h2

M=h3M=h4


Logical Effort Plotsg■ Plot tpd vs. h

► Normalize by = 15 ps► y-intercept is parasitic delay► Slope is logical effort

■ Delay fits straight line 160

180

15 ps

■ Delay fits straight linevery well in any processas long as input slope is

80100

120

140

dabsg p pconsistent

20

40

60

80

00 2 4 6 8 10

h


Logical Effort Datag■ For NAND gates in TSMC 180 nm process:

Notes:■ Notes:► Parasitic delay is greater for outer input► Average logical effort is better than estimated


Comparisonp


■ SPICE overview►N equations in terms of N unknown Node voltages►More generally using modified nodal analysis

G(v)i vv vR

G(v)i 1v2v 4vC

R

v

3v


Time Domain Equations at node 1:Time Domain Equations at node 1:

0)()()(12

4131 vvGR

vvdt

vvdC

If we do this for all N nodes:

0))(),(),(( tutxtxF Xx

)0(

N dimensional vector of unknownnode voltages

)(tx

vector of independent sources

nonlinear operator

)(tu

F


nonlinear operatorF

■ Closed form solution is not possible for bit d f diff ti l tiarbitrary order of differential equations

■ We must approximate the solution of:

0))(),(),(( tutxtxF Xx

)0(

■ This is facilitated in SPICE via numerical solutions


■ Basic circuit analyses►(Nonlinear) DC analysis

▼Finds the DC operating point of the circuit▼Solves a set of nonlinear algebraic eqnsg q

►AC analysis▼Performs frequency domain small signal analysis▼Performs frequency-domain small-signal analysis▼Require a preceding DC analysis▼Solves a set of complex linear eqns

►(Nonlinear) transient analysis▼Computes the time-domain circuit transient response▼Solves a set of nonlinear different eqns▼Converts to a set nonlinear algebraic of eqns using

numerical integration


■ SPICE offers practical techniques to solve circuit problems in time & freq domainsproblems in time & freq. domains

► Interface to device models▼Transistors diodes nonlinear caps etc▼Transistors, diodes, nonlinear caps etc

► Sparse linear solver

► Nonlinear solver – Newton-Raphson method

► N merical integration► Numerical integration

► Convergence & time-step control


■ Circuit equations are usually formulated iusing

►Nodal analysis y▼N equations in N nodal voltages

►Modified analysis►Modified analysis▼Circuit unknowns are nodal voltages & some branch

currents▼Branch current variables are added to handle▼Branch current variables are added to handle

– Voltages sources– Inductors– Current controlled voltage source etcCurrent controlled voltage source etc

■ Formulations can be done in both time d f


and frequency

How do we set up a matrix problem given a list ofHow do we set up a matrix problem given a list oflinear(ized) circuit elements?

Similar to reading a netlist for a linear circuit:

* Element Name From To Value

I 0 1 1mA

2

1

1

RRI

110

201

5101mA

3

2

RR

21

02

1005


R 52R

R

51 2

1I 1R 3RmA1 10010

0

The nodal analysis matrix equations areeasily constructed via KCL at each node:easily constructed via KCL at each node:

JvY


■ Naïve approach) C f► a) Write down the KCL eqn for each node

► b) Combine all of them to a get N eqns in N node voltages

■ Intuitive for hand analysis

■ Computer programs use a more convenient p p g“element” centric approach► Element stamps


Instead of converting the netlist into a graph and g g pwriting KCL eqns, stamp in elements one at a time:

Stamps: add to existing matrix entries

RR11 From

row ii

Y

RR11 To

row j jRY

Fromcol.

Tocol. i j


RHS of equations are stamped in a similar way:J

i

II

i

jI

From row

To

ij I j

row j


Stamping our simple example one l t t tielement at a time:

1001110

1

1

RmAI

10002521

3

2

1

RR

IVGGG

01

2

1

322

221 IVV

GGGGGG


We know that nonlinear elements are firstconverted to linear components, then stamped

EQI EQGQ Q


For 3 & 4 terminal elements we know that the linearized models have linear controlled sources

D DG

Gdsvgsv

gsmvg dsr

S S

We can stamp in MOSFETs in terms of a completestamp or in terms of simpler element stamps


stamp, or in terms of simpler element stamps

Voltage controlled current source

kv 0I

kkvgi

p

kv 0I

kmvgi

q

Voltmeter

gg prow

mm

mm

gggg p

qrow

row

k colcol


Large value that does not fall on diagonal of Y!

All other types of controlled sources include All other types of controlled sources includevoltage sources

Voltage sources are inherently incompatiblewith nodal analysis

Grounded voltages sources are easily accommodated Grounded voltages sources are easily accommodated

21 v1

v2

21

2

1

vv

0

v2

2v


0

But a voltage source in between nodes is gmore difficult

k k

Node voltages and are not independentk


We no longer have N independent node voltageg p gvariables

So we can potentially eliminate one equation p y qand one variable (section 2.3 of reference [1])

But the more popular solution is modified nodal ut the more popular solution is modified nodalanalysis (MNA)

Vk

iCreate one extra variable and one extra equation


Extra variable: voltage source current

Allows us to write KCL at nodes andk

Extra equation

Vvvk

Advantage: now have an easy way of printing

Vvvk

Advantage: now have an easy way of printingcurrent results - - ammeter


Voltage source stamp:

11

row

row k

Vi011

1row

row 1N

col colcolk 1N


Current-controlled current source (e g BJT) has to Current-controlled current source (e.g. BJT) has to stamp in an ammeter and a controlled current source

ii i 12 ii 1i


In general we would not blindly build the matrixIn general, we would not blindly build the matrixfrom an input netlist and then attempt to solve it

Various illegal ckts are possible:

Cutsets of current sources


Loops of voltage sourcesLoops of voltage sources

Dangling nodes


■ Once we efficiently formulate MNA equations, an efficient solution to is even more importantJY

solution to is even more importantJvY

■ For large ckts the matrix is really sparse► Number of entries in Y is a function of number of elements

connected to the corresponding node

■ Inverting a sparse matrix is never a good idea since the inverse is not sparse!

■ Instead direct solution methods employ Gaussian Elimination or LU factorization


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EE4800 CMOS Digital IC Design & Analysis · 2011-10-11 · Outline Introduction to SPICE DC...

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